홈 마이크로컨트롤러(MCU) 및 프로세서 DSP(디지털 신호 프로세서)
홈
마이크로컨트롤러(MCU) 및 프로세서
DSP(디지털 신호 프로세서)

TMS320VC33

활성

C30x 부동 소수점 DSP

지금 주문
데이터시트

TMS320VC33

활성
데이터시트 지금 주문

제품 상세 정보

DSP type 1 C3x DSP (max) (MHz) 75 CPU 32-bit Rating Catalog Operating temperature range (°C) 0 to 0
DSP type 1 C3x DSP (max) (MHz) 75 CPU 32-bit Rating Catalog Operating temperature range (°C) 0 to 0
LQFP (PGE) 144 484 mm² 22 x 22
  • High-Performance Floating-Point Digital Signal Processor (DSP):
    • TMS320VC33-150
      • 13-ns Instruction Cycle Time
      • 150 Million Floating-Point Operations Per Second (MFLOPS)
      • 75 Million Instructions Per Second (MIPS)
    • TMS320VC33-120
      • 17-ns Instruction Cycle Time
      • 120 MFLOPS
      • 60 MIPS
  • 34K × 32-Bit (1.1-Mbit) On-Chip Words of Dual-Access Static Random-Access Memory (SRAM) Configured in 2 × 16K Plus 2 × 1K Blocks to Improve Internal Performance
  • x5 Phase-Locked Loop (PLL) Clock Generator
  • Very Low Power: < 200 mW @ 150 MFLOPS
  • 32-Bit High-Performance CPU
  • 16-/32-Bit Integer and 32-/40-Bit Floating-Point Operations
  • Four Internally Decoded Page Strobes to Simplify Interface to I/O and Memory Devices
  • Boot-Program Loader
  • EDGEMODE Selectable External Interrupts
  • 32-Bit Instruction Word, 24-Bit Addresses
  • Eight Extended-Precision Registers
  • On-Chip Memory-Mapped Peripherals:
    • One Serial Port
    • Two 32-Bit Timers
    • Direct Memory Access (DMA) Coprocessor for Concurrent I/O and CPU Operation
  • Fabricated Using the 0.18-µm (leff-Effective Gate Length) TImeline™ Technology by Texas Instruments (TI)
  • 144-Pin Low-Profile Quad Flatpack (LQFP) (PGE Suffix)
  • Two Address Generators With Eight Auxiliary Registers and Two Auxiliary Register Arithmetic Units (ARAUs)
  • Two Low-Power Modes
  • Two- and Three-Operand Instructions
  • Parallel Arithmetic/Logic Unit (ALU) and Multiplier Execution in a Single Cycle
  • Block-Repeat Capability
  • Zero-Overhead Loops With Single-Cycle Branches
  • Conditional Calls and Returns
  • Interlocked Instructions for Multiprocessing Support
  • Bus-Control Registers Configure Strobe-Control Wait-State Generation
  • 1.8-V (Core) and 3.3-V (I/O) Supply Voltages
  • On-Chip Scan-Based Emulation Logic, IEEE Std 1149.1 (JTAG)

IEEE Standard 1149.1-1990 Standard-Test-Access Port
TImeline is a trademark of Texas Instruments.
Other trademarks are the property of their respective owners.
  • High-Performance Floating-Point Digital Signal Processor (DSP):
    • TMS320VC33-150
      • 13-ns Instruction Cycle Time
      • 150 Million Floating-Point Operations Per Second (MFLOPS)
      • 75 Million Instructions Per Second (MIPS)
    • TMS320VC33-120
      • 17-ns Instruction Cycle Time
      • 120 MFLOPS
      • 60 MIPS
  • 34K × 32-Bit (1.1-Mbit) On-Chip Words of Dual-Access Static Random-Access Memory (SRAM) Configured in 2 × 16K Plus 2 × 1K Blocks to Improve Internal Performance
  • x5 Phase-Locked Loop (PLL) Clock Generator
  • Very Low Power: < 200 mW @ 150 MFLOPS
  • 32-Bit High-Performance CPU
  • 16-/32-Bit Integer and 32-/40-Bit Floating-Point Operations
  • Four Internally Decoded Page Strobes to Simplify Interface to I/O and Memory Devices
  • Boot-Program Loader
  • EDGEMODE Selectable External Interrupts
  • 32-Bit Instruction Word, 24-Bit Addresses
  • Eight Extended-Precision Registers
  • On-Chip Memory-Mapped Peripherals:
    • One Serial Port
    • Two 32-Bit Timers
    • Direct Memory Access (DMA) Coprocessor for Concurrent I/O and CPU Operation
  • Fabricated Using the 0.18-µm (leff-Effective Gate Length) TImeline™ Technology by Texas Instruments (TI)
  • 144-Pin Low-Profile Quad Flatpack (LQFP) (PGE Suffix)
  • Two Address Generators With Eight Auxiliary Registers and Two Auxiliary Register Arithmetic Units (ARAUs)
  • Two Low-Power Modes
  • Two- and Three-Operand Instructions
  • Parallel Arithmetic/Logic Unit (ALU) and Multiplier Execution in a Single Cycle
  • Block-Repeat Capability
  • Zero-Overhead Loops With Single-Cycle Branches
  • Conditional Calls and Returns
  • Interlocked Instructions for Multiprocessing Support
  • Bus-Control Registers Configure Strobe-Control Wait-State Generation
  • 1.8-V (Core) and 3.3-V (I/O) Supply Voltages
  • On-Chip Scan-Based Emulation Logic, IEEE Std 1149.1 (JTAG)

IEEE Standard 1149.1-1990 Standard-Test-Access Port
TImeline is a trademark of Texas Instruments.
Other trademarks are the property of their respective owners.

The TMS320VC33 DSP is a 32-bit, floating-point processor manufactured in 0.18-µm four-level-metal CMOS (TImeline) technology. The TMS320VC33 is part of the TMS320C3x generation of DSPs from Texas Instruments.

The TMS320C3x’s internal busing and special digital-signal-processing instruction set have the speed and flexibility to execute up to 150 million floating-point operations per second (MFLOPS). The TMS320VC33 optimizes speed by implementing functions in hardware that other processors implement through software or microcode. This hardware-intensive approach provides performance previously unavailable on a single chip.

The TMS320VC33 can perform parallel multiply and ALU operations on integer or floating-point data in a single cycle. Each processor also possesses a general-purpose register file, a program cache, dedicated ARAUs, internal dual-access memories, one DMA channel supporting concurrent I/O, and a short machine-cycle time. High performance and ease of use are the results of these features.

General-purpose applications are greatly enhanced by the large address space, multiprocessor interface, internally and externally generated wait states, one external interface port, two timers, one serial port, and multiple-interrupt structure. The TMS320C3x supports a wide variety of system applications from host processor to dedicated coprocessor. High-level-language support is easily implemented through a register-based architecture, large address space, powerful addressing modes, flexible instruction set, and well-supported floating-point arithmetic.

The TMS320VC33 is a superset of the TMS320C31. Designers now have an additional 1M bits of on-chip SRAM, a maximum throughput of 150 MFLOPS, and several I/O enhancements that allow easy upgrades to current systems or creation of new baselines. This data sheet provides information required to fully utilize the new features of the TMS320VC33 device. For general TMS320C3x architecture and programming information, see the TMS320C3x User’s Guide (literature number SPRU031).

The TMS320VC33 DSP is a 32-bit, floating-point processor manufactured in 0.18-µm four-level-metal CMOS (TImeline) technology. The TMS320VC33 is part of the TMS320C3x generation of DSPs from Texas Instruments.

The TMS320C3x’s internal busing and special digital-signal-processing instruction set have the speed and flexibility to execute up to 150 million floating-point operations per second (MFLOPS). The TMS320VC33 optimizes speed by implementing functions in hardware that other processors implement through software or microcode. This hardware-intensive approach provides performance previously unavailable on a single chip.

The TMS320VC33 can perform parallel multiply and ALU operations on integer or floating-point data in a single cycle. Each processor also possesses a general-purpose register file, a program cache, dedicated ARAUs, internal dual-access memories, one DMA channel supporting concurrent I/O, and a short machine-cycle time. High performance and ease of use are the results of these features.

General-purpose applications are greatly enhanced by the large address space, multiprocessor interface, internally and externally generated wait states, one external interface port, two timers, one serial port, and multiple-interrupt structure. The TMS320C3x supports a wide variety of system applications from host processor to dedicated coprocessor. High-level-language support is easily implemented through a register-based architecture, large address space, powerful addressing modes, flexible instruction set, and well-supported floating-point arithmetic.

The TMS320VC33 is a superset of the TMS320C31. Designers now have an additional 1M bits of on-chip SRAM, a maximum throughput of 150 MFLOPS, and several I/O enhancements that allow easy upgrades to current systems or creation of new baselines. This data sheet provides information required to fully utilize the new features of the TMS320VC33 device. For general TMS320C3x architecture and programming information, see the TMS320C3x User’s Guide (literature number SPRU031).
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모두 보기29
유형 직함 날짜
* Data sheet TMS320VC33 Digital Signal Processor datasheet (Rev. E) 2004/01/30
Application note 320C3x, 320C4x, and 320MCM42x Power-Up Sensitivity at Cold Temperatures (Rev. D) 2004/08/06
User guide TMS320C33 User's Guide (Rev. F) 2004/03/31
More literature SM302VC33GNMM150, SMJ320VC33HFGM150, SM320VC33GNMEP (Rev. C) 2002/12/18
Application note UltraLow-Power Supply Voltage Supervisor Family TPS383x 2000/06/20
User guide TMS320C3x/C4x Assembly Language Tools User's Guide (Rev. D) 1998/04/16
User guide TMS320C3x/C4x Optimizing C Compiler User's Guide (Rev. H) 1998/04/14
Application note EDRAM Memory Controller for the TMS320C31 DSP Application Report 1998/01/01
User guide TMS320C3x General-Purpose Applications User's Guide 1998/01/01
Application note An Adaptive Noise Cancelling System to Enhance Sonar Receiver Performance -C31 1997/07/01
Application note Implementing Vocoder and HFF Modem Algorithms Using the TMS320C31 DSP 1997/07/01
Application note Implementing a Fast 3-D Vision Sensor With Multiple TMS320C31 DSPs 1997/07/01
Application note Implementing a Noise Cancellation System with the TMS320C31 1997/07/01
Application note In-Service, Non-Intrusive Measurement Device in Telecomm. Networks - TMS320C31 1997/07/01
Application note Real-Tme Implementation of a COFDM Modem for Data Transmission Over HF Channels 1997/07/01
Application note Signal Processing Subsystem-Detection of Stimulated Otoacoustic Emissions 'C31 1997/07/01
Application note Switching From Bootloader to MP Mode with TMS320C31 1997/06/01
Application note An Introduction to Fractal Image Compression 1997/01/01
Application note Interfacing Memory to the TMS320C32 DSP (Rev. A) 1996/05/01
Application note FIFO Mailbox-Bypass Registers: Using Bypass Registers to Initialize DMA Control (Rev. A) 1996/03/01
Application note FIFO Synchronous Retransmit: Programmable DSP-Interface for FIR Filtering (Rev. A) 1996/03/01
Application note Interfacing TI Clocked FIFOs With TI Floating-Point DSPs (Rev. A) 1996/03/01
Application note How TMS320 Tools Interact With the TMS320C32's Enhanced Memory Interface 1995/11/01
Application note Engine Knock Detection Using Spectral Analysis With TMS320C25 or TMS320C30 DSPs 1995/01/01
User guide JTAG/MPSD Emulation Technical Reference (Rev. A) 1994/12/01
Application note Setting Up TMS320 DSP Interrupts in 'C' 1994/11/01
User guide TMS320C3x Workstation Emulator Installation Guide 1994/11/01
User guide TMS320C3x Evaluation Module Installation Guide 1993/11/01
Application note TMS320C31 Embedded Control Technical Brief 1992/08/01

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IDE, 구성, 컴파일러 또는 디버거

CODECOMPOSER — Code Composer IDE - TMS320C3x/C4x 장치

Additional Information


Code Composer v4 was the last release of the Code Composer IDE that supported older digital signal processors such as TMS320C3x/4x and TMS320C2x/C5x.  There were different versions for these families. These products are no longer available for purchase or download. (...)

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LQFP (PGE) 144 옵션 보기
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