PMP22165

Power for Xilinx Versal adaptive compute acceleration platform (ACAP) reference design

Design files

PMP22165

Design files

Overview

This reference design addresses Xilinx Versal adaptive compute acceleration platform (ACAP) requirements and consists of a power management integrated circuit (PMIC) for system rails plus a multiphase controller and power stages to support higher current processor loads. On-board dynamic loads on the critical outputs allow testing to Xilinx's demanding power requirements. PMP22165 along with the TPS53681 EVM is a tested solution offering performance with components to meet processor requirements for Versal’s most common use cases one and three.

Features

10-rail user-programmable TPS650861 PMIC for both system-level power and full design sequence management
Full system power solution for Versal's most common use cases one and three
Optimized power stage combination for peak efficiency of 92% on the VCCINT rail at the nominal output voltage
On-board dynamic loads for more critical outputs

Output voltage options	PMP22165.1	PMP22165.2	PMP22165.3	PMP22165.4	PMP22165.5	PMP22165.6	PMP22165.7	PMP22165.8	PMP22165.9
Vin (Min) (V)	7	7	1.5	7	3.2	3.3	3.2	3.2	7
Vin (Max) (V)	14	14	1.5	14	3.4	3.3	3.4	3.4	14
Vout (Nom) (V)	3.3	1.5	1.5	1.2	.88	3.3	2.5	1.1	.8
Iout (Max) (A)	4	4	.2	4.8	3.1	.5	.5	.5	165
Output Power (W)	13.2	6	.3	5.76	2.728	1.65	1.25	.55	132
Isolated/Non-Isolated	Non-Isolated	Non-Isolated	Non-Isolated	Non-Isolated	Non-Isolated	Non-Isolated	Non-Isolated	Non-Isolated	Non-Isolated
Input Type	DC	DC	DC	DC	DC	DC	DC	DC	DC
Topology	Buck- Synchronous	Buck- Synchronous	Other	Buck- Synchronous	Buck- Synchronous	Other	Buck- Synchronous	Buck- Synchronous	Buck- Multiphase

Enterprise systems

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A fully assembled board has been developed for testing and performance validation only, and is not available for sale.

Design files & products

Design files

Download ready-to-use system files to speed your design process.

Test report — PMP22165

TIDT182.PDF (4683 K)

Test results for the reference design, including efficiency graphs, test prerequisites and more

Schematic — PMP22165

TIDM600.PDF (624 K)

Detailed schematic diagram for design layout and components

Bill of materials (BOM) — PMP22165

TIDM601.PDF (334 K)

Complete listing of design components, reference designators, and manufacturers/part numbers

Assembly drawing — PMP22165

TIDM602.PDF (384 K)

Detailed overview of design layout for component placement

CAD/CAE symbol — PMP22165

TIDM604.ZIP (1526 K)

Files used for 3D models or 2D drawings of IC components

Gerber file — PMP22165

TIDCFV0.ZIP (1789 K)

Design file that contains information on physical board layer of design PCB

PCB layout — PMP22165

TIDM603.PDF (2257 K)

PCB layer plot file used for generating PCB design layout

Products

Includes TI products in the design and potential alternatives.

Multi-channel ICs (PMICs)

TPS650861 — User programmable 3 converter, 3 controller, 4 LDO, & 3 load switch Power Management IC (PMIC)

Data sheet: PDF | HTML

AC/DC & DC/DC controllers (external FET)

TPS53681 — Dual-Channel 6+2/5+3 D-CAP+TM Multiphase Step-Down Controller with PMBus and NVM

Data sheet: PDF | HTML

AC/DC & DC/DC converters (integrated FET)

TPS62173 — 3–17V 0.5A Step-Down Converter in 2x2 QFN package

Data sheet: PDF | HTML

MOSFETs

CSD87381P — 30-V, N channel synchronous buck NexFET™ power MOSFET, 3 mm x 2.5 mm LGA, 15 A

Data sheet: PDF | HTML

Si power stages

CSD95490Q5MC — 75A Synchronous Buck NexFET™ Smart Power Stage with DualCool Package

Data sheet: PDF | HTML

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Software

Calculation tool

TIDCFV1 — TPS650861 Programming PMP22165

Supported products & hardware

Supported products & hardware

Products

Multi-channel ICs (PMICs)

TPS650861 — User programmable 3 converter, 3 controller, 4 LDO, & 3 load switch Power Management IC (PMIC)

TIDCFV1 — TPS650861 Programming PMP22165

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Latest version

Version: 01.00.00.00

Release date: 17 May 2020

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TPS650861 Programming PMP22165 (zip) — 921 K

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Products

Multi-channel ICs (PMICs)

TPS650861 — User programmable 3 converter, 3 controller, 4 LDO, & 3 load switch Power Management IC (PMIC)

Technical documentation

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	Type	Title		Date
*	Test report	Power for Xilinx Versal Adaptive Compute Acceleration Platform Reference Design		May 14, 2020

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