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- JESD204B Link Latency Using a High-Speed ADC and FPGA Design Guide
(PDF 125 KB)
18 Feb 2014 166 views
JESD204B links are the latest trend in data-converter digital interfaces. These links take advantage of high-speed serial-digital technology to offer many compelling benefits including improved channel densities. This reference design addresses one of the challenges of adopting the new interface: understanding and designing the link latency. An example achieves deterministic latency and determines the link latency of a system containing the Texas Instruments LM97937 ADC and Xilinx Kintex 7 FPGA.
- Guarantee deterministic latency across the JESD204B link
- Understand the tradeoff between link latency and tolerance to link delay variation
- Use a formulaic and procedure-based approach to design the link latency
- Implement a JESD204B link using Texas Instruments' ADC16DX370 or LM97937 ADC and a Xilinx Kintex 7 FPGA