CDCE62005EVM Evaluation Module
The CDCE62005 is a high performance clock generator and distributor featuring low output jitter, a high degree of configurability via a SPI interface, and programmable start up modes determined by on-chip EEPROM. Specifically tailored for clocking data converters and high-speed digital signals, the CDCE62005 achieves jitter performance well under 1 ps RMS(1). It incorporates a synthesizer block with partially integrated loop filter, a clock distribution block including programmable output formats, and an input block featuring an innovative smart multiplexer. The clock distribution block includes five individually programmable outputs that can be configured to provide different combinations of output formats (LVPECL, LVDS, LVCMOS). Each output can also be programmed to a unique output frequency (ranging from 800 kHz to 1.5 GHz (2)) and skew relationship via a programmable delay block. If all outputs are configured in single-ended mode (e.g., LVCMOS), the CDCE62005 supports up to ten outputs. Each output can select one of four clock sources to condition and distribute including any of the three clock inputs or the output of the frequency synthesizer. The input block includes two universal differential inputs which support frequencies up to 500 MHz and an auxiliary single ended input that can be connected to a CMOS level clock or configured to connect to an external crystal via an on board oscillator block. The smart input multiplexer has two modes of operation, manual and automatic. In manual mode, the user selects the synthesizer reference via the SPI interface. In automatic mode, the input multiplexer will automatically select between the highest priority input clock available.
- Frequency Synthesizer with PLL/VCO and Partially Integrated Loop Filter.
- Fully Configurable Outputs Including Frequency, Output Format, and Output Skew.
- Smart Input Multiplexer Automatically Switches Between One of Three Reference Inputs.
- Multiple Operational Modes Include Clock Generation via Crystal, SERDES Startup Mode, Jitter Cleaning, and Oscillator Holdover Mode
- Integrated EEPROM Determines Device Configuration at Power-up
- Excellent Jitter Performance
- Integrated Frequency Synthesizer including PLL, Multiple VCOs, and Loop Filter:
- Full Programmability Facilitates Phase Noise Performance Optimization Enabling Jitter Cleaner Mode.
- Programmable Charge Pump Gain and Loop Filter Settings
- Unique Dual-VCO Architecture Supports a Wide Tuning Range 1.750 GHz-2.356 GHz
- Universal Output Blocks Support up to 5 differential, 10 Single-ended, or Combinations of Differential or Single-ended:
- 1 ps RMS (10 kHz to 20 MHz) Output Jitter Performance
- Low Output Phase Noise:
- 130 dBc/Hz at 1MHz offset, Fc = 491.52 MHz
- Output Frequency Ranges from 4.25 MHz to 1.175GHz in Synthesizer Mode
- Output Frequency up to 1.5 GHz in Fan-out Mode, LVPECL, LVDS, LVCMOS, and Special High Output Swing Modes
- Independent Output Dividers Support Divide Ratios from 1-80(1)
- Independent Coarse Skew Control on all Outputs
- Flexible Inputs with Innovative Smart Multiplexer Feature:
- Two Universal Differential Inputs Accept Frequency, Output Format, and Output Skew. Frequencies up to 1500 MHz (LVPECL), 800 MHz (LVDS), or 250 MHz (LVCMOS
- One Auxiliary Input Accepts Single Ended Clock Source or Crystal. Auxiliary Input Accepts Crystals in the Range of 2 MHz-42 MHz or an LVCMOS Input up to 75 MHz.
- Clock Generator Mode Using Crystal Input.
- Smart Input Multiplexer can be configured to Automatically Switch between Highest Priority Clock Source Available Allowing for Fail-safe Operation and Holdover Modes.
- Typical Power Consumption 1.7W (See Table 44) at 3.3V
- Integrated EEPROM Stores Default Settings; Therefore, The Device Can Power up in a Known, Predefined State.
- Offered in QFN-48 Package
- ESD Protection Exceeds 2kV HBM
- Industrial Temperature Range -40°C to 85°C
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