SNAS483F February   2010  – August 2015 ADC128D818

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 DC Electrical Characteristics
    6. 7.6 AC Electrical Characteristics
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Supply Voltage (V+)
      2. 8.3.2 Voltage References (VREF)
      3. 8.3.3 Analog Inputs (IN0 - IN7)
        1. 8.3.3.1 Single-Ended Input
        2. 8.3.3.2 Pseudo-Differential Input
    4. 8.4 Device Functional Modes
      1. 8.4.1 Modes of Operation
    5. 8.5 Programming
      1. 8.5.1 Interface
        1. 8.5.1.1 Serial Bus Address
        2. 8.5.1.2 Time-out
          1. 8.5.1.2.1 Example Writes and Reads
    6. 8.6 Register Maps
      1. 8.6.1  ADC128D818 Internal Registers
      2. 8.6.2  Configuration Register — Address 00h
      3. 8.6.3  Interrupt Status Register — Address 01h
      4. 8.6.4  Interrupt Mask Register — Address 03h
      5. 8.6.5  Conversion Rate Register — Address 07h
      6. 8.6.6  Channel Disable Register — Address 08h
      7. 8.6.7  One-Shot Register — Address 09h
      8. 8.6.8  Deep Shutdown Register — Address 0Ah
      9. 8.6.9  Advanced Configuration Register — Address 0Bh
      10. 8.6.10 Busy Status Register — Address 0Ch
      11. 8.6.11 Channel Readings Registers — Addresses 20h - 27h
      12. 8.6.12 Limit Registers — Addresses 2Ah - 39h
      13. 8.6.13 Manufacturer ID Register — Address 3Eh
      14. 8.6.14 Revision ID Register — Addresses 3Fh
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Digital Output (DOUT)
      2. 9.1.2 Temperature Measurement System
        1. 9.1.2.1 Temperature Limits
      3. 9.1.3 Interrupt Structure
        1. 9.1.3.1 Interrupt Output (INT)
        2. 9.1.3.2 Interrupt Clearing
        3. 9.1.3.3 Temperature Interrupt
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Power Management
        2. 9.2.2.2 Using the ADC128D818
          1. 9.2.2.2.1 Quick Start
          2. 9.2.2.2.2 Poweron Reset (POR)
          3. 9.2.2.2.3 Configuration Register (address 00h)
          4. 9.2.2.2.4 Interrupt Status Register (address 01h)
          5. 9.2.2.2.5 Interrupt Mask Register (address 03h)
          6. 9.2.2.2.6 Conversion Rate Register (address 07h)
          7. 9.2.2.2.7 One-Shot Register (address 09h)
          8. 9.2.2.2.8 Deep Shutdown Register (address 0Ah)
          9. 9.2.2.2.9 Channel Readings Registers (addresses 20h - 27h)
      3. 9.2.3 Application Curve
    3. 9.3 System Examples
      1. 9.3.1 General Voltage Monitoring
      2. 9.3.2 Voltage Monitoring for Power Supplies
      3. 9.3.3 Temperature Sensors
      4. 9.3.4 Bridge Sensors
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Pin Configuration and Functions

PW Package
16-Pin TSSOP
Top View
ADC128D818 30096302.gif

Pin Functions

PIN TYPE DESCRIPTION
NO. NAME ESD STRUCTURE
1 VREF
ADC128D818 30096330.gif
 Analog Input ADC external reference.
ADC128D818 allows two choices for sourcing VREF: internal or external. If the 2.56-V internal VREF is used, leave this pin unconnected. If the external VREF is used, source this pin with a voltage between 1.25 V and V+. At Power-On-Reset (POR), the default setting is the internal VREF.
Bypass with the parallel combination of 1-μF (electrolytic or tantalum) and 0.1-μF (ceramic) capacitors.
2 SDA
ADC128D818 30096329.gif
 Digital I/O Serial Bus Bidirectional Data. NMOS open-drain output. Requires external pullup resistor to function properly.
3 SCL
ADC128D818 30096329.gif
 Digital Input Serial Bus Clock. Requires external pullup resistor to function properly.
4 GND GROUND Internally connected to all of the circuitry.
5 V+
ADC128D818 30096328.gif
 POWER 3.0-V to 5.5-V power. Bypass with the parallel combination of 1-μF (electrolytic or tantalum) and 0.1-μF (ceramic) bypass capacitors.
6 INT
ADC128D818 30096329.gif
 Digital Output Interrupt Request. Active Low, NMOS, open-drain. Requires external pullup resistor to function properly.
7 A0
ADC128D818 30096329.gif
 Tri-Level Inputs Tri-Level Serial Address pins that allow 9 devices on a single I2C bus.
8 A1
9 IN7
ADC128D818 30096330.gif
 Analog Inputs The full scale range will be controlled by the internal or external VREF. These inputs can be assigned as single-ended and/or pseudo-differential inputs.
10 IN6
11 IN5
12 IN4
13 IN3
14 IN2
15 IN1
16 IN0