SLVSDR3A May   2018  – September 2018 ADC12DL3200

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     ADC12DL3200 Frequency Response
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: DC Specifications
    6. 6.6  Electrical Characteristics: Power Consumption
    7. 6.7  Electrical Characteristics: AC Specifications (Dual-Channel Mode)
    8. 6.8  Electrical Characteristics: AC Specifications (Single-Channel Mode)
    9. 6.9  Timing Requirements
    10. 6.10 Switching Characteristics
    11. 6.11 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Inputs
        1. 7.3.1.1 Analog Input Protection
        2. 7.3.1.2 Full-Scale Voltage (VFS) Adjustment
        3. 7.3.1.3 Analog Input Offset Adjust
      2. 7.3.2 ADC Core
        1. 7.3.2.1 ADC Theory of Operation
        2. 7.3.2.2 ADC Core Calibration
        3. 7.3.2.3 ADC Overrange Detection
        4. 7.3.2.4 Code Error Rate (CER)
        5. 7.3.2.5 Internal Dither
      3. 7.3.3 Timestamp
      4. 7.3.4 Clocking
        1. 7.3.4.1 Noiseless Aperture Delay Adjustment (tAD Adjust)
        2. 7.3.4.2 Aperture Delay Ramp Control (TAD_RAMP)
        3. 7.3.4.3 SYSREF Capture for Multi-Device Synchronization and Deterministic Latency
          1. 7.3.4.3.1 SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing)
          2. 7.3.4.3.2 Automatic SYSREF Calibration
      5. 7.3.5 LVDS Digital Interface
        1. 7.3.5.1 Multi-Device Synchronization and Deterministic Latency Using Strobes
          1. 7.3.5.1.1 Dedicated Strobe Pins
          2. 7.3.5.1.2 Reduced Width Interface With Dedicated Strobe Pins
          3. 7.3.5.1.3 LSB Replacement With a Strobe
          4. 7.3.5.1.4 Strobe Over All Data Pairs
      6. 7.3.6 Alarm Monitoring
        1. 7.3.6.1 Clock Upset Detection
      7. 7.3.7 Temperature Monitoring Diode
      8. 7.3.8 Analog Reference Voltage
    4. 7.4 Device Functional Modes
      1. 7.4.1 Dual-Channel Mode (Non-DES Mode)
      2. 7.4.2 Internal Dither Modes
      3. 7.4.3 Single-Channel Mode (DES Mode)
      4. 7.4.4 LVDS Output Driver Modes
      5. 7.4.5 LVDS Output Modes
        1. 7.4.5.1 Staggered Output Mode
        2. 7.4.5.2 Aligned Output Mode
        3. 7.4.5.3 Reducing the Number of Strobes
        4. 7.4.5.4 Reducing the Number of Data Clocks
        5. 7.4.5.5 Scrambling
        6. 7.4.5.6 Digital Interface Test Patterns and LVSD SYNC Functionality
          1. 7.4.5.6.1 Active Pattern
          2. 7.4.5.6.2 Synchronization Pattern
          3. 7.4.5.6.3 User-Defined Test Pattern
      6. 7.4.6 Power-Down Modes
      7. 7.4.7 Calibration Modes and Trimming
        1. 7.4.7.1 Foreground Calibration Mode
        2. 7.4.7.2 Background Calibration Mode
        3. 7.4.7.3 Low-Power Background Calibration (LPBG) Mode
      8. 7.4.8 Offset Calibration
      9. 7.4.9 Trimming
    5. 7.5 Programming
      1. 7.5.1 Using the Serial Interface
        1. 7.5.1.1 SCS
        2. 7.5.1.2 SCLK
        3. 7.5.1.3 SDI
        4. 7.5.1.4 SDO
        5. 7.5.1.5 Streaming Mode
    6. 7.6 Register Maps
      1. 7.6.1 SPI_REGISTER_MAP Registers
        1. 7.6.1.1  CONFIG_A Register (Address = 0x000) [reset = 0x30]
          1. Table 20. CONFIG_A Register Field Descriptions
        2. 7.6.1.2  DEVICE_CONFIG Register (Address = 0x002) [reset = 0x00]
          1. Table 21. DEVICE_CONFIG Register Field Descriptions
        3. 7.6.1.3  CHIP_TYPE Register (Address = 0x003) [reset = 0x03]
          1. Table 22. CHIP_TYPE Register Field Descriptions
        4. 7.6.1.4  CHIP_ID Register (Address = 0x004) [reset = 0x0022]
          1. Table 23. CHIP_ID Register Field Descriptions
        5. 7.6.1.5  VENDOR_ID Register (Address = 0xC) [reset = 0x0451]
          1. Table 24. VENDOR_ID Register Field Descriptions
        6. 7.6.1.6  USR0 Register (Address = 0x010) [reset = 0x00]
          1. Table 25. USR0 Register Field Descriptions
        7. 7.6.1.7  CLK_CTRL0 Register (Address = 0x029) [reset = 0x00]
          1. Table 26. CLK_CTRL0 Register Field Descriptions
        8. 7.6.1.8  CLK_CTRL1 Register (Address = 0x02A) [reset = 0x00]
          1. Table 27. CLK_CTRL1 Register Field Descriptions
        9. 7.6.1.9  SYSREF_POS Register (Address = 0x02C-0x02E) [reset = Undefined]
          1. Table 28. SYSREF_POS Register Field Descriptions
        10. 7.6.1.10 INA Full-Scale Range Adjust Register (Address = 0x030-0x031) [reset = 0xA000]
          1. Table 29. FS_RANGE_A Register Field Descriptions
        11. 7.6.1.11 INB Full-Scale Range Adjust Register (Address = 0x032-0x033) [reset = 0xA000]
          1. Table 30. FS_RANGE_B Register Field Descriptions
        12. 7.6.1.12 BG_BYPASS Register (Address = 0x038) [reset = 0x00]
          1. Table 31. BG_BYPASS Register Field Descriptions
        13. 7.6.1.13 TMSTP_CTRL Register (Address = 0x03B) [reset = 0x00]
          1. Table 32. SYNC_CTRL Register Field Descriptions
        14. 7.6.1.14 LVDS_SWING Register (Address = 0x048) [reset = 0x00]
          1. Table 33. LVDS_SWING Register Field Descriptions
        15. 7.6.1.15 INPUT_MUX Register (Address = 0x060) [reset = 0x01]
          1. Table 34. INPUT_MUX Register Field Descriptions
        16. 7.6.1.16 CAL_EN Register (Address = 0x61) [reset = 0x01]
          1. Table 35. CAL_EN Register Field Descriptions
        17. 7.6.1.17 CAL_CFG0 Register (Address = 0x062) [reset = 0x01]
          1. Table 36. CAL_CFG0 Register Field Descriptions
        18. 7.6.1.18 CAL_AVG Register (Address = 0x68) [reset = 0x61]
          1. Table 37. CAL_AVG Register Field Descriptions
        19. 7.6.1.19 CAL_STATUS Register (Address = 0x06A) [reset = Undefined]
          1. Table 38. CAL_STATUS Register Field Descriptions
        20. 7.6.1.20 CAL_PIN_CFG Register (Address = 0x06B) [reset = 0x00]
          1. Table 39. CAL_PIN_CFG Register Field Descriptions
        21. 7.6.1.21 CAL_SOFT_TRIG Register (Address = 0x06C) [reset = 0x01]
          1. Table 40. CAL_SOFT_TRIG Register Field Descriptions
        22. 7.6.1.22 Low-Power Background Calibration Register (Address = 0x6E) [reset = 0x88]
          1. Table 41. CAL_LP Register Field Descriptions
        23. 7.6.1.23 CAL_DATA_EN Register (Address = 0x70) [reset = 0x00]
          1. Table 42. CAL_DATA_EN Register Field Descriptions
        24. 7.6.1.24 CAL_DATA Register (Address = 0x71) [reset = Undefined]
          1. Table 43. CAL_DATA Register Field Descriptions
        25. 7.6.1.25 GAIN_TRIM_A Register (Address = 0x07A) [reset = Undefined]
          1. Table 44. GAIN_TRIM_A Register Field Descriptions
        26. 7.6.1.26 GAIN_TRIM_B Register (Address = 0x07B) [reset = Undefined]
          1. Table 45. GAIN_TRIM_B Register Field Descriptions
        27. 7.6.1.27 BG_TRIM Register (Address = 0x07C) [reset = Undefined]
          1. Table 46. BG_TRIM Register Field Descriptions
        28. 7.6.1.28 RTRIM_A Register (Address = 0x07E) [reset = Undefined]
          1. Table 47. RTRIM_A Register Field Descriptions
        29. 7.6.1.29 RTRIM_B Register (Address = 0x7F) [reset = Undefined]
          1. Table 48. RTRIM_B Register Field Descriptions
        30. 7.6.1.30 ADC_DITH Register (Address = 0x9D) [reset = 0x01]
          1. Table 49. ADC_DITH Register Field Descriptions
        31. 7.6.1.31 Timing Adjustment for Bank 0 (0° Clock) Register (Address = 0x102) [reset = Undefined]
          1. Table 50. B0_TIME_0 Register Field Descriptions
        32. 7.6.1.32 Timing Adjustment for Bank 0 (90° Clock) Register (Address = 0x103) [reset = Undefined]
          1. Table 51. B0_TIME_90 Register Field Descriptions
        33. 7.6.1.33 Timing Adjustment for Bank 1 (0° Clock) Register (Address = 0x112) [reset = Undefined]
          1. Table 52. B1_TIME_0 Register Field Descriptions
        34. 7.6.1.34 Timing Adjustment for Bank 1 (90° Clock) Register (Address = 0x113) [reset = Undefined]
          1. Table 53. B1_TIME_90 Register Field Descriptions
        35. 7.6.1.35 Timing Adjustment for Bank 4 (0° Clock) Register (Address = 0x142) [reset = Undefined]
          1. Table 54. B4_TIME_0 Register Field Descriptions
        36. 7.6.1.36 Timing Adjustment for Bank 5 (0° Clock) Register (Address = 0x152) [reset = Undefined]
          1. Table 55. B5_TIME_0 Register Field Descriptions
        37. 7.6.1.37 LSB_CTRL Register (Address = 0x160) [reset = 0x00]
          1. Table 56. LSB_CTRL Register Field Descriptions
        38. 7.6.1.38 LSB_SEL Register (Address = 0x161) [reset = 0x00]
          1. Table 57. LSB_SEL Register Field Descriptions
        39. 7.6.1.39 UPAT0 Register (Address = 0x180) [reset = 0x0000]
          1. Table 58. UPAT0 Register Field Descriptions
        40. 7.6.1.40 UPAT1 Register (Address = 0x182) [reset = 0x0FFF]
          1. Table 59. UPAT1 Register Field Descriptions
        41. 7.6.1.41 UPAT2 Register (Address = 0x184) [reset = 0x0000]
          1. Table 60. UPAT2 Register Field Descriptions
        42. 7.6.1.42 UPAT3 Register (Address = 0x186) [reset = 0x0FFF]
          1. Table 61. UPAT3 Register Field Descriptions
        43. 7.6.1.43 UPAT4 Register (Address = 0x188) [reset = 0x0000]
          1. Table 62. UPAT4 Register Field Descriptions
        44. 7.6.1.44 UPAT5 Register (Address = 0x18A) [reset = 0x0FFF]
          1. Table 63. UPAT5 Register Field Descriptions
        45. 7.6.1.45 UPAT6 Register (Address = 0x18C) [reset = 0x0000]
          1. Table 64. UPAT6 Register Field Descriptions
        46. 7.6.1.46 UPAT7 Register (Address = 0x18E) [reset = 0x0FFF]
          1. Table 65. UPAT7 Register Field Descriptions
        47. 7.6.1.47 UPAT_CTRL Register (Address = 0x190) [reset = 0x1E]
          1. Table 66. UPAT_CTRL Register Field Descriptions
        48. 7.6.1.48 LVDS_EN Register (Address = 0x200) [reset = 0x01]
          1. Table 67. LVDS_EN Register Field Descriptions
        49. 7.6.1.49 LMODE Register (Address = 0x201) [reset = 0x01]
          1. Table 68. LMODE Register Field Descriptions
        50. 7.6.1.50 LFRAME Register (Address = 0x202) [reset = 0x80]
          1. Table 69. LFRAME Register Field Descriptions
        51. 7.6.1.51 LSYNC_N Register (Address = 0x203) [reset = 0x01]
          1. Table 70. LSYNC_N Register Field Descriptions
        52. 7.6.1.52 LCTRL Register (Address = 0x204) [reset = 0x02]
          1. Table 71. LCTRL Register Field Descriptions
        53. 7.6.1.53 PAT_SEL Register (Address = 0x205) [reset = 0x02]
          1. Table 72. PAT_SEL Register Field Descriptions
        54. 7.6.1.54 LCS_EN Register (Address = 0x206) [reset = 0xFF]
          1. Table 73. LCS_EN Register Field Descriptions
        55. 7.6.1.55 LVDS_STATUS Register (Address = 0x208) [reset = Undefined]
          1. Table 74. LVDS_STATUS Register Field Descriptions
        56. 7.6.1.56 PD_CH Register (Address = 0x209) [reset = 0x00]
          1. Table 75. PD_CH Register Field Descriptions
        57. 7.6.1.57 OVR_T0 Register (Address = 0x211) [reset = 0xF2]
          1. Table 76. OVR_T0 Register Field Descriptions
        58. 7.6.1.58 OVR_T1 Register (Address = 0x212) [reset = 0xAB]
          1. Table 77. OVR_T1 Register Field Descriptions
        59. 7.6.1.59 OVR_CFG Register (Address = 0x213) [reset = 0x07]
          1. Table 78. OVR_CFG Register Field Descriptions
        60. 7.6.1.60 SPIN_ID Register (Address = 0x297) [reset = 0x00]
          1. Table 79. SPIN_ID Register Field Descriptions
        61. 7.6.1.61 SRC_EN Register (Address = 0x2B0) [reset = 0x00]
          1. Table 80. SRC_EN Register Field Descriptions
        62. 7.6.1.62 SRC_CFG Register (Address = 0x2B1) [reset = 0x05]
          1. Table 81. SRC_CFG Register Field Descriptions
        63. 7.6.1.63 SRC_STATUS Register (Address = 0x2B2) [reset = Undefined]
          1. Table 82. SRC_STATUS Register Field Descriptions
        64. 7.6.1.64 TAD Register (Address = 0x2B5-2B7) [reset = 0x000000]
          1. Table 83. TAD Register Field Descriptions
        65. 7.6.1.65 TAD_RAMP Register (Address = 0x2B8) [reset = 0x00]
          1. Table 84. TAD_RAMP Register Field Descriptions
        66. 7.6.1.66 ALARM Register (Address = 0x2C0) [reset = Undefined]
          1. Table 85. ALARM Register Field Descriptions
        67. 7.6.1.67 ALM_STATUS Register (Address = 0x2C1) [reset = 0x05]
          1. Table 86. ALM_STATUS Register Field Descriptions
        68. 7.6.1.68 ALM_MASK Register (Address = 0x2C2) [reset = 0x05]
          1. Table 87. ALM_MASK Register Field Descriptions
        69. 7.6.1.69 TADJ_A Register (Address = 0x310) [reset = Undefined]
          1. Table 88. TADJ_A Register Field Descriptions
        70. 7.6.1.70 TADJ_B Register (Address = 0x313) [reset = Undefined]
          1. Table 89. TADJ_B Register Field Descriptions
        71. 7.6.1.71 TADJ_A_FG90_VINA Register (Address = 0x314) [reset = Undefined]
          1. Table 90. TADJ_A_FG90_VINA Register Field Descriptions
        72. 7.6.1.72 TADJ_B_FG0_VINA Register (Address = 0x315) [reset = Undefined]
          1. Table 91. TADJ_B_FG0_VINA Register Field Descriptions
        73. 7.6.1.73 TADJ_A_FG90_VINB Register (Address = 0x31A) [reset = Undefined]
          1. Table 92. TADJ_A_FG90_VINB Register Field Descriptions
        74. 7.6.1.74 TADJ_B_FG0_VINB Register (Address = 0x31B) [reset = 0x0]
          1. Table 93. TADJ_B_FG0_VINB Register Field Descriptions
        75. 7.6.1.75 OADJ_A_FG0_VINA Register (Address = 0x344) [reset = Undefined]
          1. Table 94. OADJ_A_FG0_VINA Register Field Descriptions
        76. 7.6.1.76 OADJ_A_FG0_VINB Register (Address = 0x346) [reset = Undefined]
          1. Table 95. OADJ_A_FG0_VINB Register Field Descriptions
        77. 7.6.1.77 OADJ_A_FG90_VINA Register (Address = 0x348) [reset = Undefined]
          1. Table 96. OADJ_A_FG90_VINA Register Field Descriptions
        78. 7.6.1.78 OADJ_A_FG90_VINB Register (Address = 0x34A) [reset = Undefined]
          1. Table 97. OADJ_A_FG90_VINB Register Field Descriptions
        79. 7.6.1.79 OADJ_B_FG0_VINA Register (Address = 0x34C) [reset = Undefined]
          1. Table 98. OADJ_B_FG0_VINA Register Field Descriptions
        80. 7.6.1.80 OADJ_B_FG0_VINB Register (Address = 0x34E) [reset = Undefined]
          1. Table 99. OADJ_B_FG0_VINB Register Field Descriptions
        81. 7.6.1.81 GAIN_B0 Register (Address = 0x360) [reset = Undefined]
          1. Table 100. GAIN_B0 Register Field Descriptions
        82. 7.6.1.82 GAIN_B1 Register (Address = 0x361) [reset = Undefined]
          1. Table 101. GAIN_B1 Register Field Descriptions
        83. 7.6.1.83 GAIN_B4 Register (Address = 0x364) [reset = Undefined]
          1. Table 102. GAIN_B4 Register Field Descriptions
        84. 7.6.1.84 GAIN_B5 Register (Address = 0x365) [reset = Undefined]
          1. Table 103. GAIN_B5 Register Field Descriptions
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Wideband RF Sampling Receiver
        1. 8.2.1.1 Design Requirements
          1. 8.2.1.1.1 Input Signal Path
          2. 8.2.1.1.2 Clocking
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Calculating Values of AC-Coupling Capacitors
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Reconfigurable Dual-Channel, 2.5-GSPS or Single-Channel, 5.0-GSPS Oscilloscope
        1. 8.2.2.1 Design Requirements
          1. 8.2.2.1.1 Input Signal Path
          2. 8.2.2.1.2 Clocking
          3. 8.2.2.1.3 The ADC12DL3200
        2. 8.2.2.2 Application Curves
    3. 8.3 Initialization Set Up
  9. Power Supply Recommendations
    1. 9.1 Power Sequencing
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
  • ACF|256
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Features

  • ADC Core:
    • 12-Bit Resolution
    • Up to 6.4 GSPS in Single-Channel Mode
    • Up to 3.2 GSPS in Dual-Channel Mode
  • Internal Dither for Low-Magnitude, High-Order Harmonics
  • Low-Latency LVDS Interface:
    • Total Latency: < 10 ns
    • Up to 48 Data Pairs at 1.6 Gbps
    • Four DDR Data Clocks
    • Strobe Signals Simplify Synchronization
  • Noise Floor (No Input, VFS = 1.0 VPP-DIFF):
    • Dual-Channel Mode: –151.1 dBFS/Hz
    • Single-Channel Mode: –154.3 dBFS/Hz
  • Buffered Analog Inputs With VCMI of 0 V:
    • Analog Input Bandwidth (–3 dB): 8.0 GHz
    • Usable Input Frequency Range: > 10 GHz
    • Full-Scale Input Voltage (VFS, Default): 0.8 VPP
  • Noiseless Aperture Delay (TAD) Adjustment:
    • Precise Sampling Control: 19-fs Step
    • Simplifies Synchronization and Interleaving
    • Temperature and Voltage Invariant Delays
  • Easy-to-Use Synchronization Features:
    • Automatic SYSREF Timing Calibration
    • Timestamp for Sample Marking
  • Power Consumption: 3.15 W