12-bit, dual 3.2-GSPS or single 6.4-GSPS, RF-sampling analog-to-digital converter (LVDS interface)


Product details


Sample rate (Max) (MSPS) 3200, 6400 Resolution (Bits) 12 Number of input channels 2, 1 Interface type DDR LVDS, Parallel LVDS Analog input BW (MHz) 8000 Features Ultra High Speed Rating Catalog Input range (Vp-p) 0.8 Power consumption (Typ) (mW) 3150 Architecture Folding Interpolating SNR (dB) 57.9 ENOB (Bits) 9 SFDR (dB) 78 Operating temperature range (C) -40 to 85 Input buffer Yes open-in-new Find other High-speed ADCs (>10MSPS)


  • ADC Core:
    • 12-Bit Resolution
    • Up to 6.4 GSPS in Single-Channel Mode
    • Up to 3.2 GSPS in Dual-Channel Mode
  • Internal Dither for Low-Magnitude, High-Order Harmonics
  • Low-Latency LVDS Interface:
    • Total Latency: < 10 ns
    • Up to 48 Data Pairs at 1.6 Gbps
    • Four DDR Data Clocks
    • Strobe Signals Simplify Synchronization
  • Noise Floor (No Input, VFS = 1.0 VPP-DIFF):
    • Dual-Channel Mode: –151.1 dBFS/Hz
    • Single-Channel Mode: –154.3 dBFS/Hz
  • Buffered Analog Inputs With VCMI of 0 V:
    • Analog Input Bandwidth (–3 dB): 8.0 GHz
    • Usable Input Frequency Range: > 10 GHz
    • Full-Scale Input Voltage (VFS, Default): 0.8 VPP
  • Noiseless Aperture Delay (TAD) Adjustment:
    • Precise Sampling Control: 19-fs Step
    • Simplifies Synchronization and Interleaving
    • Temperature and Voltage Invariant Delays
  • Easy-to-Use Synchronization Features:
    • Automatic SYSREF Timing Calibration
    • Timestamp for Sample Marking
  • Power Consumption: 3.15 W

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open-in-new Find other High-speed ADCs (>10MSPS)


The ADC12DL3200 is an RF-sampling, giga-sample, analog-to-digital converter (ADC) that can directly sample input frequencies from DC to above 10 GHz. In dual-channel mode, the ADC12DL3200 can sample up to 3200 MSPS and in single-channel mode up to 6400 MSPS. Programmable tradeoffs in channel count (dual-channel mode) and Nyquist bandwidth (single-channel mode) allow development of flexible hardware that meets the needs of both high-channel count or wide instantaneous signal bandwidth applications. Full-power input bandwidth (–3 dB) of 8.0 GHz and a useable frequency range allows direct RF sampling of L-band, S-band, C-band, and X-band for frequency agile systems.

The ADC12DL3200 uses a low-latency, low-voltage differential signaling (LVDS) interface for latency sensitive applications or when the simplicity of LVDS is preferred. The interface uses up to 48 data pairs, four double data rate (DDR) clocks, and four strobe signals arranged in four 12-bit data buses. The interface supports signaling rates of up to 1.6 Gbps. Strobe signals simplify synchronization across buses and between multiple devices. The strobe is generated internally and can be reset at a deterministic time by the SYSREF input. Multi-device synchronization is further eased by innovative synchronization features such as noiseless aperture delay (TAD) adjustment and SYSREF windowing.

open-in-new Find other High-speed ADCs (>10MSPS)

Technical documentation

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Type Title Date
* Datasheet ADC12DL3200 6.4-GSPS Single-Channel or 3.2-GSPS Dual-Channel, 12-Bit Analog-to-Digital Converter (ADC) With LVDS Interface datasheet (Rev. B) Jun. 16, 2020
Technical articles How to achieve fast frequency hopping Mar. 03, 2019
User guides TSW14DL3200EVM High-Speed LVDS Data Capture and Pattern Generator User's Guide May 15, 2018
User guides ADC12DL3200 Evaluation Module User's Guide May 09, 2018
Technical articles RF sampling: Learning more about latency Feb. 09, 2017
Technical articles Why phase noise matters in RF sampling converters Nov. 28, 2016
Technical articles How to minimize filter loss when you drive an ADC Oct. 20, 2016

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

document-generic User guide

The ADC12DL3200 evaluation module (EVM) is used to evaluate the ADC12DL3200, which is a 12-bit, dual 3.2-GSPS or single 6.4-GSPS, RF-sampling analog-to-digital converter (ADC) with an LVDS interface. The EVM has single-ended AC-coupled analog inputs, onboard ADC clock generation, and (...)

  • Clocking provided by onboard LMX2582 clock synthesizer
  • 400-pin Samtec® SEARAY™ header connects directly to TSW14DL3200EVM data capture solution via LVDS interface
  • DATACONVERTERPRO-SW analysis tool provides complete environment for signal analysis, including data capture and storage of ADC EVM output
SLVC719.ZIP (40554 KB)

Software development

PLUG-INS Download
Abaco Systems® wideband low-latency high-speed ADC/DAC module mezzanine card
Provided by Abaco Systems The Abaco FMC172 module highlights the Texas Instruments low-latency ADC12DL3200 one-channel 6.4-GSPS analog-to-digital converter (ADC) in a daughtercard with an FPGA mezzanine card (FMC) connector. The combination of FMC172 >6-GHz bandwidth, high sample rate, and low latency is ideal (...)

Design tools & simulation

SLVMCP2.ZIP (53 KB) - IBIS Model
PSpice® for TI design and simulation tool
PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
  • Leverages Cadence PSpice Technology
  • Preinstalled library with a suite of digital models to enable worst-case timing analysis
  • Dynamic updates ensure you have access to most current device models
  • Optimized for simulation speed without loss of accuracy
  • Supports simultaneous analysis of multiple products
  • (...)
RF-Sampling Frequency Planner, Analog Filter, and DDC Excel™ Calculator
FREQ-DDC-FILTER-CALC This Excel calculator provides system designers a way to simplify the design and debugging of direct RF-sampling receivers. It offers three functions: frequency planning, analog filtering, and decimation filter spur location.

In the concept phase, a frequency-planning tool enables fine tuning of both (...)

  • Frequency planning
  • Analog filtering
  • Decimation filter spur location
SLVC726.ZIP (12398 KB)

CAD/CAE symbols

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Ordering & quality

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