The ADC12J1600 and ADC12J2700 devices are wideband sampling and digital tuning devices. Texas Instruments' giga-sample analog-to-digital converter (ADC) technology enables a large block of frequency spectrum to be sampled directly at RF. An integrated DDC (Digital Down Converter) provides digital filtering and down-conversion. The selected frequency block is made available on a JESD204B serial interface. Data is output as baseband 15-bit complex information for ease of downstream processing. Based on the digital down-converter (DDC) decimation and link output rate settings, this data is output on 1 to 5 lanes of the serial interface.
A DDC bypass mode allows the full rate 12-bit raw ADC data to also be output. This mode of operation requires 8 lanes of serial output.
The ADC12J1600 and ADC12J2700 devices are available in a 68-pin VQFN package. The device operates over the Industrial (–40°C ≤ TA ≤ 85°C) ambient temperature range.
|BODY SIZE (NOM)
|10.00 mm × 10.00 mm
|10.00 mm × 10.00 mm
- For all available packages, see the orderable addendum at the end of the datasheet.
Bypass — Spectral Response
ƒS = 2.7 GHz, FIN = 1897 MHz at –1 dBFS
4 Revision History
Changes from C Revision (July 2015) to D Revision
Changed reset value of address 0x006 from 0x03 to 0x13 in Memory Map tableGo
Changed reset value of address 0x006 from 0x03 to 0x13 in Standard SPI-3.0 Registers tableGo
Changed 0x03 to 0x13 in reset value and description of bits 7-0 and changed 0000 0011 to 0001 0011 in Chip Version Register sectionGo
Changes from B Revision (September 2014) to C Revision
Added additional voltage difference parameters to the Absolute Maximum Ratings tableGo
Added junction temperature to the Absolute Maximum Ratings tableGo
Added common mode voltage parameter to the Recommended Operating Conditions table. Changed CLK to SYSREF, and ~SYNC Go
Changed some of the maximum interleaving offset values for both devices to tighten the levels Go
Deleted the Differential Analog Input Connection image in The Analog Inputs section Go
Added note about offset adjust in Background Calibration Mode to the Offset Adjust section and I/O offset register tablesGo
Added the Calibration Cycle Timing for Different Calibration Modes and Options table in the Timing Calibration Mode sectionGo
Changed 0x004-0x005 to RESERVED in the Standard SPI-3.0 Registers summary tableGo
Changes from A Revision (February 2014) to B Revision
Changed the device status from Product Preview to Production DataGo