ADC12J2700

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12-Bit, 2.7-GSPS, RF Sampling Analog-to-Digital Converter (ADC)

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Product details

Parameters

Sample rate (Max) (MSPS) 2700 Resolution (Bits) 12 Number of input channels 1 Interface type JESD204B Analog input BW (MHz) 3200 Features Ultra High Speed Rating Catalog Input range (Vp-p) 0.725 Power consumption (Typ) (mW) 1800 Architecture Folding Interpolating SNR (dB) 55.1 ENOB (Bits) 8.8 SFDR (dB) 72 Operating temperature range (C) -40 to 85 Input buffer Yes open-in-new Find other High-speed ADCs (>10MSPS)

Package | Pins | Size

VQFNP (NKE) 68 100 mm² 10 x 10 open-in-new Find other High-speed ADCs (>10MSPS)

Features

  • Excellent Noise and Linearity up to and beyond FIN = 3 GHz
  • Configurable DDC
  • Decimation Factors from 4 to 32 (Complex Baseband Out)
  • Bypass Mode for Full Nyquist Output Bandwidth
  • Usable Output Bandwidth of 540 MHz at
    4x Decimation and 2700 MSPS
  • Usable Output Bandwidth of 320 MHz at
    4x Decimation and 1600 MSPS
  • Usable Output Bandwidth of 67.5 MHz at
    32x Decimation and 2700 MSPS
  • Usable Output Bandwidth of 40 MHz at
    32x Decimation and 1600 MSPS
  • Low Pin-Count JESD204B Subclass 1 Interface
  • Automatically Optimized Output Lane Count
  • Embedded Low Latency Signal Range Indication
  • Low Power Consumption
  • Key Specifications:
    • Max Sampling Rate: 1600 or 2700 MSPS
    • Min Sampling Rate: 1000 MSPS
    • DDC Output Word Size: 15-Bit Complex (30 bits total)
    • Bypass Output Word Size: 12-Bit Offset Binary
    • Noise Floor: –147.3 dBFS/Hz (ADC12J2700)
    • Noise Floor: –145 dBFS/Hz (ADC12J1600)
    • IMD3: −64 dBc (FIN = 2140 MHz ± 30 MHz at −13 dBFS)
    • FPBW (–3 dB): 3.2 GHz
    • Peak NPR: 46 dB
    • Supply Voltages: 1.9 V and 1.2 V
    • Power Consumption
      • Bypass (2700 MSPS): 1.8 W
      • Bypass (1600 MSPS): 1.6 W
      • Power Down Mode: <50 mW

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open-in-new Find other High-speed ADCs (>10MSPS)

Description

The ADC12J1600 and ADC12J2700 devices are wideband sampling and digital tuning devices. Texas Instruments’ giga-sample analog-to-digital converter (ADC) technology enables a large block of frequency spectrum to be sampled directly at RF. An integrated DDC (Digital Down Converter) provides digital filtering and down-conversion. The selected frequency block is made available on a JESD204B serial interface. Data is output as baseband 15-bit complex information for ease of downstream processing. Based on the digital down-converter (DDC) decimation and link output rate settings, this data is output on 1 to 5 lanes of the serial interface.

A DDC bypass mode allows the full rate 12-bit raw ADC data to also be output. This mode of operation requires 8 lanes of serial output.

The ADC12J1600 and ADC12J2700 devices are available in a 68-pin VQFN package. The device operates over the Industrial (–40°C ≤ TA ≤ 85°C) ambient temperature range.

open-in-new Find other High-speed ADCs (>10MSPS)
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Technical documentation

= Top documentation for this product selected by TI
No results found. Please clear your search and try again. View all 8
Type Title Date
* Datasheet ADC12Jxx00 12-Bit 1.6- or 2.7-GSPS ADCs With Integrated DDC datasheet (Rev. D) Oct. 19, 2017
Technical articles Keys to quick success using high-speed data converters Oct. 13, 2020
Technical articles How to achieve fast frequency hopping Mar. 03, 2019
Technical articles RF sampling: Learning more about latency Feb. 09, 2017
Technical articles Why phase noise matters in RF sampling converters Nov. 28, 2016
Application note System solution for avionics & defense Sep. 23, 2015
White paper Ready to make the jump to JESD204B? White Paper (Rev. B) Mar. 19, 2015
User guide ADC12J2700EVM and ADC12J1600EVM User's Guide Aug. 05, 2014

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARD Download
Description

The ADC12J2700EVM is an evaluation module (EVM) that allows for the evaluation of Texas Instruments’ ADC12J2700. The ADC12J2700 is a low power, 12-bit, 2.7-GSPS RF-sampling analog to digital converter (ADC) with a buffered analog input, integrated Digital Down Converter with programmable NCO and (...)

Features
  • Flexible transformer coupled analog input and clock input to allow for a variety of sources and frequencies
  • Easy to use software GUI to configure the ADC12J2700EVM, LMX2581 and LMK04828 for a variety of configurations through a USB interface
  • Quickly evaluate ADC performance through High Speed Data (...)

Software development

FIRMWARE Download
JESD204 Rapid Design IP for FPGAs connected to TI high-speed data converters
TI-JESD204-IP The JESD204 rapid design IP has been designed to enable FPGA engineers to achieve an accelerated path to a working JESD204 system. The IP has been architected in a way that downstream digital processing and other application logic are isolated from most of the performance- and timing-critical (...)
Features
  • Compatible with JEDEC JESD204a/b/c protocols
  • Supports subclass 1 deterministic latency and multidevice synchronization
  • Supported lane rates
    • Up to 16.375 Gbps in 8b/10b mode
    • Up to 20 Gbps in 64b/66b mode
  • Supports all protocol related error detection and reporting features
  • Integrated transport layer (...)
SUPPORT SOFTWARE Download
High-speed data converter pro software
DATACONVERTERPRO-SW This high-speed data converter pro GUI is a PC (Windows® XP/7 compatible) program designed to aid in evaluation of most TI high-speed data converter and analog front-end (AFE) platforms. Designed to support the entire TSW14xxx series of data-capture and pattern-generation cards (...)
Features
  • Compatible with TSW1400, TSW1405, TSW1406 and TSW14J10, TSW14J50, TSW14J56, and TSW14J57 pattern-generation and data-capture platforms
  • Works with all TI high-speed DAC, ADC, and AFE products
  • Provides time-domain and frequency-domain analysis
  • Supports single-tone, multi-tone, and modulated (...)

Design tools & simulation

SIMULATION MODEL Download
SLAM198A.ZIP (4134 KB) - IBIS-AMI Model
SIMULATION MODEL Download
SLAM223A.ZIP (24 KB) - IBIS Model
SIMULATION TOOL Download
PSpice® for TI design and simulation tool
PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Features
  • Leverages Cadence PSpice Technology
  • Preinstalled library with a suite of digital models to enable worst-case timing analysis
  • Dynamic updates ensure you have access to most current device models
  • Optimized for simulation speed without loss of accuracy
  • Supports simultaneous analysis of multiple products
  • (...)
CALCULATION TOOL Download
RF-Sampling Frequency Planner, Analog Filter, and DDC Excel™ Calculator
FREQ-DDC-FILTER-CALC This Excel calculator provides system designers a way to simplify the design and debugging of direct RF-sampling receivers. It offers three functions: frequency planning, analog filtering, and decimation filter spur location.

In the concept phase, a frequency-planning tool enables fine tuning of both (...)

Features
  • Frequency planning
  • Analog filtering
  • Decimation filter spur location

Reference designs

REFERENCE DESIGNS Download
Synchronization of JESD204B Giga-Sample ADCs using Xilinx Platform for Phased Array Radar Systems
TIDA-00432 This system level design shows how two ADC12J4000 evaluation modules (EVMs) can be synchronized together using a Xilinx VC707 platform. The design document describes the required hardware modifications and device configurations, including the clocking scheme. Example configuration files are shown (...)
document-generic Schematic

CAD/CAE symbols

Package Pins Download
VQFN (NKE) 68 View options

Ordering & quality

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  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring

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