SBASAU7C December   2024  – July 2025 ADC3548 , ADC3549

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - Power Consumption
    6. 6.6  Electrical Characteristics - DC Specifications
    7. 6.7  Electrical Characteristics - AC Specifications (ADC3548 - 250 MSPS)
    8. 6.8  Electrical Characteristics - AC Specifications (ADC3549 - 500 MSPS)
    9. 6.9  Timing Requirements
    10. 6.10 Typical Characteristics - ADC3548 (250MSPS)
    11. 6.11 Typical Characteristics - ADC3549 (500MSPS)
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog Inputs
        1. 8.3.1.1 Nyquist Zone Selection
        2. 8.3.1.2 Analog Front End Design
      2. 8.3.2 Sampling Clock
        1. 8.3.2.1 Multi-Chip Synchronization
        2. 8.3.2.2 SYSREF Monitor
      3. 8.3.3 Time-Stamp
      4. 8.3.4 Overrange
      5. 8.3.5 External Voltage Reference
      6. 8.3.6 Digital Gain
      7. 8.3.7 Decimation Filter
        1. 8.3.7.1 Uncommon Decimation Ratios
        2. 8.3.7.2 Decimation Filter Response
        3. 8.3.7.3 Decimation Filter Configuration
        4. 8.3.7.4 Numerically Controlled Oscillator (NCO)
      8. 8.3.8 Digital Interface
        1. 8.3.8.1 Parallel LVDS (SDR) - Default
        2. 8.3.8.2 Parallel LVDS (DDR)
        3. 8.3.8.3 SLVDS with Decimation
          1. 8.3.8.3.1 SLVDS - Status Bit Insertion
        4. 8.3.8.4 Output Data Format
        5. 8.3.8.5 32-bit Output Resolution
        6. 8.3.8.6 Output Scrambler
        7. 8.3.8.7 Output MUX
        8. 8.3.8.8 Test Pattern
    4. 8.4 Device Functional Modes
      1. 8.4.1 Low Latency Mode
      2. 8.4.2 Power Down Mode
    5. 8.5 Programming
      1. 8.5.1 GPIO Programming
      2. 8.5.2 Register Write
      3. 8.5.3 Register Read
      4. 8.5.4 Device Programming
      5. 8.5.5 Register Map
      6. 8.5.6 Register Description
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Wideband Spectrum Analyzer
      2. 9.2.2 Design Requirements
        1. 9.2.2.1 Input Signal Path
        2. 9.2.2.2 Clocking
      3. 9.2.3 Detailed Design Procedure
        1. 9.2.3.1 Sampling Clock
      4. 9.2.4 Application Performance Plots
      5. 9.2.5 Initialization Set Up
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Third-Party Products Disclaimer
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.5.6 Register Description

Figure 8-72 Register 0x025
7 6 5 4 3 2 1 0
0 0 0 CFG RDY 0 0 0 0
Table 8-18 Register 0x025 Field Descriptions
Bit Field Type Reset Description
7-5 0 R/W 0 Must write 0
0 CFG RDY R/W 0 This bit indicates the status of the internal fuse load after HW reset.
0: Fuse load not complete
1: Fuses are loaded, applied and device ready for programming.
3-0 0 R/W 0 Must write 0
Figure 8-73 Register 0x100
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 RESET
Table 8-19 Register 0x100 Field Descriptions
Bit Field Type Reset Description
7-1 0 R/W 0 Must write 0
0 RESET R/W 0 This bit resets all internal registers to the default values and self clears to 0.
Figure 8-74 Register 0x101
7 6 5 4 3 2 1 0
0 0 0 GBL PDN 0 0 0 0
Table 8-20 Register 0x101 Field Descriptions
Bit Field Type Reset Description
7-5 0 R/W 0 Must write 0
4 GBL PDN R/W 0 Global power down. This bit powers down the entire device. This feature is also available using GPIO pins.

0: normal operation
1: Device in global power down mode
3-0 0 R/W 0 Must write 0
Figure 8-75 Register 0x102
7 6 5 4 3 2 1 0
0 SYSREF DET CLR 0 0 0 0 0 0
Table 8-21 Register 0x102 Field Descriptions
Bit Field Type Reset Description
7 0 R/W 0 Must write 0
6 SYSREF DET CLR R/W 0 This bit resets the SYSREF DET flag (0x140, D6)

0: normal operation
1: SYSREF DET flag gets reset.
5-0 0 R/W 0 Must write 0
Figure 8-76 Register 0x104
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 CHA TERM
Table 8-22 Register 0x104 Field Descriptions
Bit Field Type Reset Description
7-1 0 R/W 0 Must write 0
0 CHA TERM R/W 0 ChA internal termination. This bit sets the internal termination on channel A.
0: 100Ω differential termination
1: 200Ω differential termination
Table 8-23 Register 0x10A
7 6 5 4 3 2 1 0
0 0 0 0 0 OVR CLR OVR STICKY
Table 8-24 Register 0x10A Field Descriptions
Bit Field Type Reset Description
7-3 0 R/W 0 Must write 0
2-1 OVR CLR R/W 0 This is useful for clearing the sticky bit. Setting a value of 0x2 clears the sticky OVR
0 OVR STICKY R/W 0 This bit makes the OVR sticky.
0: OVR is non-sticky (updated based on <OVR LENGTH>)
1: OVR is sticky (use <OVR CLR> to reset)
Table 8-25 Register 0x10B
7 6 5 4 3 2 1 0
OVR LENGTH
Table 8-26 Register 0x10B Field Descriptions
Bit Field Type Reset Description
7-0 OVR LENGTH R/W 0 This controls the OVR pulse expansion. This field species the expansion width in terms of the number of clock cycles. For example 0x0F sets the OVR length to 16 clock cycles.
Figure 8-77 Register 0x110
7 6 5 4 3 2 1 0
LVDS TERM 0 LVDS ½ SWING 0 0 SDR/DDR 0 0
Table 8-27 Register 0x110 Field Descriptions
Bit Field Type Reset Description
7 LVDS TERM R/W 0 This bit configures the LVDS termination resistance. Setting this bit enables 100 Ohm termination. The default termination resistance is 50Ω
6 0 R/W 0 Must write 0
5 LVDS ½ SWING R/W 0 This bit reduces the LVDS output swing by 50% to save power consumption.
0: Normal output swing
1: Reduced output swing
4-3 0 R/W 0 Must write 0
2 SDR/DDR R/W 1 This bit configures the parallel LVDS output interface. When only a single channel is output, SDR LVDS can be enabled.
0: DDR LVDS
1: SDR LVDS
1-0 0 R/W 0 Must write 0
Figure 8-78 Register 0x111/0x112
7 6 5 4 3 2 1 0
LVDS DATA INV [7:0]
LVDS DATA INV [15:8]
Table 8-28 Register 0x111/0x112 Field Descriptions
Bit Field Type Reset Description
7-0 LVDS DATA INV [15:0] R/W 0 These bits allow inverting of the polarity of individual LVDS output lanes as shown in Table 8-29.
0: Polarity as shown in pin diagram.
1: Polarity inverted
Table 8-29 LVDS data inversion register lane assignment
REG ADDR 0x112 0x111
REG BIT D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
LVDS OUTPUT LANE 8 9 10 11 12 13 14 15 7 6 5 4 3 2 1 0
Figure 8-79 Register 0x113/0x114
7 6 5 4 3 2 1 0
LVDS PDN [14:8] 0
0 0 0 0 0 0 0 LVDS PDN [15]
Table 8-30 Register 0x113/0x114 Field Descriptions
Bit Field Type Reset Description
7-0 LVDS PDN [15:8] R/W 0 These register bits power down the individual LVDS output lanes with LVDS pins into high impedance state (e.g. 0x113, D7 powers down output lane 14). The remaining LVDS lane (0-7) power down registers are in registers 0x691/0x692.
0: Normal operation
1: LVDS output lane powered down
7-0 0 R/W 0 Must write 0
Figure 8-80 Register 0x115
7 6 5 4 3 2 1 0
0 0 0 0 FCLK DC FCLK DIS 0 LVDS SCR EN
Table 8-31 Register 0x115 Field Descriptions
Bit Field Type Reset Description
7-4 0 R/W 0 Must write 0
3 FCLK DC R/W 0 This bit allows adjusting the FCLK duty cycle.
0: FCLK stays high for one DCLK cycle at the beginning of the output sample
1: FCLK stays high for 50% of the output sample
2 FCLK DIS R/W 0 This bit disables the output FCLK. FCLK is transmitted on lane DOUT0. In decimation modes where all 16 lanes are used, FCLK replaces the LSB.
0: FCLK replaces the LSB data and is transmitted on DOUT0
1: FCLK is disabled and the LSB data is transmitted on DOUT0.
1 0 R/W 0 Must write 0
0 0 R/W 0 Must write 0
Figure 8-81 Register 0x116
7 6 5 4 3 2 1 0
LVDS MUX EN LVDS SWAP RISE/FALL 0 0 0 LVDS SCR
Table 8-32 Register 0x116 Field Descriptions
Bit Field Type Reset Description
7 LVDS MUX EN R/W 0 This bit enables use of the LVDS output mux in registers 0x117..0x11E.
0: LVDS output mux disabled
1: LVDS output mux enabled
6 LVDS SWAP RISE/FALL R/W 0 This bit swaps the output data bits transmitted on rising and falling edge of DCLK.
0: Normal operation
1: Output bits on rising and falling edge are swapped.
5-3 0 R/W 0 Must write 0
2-0 LVDS SCR R/W 0 This field controls the scrambling and lsb insertion config on the output data
000: Default operation
001: Data is XOR'ed with a PRBS bit. This PRBS is inserted on the LSB position. The PRBS is generated using a large LFSR and can be treated as random for all practical scenarios
010: OVR is inserted on the LSB position
011: OVR is inserted on the LSB+1 position
100: Data is XOR'ed with a PRBS bit, and the PRBS is inserted on LSB+1 position
101: OVR is inserted on LSB+1 position, PRBS is inseted on LSB position. Data is XOR'ed with PRBS
110: OVR is inserted on LSB+2 position, PRBS is inseted on LSB+1 position. Data is XOR'ed with PRBS
111: Unused
Figure 8-82 Register 0x117...0x11E
7 6 5 4 3 2 1 0
DOUT1/3/5/7/9/11/13/15 MUX DOUT0/2/4/6/8/10/12/14 MUX
Table 8-33 Register 0x117...0x11E Field Descriptions
Bit Field Type Reset Description
7-4 DOUT1/3/5/7/9/11/13/15 MUX R/W 0000 These bits configure the data bus assignment for the individual output lanes.
0000: LVDS lane DOUTx carries data of internal digital bus lane DIG0
0001: LVDS lane DOUTx carries data of internal digital bus lane DIG1
...
1111: LVDS lane DOUTx carries data of internal digital bus lane DIG15
3-0 DOUT0/2/4/6/8/10/12/14 MUX R/W 0000
Figure 8-83 Register 0x132
7 6 5 4 3 2 1 0
HIGH FIN 0 0 0 0 0 0 0
Table 8-34 Register 0x132 Field Descriptions
Bit Field Type Reset Description
7 HIGH FIN R/W 0 This bit must be set for best AC performance for input frequencies greater than 500 MHz
0: Input frequencies < 500 MHz
1: Input frequencies > 500 MHz
6-0 0 R/W 0 Must write 0
Figure 8-84 Register 0x140
7 6 5 4 3 2 1 0
0 SYSREF EN SYSREF OR SYSREF X5 SYSREF X4 SYSREF X3 SYSREF X2 SYSREF X1
Table 8-35 Register 0x140 Field Descriptions
Bit Field Type Reset Description
7 0 R/W 0 Must write 0
6 SYSREF DET R/W 0 This register indicates if a SYSREF signal is detected. Upon detection this bit stays high until it gets reset (0x102, D6) or a device reset is issued.
0: no SYSREF signal detected
1: SYSREF signal detected
5 SYSREF OR R/W 0

This bit is the output of the five SYSREF XOR flags logically OR'ed together.
0: no SYSREF flag raised
1: one of the five SYSREF XOR flags is raised.
4-0 SYSREF X5..X1 R/W 0

These bits are the XOR flags from the SYSREF window monitoring circuitry. The sampling clock falling edge is used to capture the SYSREF signal. If a SYSREF signal transition happens within -60/+140 ps of the SYSREF capture, the appropriate XOR flag gets raised. These bits are updated on every SYSREF rising edge.
X1: SYSREF leading sample clock by 20 to 60ps
X2: SYSREF leading sample clock by 20ps to 0ps or SYSREF lagging sample clock by 0 to 20ps
X3: SYSREF lagging sample clock by up to 20 to 60ps
X4: SYSREF lagging sample clock by 60 to 100ps
X5: SYSREF lagging sample clock by 100 to 140ps
0: No SYSREF transition detected
1: SYSREF transition detected within given window
Figure 8-85 Register 0x146
7 6 5 4 3 2 1 0
0 0 0 GPIO CONFIG
Table 8-36 Register 0x146 Field Descriptions
Bit Field Type Reset Description
7-5 0 R/W 0 Must write 0
4-0 GPIO CONFIG R/W 0 These register bits configure the functionality of the two GPIO pins as shown in Table 8-37.
Table 8-37 GPIO pin configuration
GPIO CONFIG GPIO1 GPIO0
00000 NOT USED SYSREF
00011 GLOBAL POWER DOWN SYSREF
00100 EXTERNAL REFERENCE SYSREF
00101 NCO SWITCH1 NCO SWITCH0
01000 NOT USED SYSREF
01001 OVR CHA SYSREF
01010 NOT USED GLOBAL POWER DOWN
01011 OVR CHA GLOBAL POWER DOWN
10010 NOT USED OVR CHA
all others NOT USED
Figure 8-86 Register 0x14A
7 6 5 4 3 2 1 0
0 0 0 PATTERN CLK 0 TEST PATTERN
Table 8-38 Register 0x14A Field Descriptions
Bit Field Type Reset Description
7-5 0 R/W 0 Must write 0
4 PATTERN CLK R/W 0 This controls the clock of the pattern signal generator. Setting this bit switches the pattern generator clock to decimation clock.
3 0 R/W 0 Must write 0
2-0 TEST PATTERN R/W 0 This field controls the type of pattern injected. Default value is 0 and indicates that the pattern generator is off. The generated pattern is 20 bit wide. In 16 bit resolution mode, MSB 16 bits of the pattern mode are sent out. In 32 bit resolution mode, 12 zero bits are padded to the generated pattern and sent out.
000: Test pattern is disabled
001: Ramp pattern with a step of 1 (at 20 bit level, which is equivalent to 1/16 at 16 bit level)
010: Ramp pattern with a step value set by CUSTOM PATTERN. For example, to configure a ramp pattern with unit step in 16 bit mode, the CUSTOM PATTERN must be set to 0x010
011: Unused
100: Static pattern set by CUSTOM PATTERN
101: Pattern toggles between CUSTOM PATTERN and invert of CUSTOM PATTERN
110: Pattern toggles between CUSTOM PATTERN and 0
111: Unused
Figure 8-87 Register 0x14B/0x14C/0x14D
7 6 5 4 3 2 1 0
CUSTOM PATTERN [7:0]
CUSTOM PATTERN [15:8]
0 0 0 0 CUSTOM PATTERN [19:16]
Table 8-39 Register 0x14B/0x14C/0x14D Field Descriptions
Bit Field Type Reset Description
7-0 CUSTOM PATTERN [19:0] R/W 0 This filed controls the pattern generator. This controls different functions depending on the TEST PATTERN setting
Figure 8-88 Register 0x15B
7 6 5 4 3 2 1 0
DIGITAL GAIN CHA [7:0]
Table 8-40 Register 0x15B Field Descriptions
Bit Field Type Reset Description
7-0 DIGITAL GAIN CHA [7:0] R/W 0 This register controls digital gain for channel A and is interpreted as a 2's complement number. Maximum gain is 6dB(20 x log (1+(DIGITAL GAIN CHA / 128))).
Figure 8-89 Register 0x160
7 6 5 4 3 2 1 0
0 0 0 0 0 SPI SYSREF SYSREF MODE
Table 8-41 Register 0x160 Field Descriptions
Bit Field Type Reset Description
7-3 0 R/W 0 Must write 0
2 SPI SYSREF R/W 0 Must write 0
1-0 SYSREF MODE R/W 0 This controls the global SYSREF mask
00: Pass all SYSREF pulses
01: Pass the first SYSREF pulse and gates subsequent pulses
10: Gate all SYSREF pulses
11: Issue new SYSREF pulse. The pulse is issued when the state transitions to 11
Figure 8-90 Register 0x161
7 6 5 4 3 2 1 0
LVDS SYSREF MASK DEC SYSREF MASK NCO SYSREF MASK TIMER SYSREF MASK
Table 8-42 Register 0x161 Field Descriptions
Bit Field Type Reset Description
7-6 LVDS SYSREF MASK R/W 0 This controls the SYSREF pulse going to the LVDS block. Default setting is 0 and passes all SYSREF pulses.
00: Pass all SYSREF pulses
01: Pass the first SYSREF pulse and gates subsequent pulses
10: Gate all SYSREF pulses
11: Issue new SYSREF pulse. The pulse is issued when the state transitions to 11
5-4 DDC SYSREF MASK R/W 0 This controls the SYSREF pulse of DDC block. The value - function map is same as LVDS SYSREF MASK
3-2 NCO SYSREF MASK R/W 0 This controls the SYSREF pulse of NCO block. The value - function map is same as LVDS SYSREF MASK
1-0 TIMER SYSREF MASK R/W 0 This controls the SYSREF pulse of TIMER block. The value - function map is same as LVDS SYSREF MASK
Figure 8-91 Register 0x162
7 6 5 4 3 2 1 0
SYSREF TIME STAMP 0 6dB GAIN OVERRIDE COMPLEX DDC EN OUTPUT RES OUTPUT FORMAT
Table 8-43 Register 0x162 Field Descriptions
Bit Field Type Reset Description
7-6 SYSREF TIME STAMP R/W 0 Setting this field to 0x3 allows the SYSREF to replace the LSB. OVR_ON_LSB setting takes precedence
5 0 R/W 0 Must write 0
4-3 6dB GAIN OVERRIDE R/W 0 This field controls 6dB gain setting of the DDC. The 6dB gain is applied in COMPLEX DDC mode by default. Setting this to 0x3 forces 6dB gain on the DDC output, irrespective of the DDC mode. Setting this to 0x2 forces unity gain irrespective of the DDC mode.
2 COMPLEX DDC EN R/W 0 This bit enables complex decimation for all DDCs. The decimation factor is set in 0x167..0x169
0: Real decimation
1: Complex decimation
1 OUTPUT RES R/W 0

This bit increases the output resolution from 14-bit (DDC bypass)/ 16-bit (DDC) to 32-bit.


0: 14/16-bit output resolution
1: 32-bit output resolution
0 OUTPUT FORMAT R/W 0 This bit selects the output format
0: Output format is 2s complement
1: Output format is offset binary
Figure 8-92 Register 0x163
7 6 5 4 3 2 1 0
DDC3 MUX DDC2 MUX DDC1 MUX DDC0 MUX
Table 8-44 Register 0x163 Field Descriptions
Bit Field Type Reset Description
7-6 DDC3 MUX R/W 0 These register bits set the input data source to the individual decimation filters.
00: unconnected
01: Channel A
others: not used
5-4 DDC2 MUX R/W 0 These register bits set the input data source to the individual decimation filters.
00: Channel A
01: unconnected
others: not used
3-2 DDC1 MUX R/W 0 These register bits set the input data source to the individual decimation filters.
00: unconnected
01: Channel A
others: not used
1-0 DDC0 MUX R/W 0 These register bits set the input data source to the individual decimation filters.
00: Channel A
01: unconnected
others: not used
Figure 8-93 Register 0x164
7 6 5 4 3 2 1 0
NCO3 UPDATE NCO2 UPDATE NCO1 UPDATE NCO0 UPDATE SEL NEG IM 0 0 NCO MODE
Table 8-45 Register 0x164 Field Descriptions
Bit Field Type Reset Description
7 NCO3 UPDATE R/W 0 A '0' to '1' transition in these register bits updates the four NCO frequencies of the respective NCOs.
6 NCO2 UPDATE R/W 0
5 NCO1 UPDATE R/W 0
4 NCO0 UPDATE R/W 0
3 SEL NEG IM R/W 0 This field contols the selection of negative frequency image, and is applicable only in COMPLEX DDC model.
2-1 0 R/W 0 Must write 0
0 NCO MODE R/W 0 This register configures the NCOs operating mode.
0: Phase continuous
1: Infinite phase coherent
Figure 8-94 Register 0x165
7 6 5 4 3 2 1 0
0 0 0 LOW LATENCY EN 0 DIS NCO AUTO UPDATE NCO SEL EN NCO COMMON UPDATE
Table 8-46 Register 0x165 Field Descriptions
Bit Field Type Reset Description
7-5 0 R/W 0 Must write 0
4 LOW LATENCY EN R/W 0 This bit enables low latency mode by bypassing all digital features.
0: Normal operation
1: Enables low latency mode
3 0 R/W 0 Must write 0
2 DIS NCO AUTO UPDATE R/W 0 This register bit disables the automatic update when switching the NCOs using GPIO pins
0: Normal operation
1: Automatic switch disabled
1 NCO SEL EN R/W 0 This bit enables NCO frequency selection via SPI register 0x166 instead of GPIO pins.
0: NCO frequency selection via GPIO pins
1: NCO frequency selection via register 0x166.
0 NCO COMMON UPDATE R/W 0 A '0' to '1' transition in this register bit updates the four NCO frequencies of all NCOs.
Figure 8-95 Register 0x166
7 6 5 4 3 2 1 0
DDC3 NCO SEL DDC2 NCO SEL DDC1 NCO SEL DDC0 NCO SEL
Table 8-47 Register 0x166 Field Descriptions
Bit Field Type Reset Description
7-6 DDC3 NCO SEL R/W 0 These bits select which of the 4 frequencies are active in the respective DDCs/NCOs. The <NCO SEL EN> bit in register 0x165 (D1) has to be set also.
5-4 DDC2 NCO SEL R/W 0
3-2 DDC1 NCO SEL R/W 0
1-0 DDC0 NCO SEL R/W 0
Figure 8-96 Register 0x167/168
7 6 5 4 3 2 1 0
DDC1/3 DECIMATION DDC0/2 DECIMATION
Table 8-48 Register 0x167/0x168 Field Descriptions
Bit Field Type Reset Description
7-4 DDC1/3 DECIMATION R/W 0 These bits set the decimation filter factors for the respective DDCs when using unequal decimation factors. Register <UNEQUAL DECIMATION> in register 0x169 (D7) has to be set also.
0000: DDC bypass
0001: Decimation by 2
0010: Decimation by 4
...
1110: Decimation by 16384
1111: Decimation by 32768
3-0 DDC0/2 DECIMATION R/W 0
Figure 8-97 Register 0x169
7 6 5 4 3 2 1 0
UNEQUAL DECIMATION 0 # OF DDCS DECIMATION (COMMON)
Table 8-49 Register 0x169 Field Descriptions
Bit Field Type Reset Description
7 UNEQUAL DECIMATION R/W 0 This bit enables configuration of DDC0..3 to have unequad decimation factors.
0: Common decimation factor for all DDCs
1: Unequal decimation factors
6 0 R/W 0 Must write 0
5-4 # OF DDCS R/W 00 This register configures the # of active DDCs
00: Dual DDC Mode
01: Quad DDC Mode
10: Single DDC Mode
11: not used
3-0 DECIMATION (COMMON) R/W 0000 This register bit set the decimation filter factors for all active DDCs.
0000: DDC bypass
0001: Decimation by 2
0010: Decimation by 4
...
1110: Decimation by 16384
1111: Decimation by 32768
Figure 8-98 Register 0x16B
7 6 5 4 3 2 1 0
0 0 0 UPDATE NYQUIST ZONE 0 NYQUIST ZONE
Table 8-50 Register 0x16B Field Descriptions
Bit Field Type Reset Description
7-5 0 R/W 0 Must write 0
4 UPDATE NYQUIST ZONE R/W 0 This field must be pulsed after the Nyquist zone if programmed. A 0 to 1 transition on this bit copies the NYQUIST ZONE filed to an internal register.
3 0 R/W 0 Must write 0
2-0 NYQUIST ZONE R/W 000 This field controls the nyquist zone of operation. The internal calibration of the device depends on the NYQUIST ZONE of the signal being sampled. This field must be programmed based on the operating Nyquist zone
000: First Nyquist zone (from 0 to Fs/2)
001: Second Nyquist (from Fs/2 to Fs)
010: Third Nyquist (from Fs to 3Fs/2)
011:Fourth Nyquist (from 3Fs/2 to 2Fs)
100: Fifth Nyquist (from 2Fs to 5Fs/2)
101: Sixth Nyquist (from 5Fs/2 to 3Fs)
110,111: not used
Figure 8-99 Register 0x200..0x2DF
7 6 5 4 3 2 1 0
DDCx NCO FREQUENCYy [48:0]
DDCx NCO PHASEy [15:0]
Table 8-51 Register 0x200..0x2DF Field Descriptions
Bit Field Type Reset Description
7-0 DDCx NCO FREQUENCYy [48:0] R/W 0 These register bits configure the 48-bit frequency words for the four DDCs/NCOs. The format is little endian.
7-0 DDCx NCO PHASEy [15:0] R/W 0 These register bits configure the starting phase of the four frequency words for the four DDCs/NCOs. The format is little endian. The phase value is: 90° / <16-bit register>
Figure 8-100 Register 0x590
7 6 5 4 3 2 1 0
0 0 0 0 0 0 ENABLE DCLK DIVIDER 0
Table 8-52 Register 0x590 Field Descriptions
Bit Field Type Reset Description
7-2 0 R/W 0 Must write 0
1 ENABLE DCLK DIVIDER R/W 0 Setting this bit enables the DCLK divider. This is required for high decimation factors when the bit clock of the LVDS is lower than the ADC clk.
Figure 8-101 Register 0x691/0x692
7 6 5 4 3 2 1 0
LVDS PDN [5:7] DCLK PDN 0 0 0 0
0 0 0 LVDS PDN [0:4]
Table 8-53 Register 0x691/0x692 Field Descriptions
Bit Field Type Reset Description
7-0 LVDS PDN [0:7] R/W 0 These register bits power down the individual LVDS output lanes with LVDS pins in high impedance state as shown in Table 8-54. The remaining LVDS bus power down registers are in registers 0x113/0x114.
0: Normal operation
1: LVDS output lane powered down
4 DCLK PDN R/W 0 This bit powers down the LVDS output clock.
0: Normal operation
1: DCLK powered down
Table 8-54 LVDS power down register lane assignment
REG ADDR 0x113 0x114 0x691 0x692
REG BIT D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
LVDS OUTPUT LANE 14 13 12 11 10 9 8 15 5 6 7 0 1 2 3 4