The ADS101x-Q1 are very small, low-power, noise-free, 12-bit, delta-sigma (ΔΣ) analog-to-digital converters (ADCs). The ADS101x-Q1 consist of a ΔΣ ADC core with an internal voltage reference, a clock oscillator and an I2C interface. The ADS1014-Q1 and ADS1015-Q1 also integrate a programmable gain amplifier (PGA) and a programmable digital comparator. Figure 7, Figure 8, and Figure 9 show the functional block diagrams of ADS1015-Q1, ADS1014-Q1, and ADS1013-Q1, respectively.
The ADS101x-Q1 ADC core measures a differential signal, VIN, that is the difference of V(AINP) and V(AINN). The converter core consists of a differential, switched-capacitor ΔΣ modulator followed by a digital filter. This architecture results in a very strong attenuation of any common-mode signals. Input signals are compared to the internal voltage reference. The digital filter receives a high-speed bitstream from the modulator and outputs a code proportional to the input voltage.
The ADS101x-Q1 have two available conversion modes: single-shot and continuous-conversion. In single-shot mode, the ADC performs one conversion of the input signal upon request, stores the conversion value to an internal conversion register, and then enters a power-down state. This mode is intended to provide significant power savings in systems that only require periodic conversions or when there are long idle periods between conversions. In continuous-conversion mode, the ADC automatically begins a conversion of the input signal as soon as the previous conversion is completed. The rate of continuous conversion is equal to the programmed data rate. Data can be read at any time and always reflect the most recent completed conversion.