SBAS558C December   2012  – December 2015 ADS42B49

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 ADS424x and ADS422x Family Comparison
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Thermal Information
    5. 8.5  Electrical Characteristics: ADS42B49 (250 MSPS)
    6. 8.6  Electrical Characteristics: General
    7. 8.7  Digital Characteristics
    8. 8.8  Timing Requirements: LVDS and CMOS Modes
    9. 8.9  Serial Interface Timing Characteristics
    10. 8.10 Reset Timing (Only When Serial Interface is Used)
    11. 8.11 LVDS Timings at Lower Sampling Frequencies
    12. 8.12 CMOS Timings at Lower Sampling Frequencies
    13. 8.13 Typical Characteristics
      1. 8.13.1 ADS42B49
      2. 8.13.2 Contour
  9. 9 Parameter Measurement Information
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1 Migrating from the ADS62P49 and ADS4249
      2. 10.3.2 Digital Functions
      3. 10.3.3 Gain for SFDR and SNR Trade-Off
      4. 10.3.4 Offset Correction
    4. 10.4 Device Functional Modes
      1. 10.4.1 Power-Down
        1. 10.4.1.1 Global Power-Down
        2. 10.4.1.2 Channel Standby
        3. 10.4.1.3 Input Clock Stop
      2. 10.4.2 Digital Output Information
        1. 10.4.2.1 Output Interface
        2. 10.4.2.2 DDR LVDS Outputs
        3. 10.4.2.3 LVDS Buffer
        4. 10.4.2.4 Parallel CMOS Interface
        5. 10.4.2.5 CMOS Interface Power Dissipation
        6. 10.4.2.6 Multiplexed Mode of Operation
        7. 10.4.2.7 Output Data Format
      3. 10.4.3 Parallel Configuration Details
    5. 10.5 Programming
      1. 10.5.1 Parallel Configuration Only
      2. 10.5.2 Serial Interface Configuration Only
      3. 10.5.3 Using Both Serial Interface and Parallel Controls
      4. 10.5.4 Serial Interface Details
        1. 10.5.4.1 Register Initialization
        2. 10.5.4.2 Serial Register Readout
    6. 10.6 Register Maps
      1. 10.6.1 Register Description
  11. 11Application and Implementation
    1. 11.1 Application Information
      1. 11.1.1 Driving Circuit
        1. 11.1.1.1 Drive Circuit Requirements
      2. 11.1.2 Clock Input
    2. 11.2 Typical Application
      1. 11.2.1 Design Requirements
      2. 11.2.2 Detailed Design Procedure
        1. 11.2.2.1 Analog Input
        2. 11.2.2.2 Clock Driver
        3. 11.2.2.3 Digital Interface
      3. 11.2.3 Application Curves
  12. 12Power Supply Recommendations
    1. 12.1 Using DC/DC Power Supplies
    2. 12.2 Power Supply Bypassing
  13. 13Layout
    1. 13.1 Layout Guidelines
      1. 13.1.1 Grounding
      2. 13.1.2 Supply Decoupling
      3. 13.1.3 Exposed Pad
      4. 13.1.4 Routing Analog Inputs
    2. 13.2 Layout Example
  14. 14Device and Documentation Support
    1. 14.1 Device Support
      1. 14.1.1 Device Nomenclature
    2. 14.2 Documentation Support
      1. 14.2.1 Related Documentation
    3. 14.3 Community Resources
    4. 14.4 Trademarks
    5. 14.5 Electrostatic Discharge Caution
    6. 14.6 Glossary
  15. 15Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Specifications

8.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Supply voltage AVDD –0.3 2.1 V
AVDD_BUF –0.3 3.6 V
DRVDD –0.3 2.1 V
Voltage between: AGND and DRGND –0.3 0.3 V
AVDD to DRVDD
(when AVDD leads DRVDD)		 –2.4 2.4 V
DRVDD to AVDD
(when DRVDD leads AVDD)		 –2.4 2.4 V
AVDD_BUF to DRVDD and AVDD –3.9 3.9 V
Voltage applied to INP, INM –0.3 Minimum
(3, AVDD_BUF + 0.3)		 V
CLKP, CLKM(2) –0.3 AVDD + 0.3 V
RESET, SCLK, SDATA, SEN,
CTRL1, CTRL2, CTRL3		 –0.3 3.9 V
Temperature Operating free-air, TA –40 85 °C
Operating junction, TJ 125 °C
Storage, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) When AVDD is turned off, TI recommends switching off the input clock (or ensuring the voltage on CLKP, CLKM is less than |0.3 V|). This configuration prevents the ESD protection diodes at the clock input pins from turning on.

8.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

8.3 Recommended Operating Conditions

over operating free-air temperature range, unless otherwise noted.
PARAMETER MIN NOM MAX UNIT
SUPPLIES
AVDD Analog supply voltage 1.8 1.9 2 V
AVDD_BUF Analog buffer supply voltage 3.15 3.3 3.45 V
DRVDD Digital supply voltage 1.7 1.8 2 V
ANALOG INPUTS
VID Differential input voltage range 2 VPP
VICR Input common-mode voltage VCM ± 0.05 V
Maximum analog input frequency with 2-VPP input amplitude(1) 400 MHz
Maximum analog input frequency with 1.6-VPP input amplitude(1) 500 MHz
CLOCK INPUT
Input clock sample rate Low-speed mode enabled(2) 1 80 MSPS
Low-speed mode disabled(2) (by default after reset) 80 250 MSPS
Input clock amplitude differential
(VCLKP – VCLKM)		 Sine wave, ac-coupled 0.2 1.5 VPP
LVPECL, ac-coupled 1.6 VPP
LVDS, ac-coupled 0.7 VPP
LVCMOS, single-ended, ac-coupled 1.5 V
Input clock duty cycle Low-speed mode disabled 45% 50% 55%
Low-speed mode enabled 40% 50% 60%
DIGITAL OUTPUTS
CLOAD Maximum external load capacitance from each output pin to DRGND 3.3 pF
RLOAD Differential load resistance between the LVDS output pairs (LVDS mode) 100 Ω
TA Operating free-air temperature –40 85 °C
(1) See the Analog Input section in the Application Information.
(2) See the Serial Interface Configuration section for details on programming the low-speed mode.

8.4 Thermal Information

THERMAL METRIC(1) ADS42B49 UNIT
RGC (VQFN)
64 PINS
RθJA Junction-to-ambient thermal resistance 23.9 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 10.9 °C/W
RθJB Junction-to-board thermal resistance 4.3 °C/W
ψJT Junction-to-top characterization parameter 0.1 °C/W
ψJB Junction-to-board characterization parameter 4.4 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 0.6 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

8.5 Electrical Characteristics: ADS42B49 (250 MSPS)

Typical values are at 25°C, AVDD = 1.9 V, AVDD_BUF = 3.3 V, DRVDD = 1.8 V, 50% clock duty cycle, –1-dBFS differential analog input, LVDS interface, and 0-dB gain, unless otherwise noted. Minimum and maximum values are across the full temperature range: TMIN = –40°C to TMAX = 85°C, AVDD = 1.9 V, AVDD_BUF = 3.3 V, and DRVDD = 1.8 V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Resolution 14 Bits
SNR Signal-to-noise ratio fIN = 10 MHz 71.3 dBFS
fIN = 70 MHz 71.2
fIN = 100 MHz 71.1
fIN = 170 MHz, 0-dB gain 68 70.7
fIN = 170 MHz, 3-dB gain 67.8
fIN = 300 MHz 69.5
SINAD Signal-to-noise and
distortion ratio		 fIN = 10 MHz 71 dBFS
fIN = 70 MHz 71
fIN = 100 MHz 70.9
fIN = 170 MHz, 0-dB gain 67 70.4
fIN = 170 MHz, 3-dB gain 67.7
fIN = 300 MHz 67.7
SFDR Spurious-free dynamic range fIN = 10 MHz 83 dBc
fIN = 70 MHz 87
fIN = 100 MHz 86
fIN = 170 MHz, 0-dB gain 73 85
fIN = 170 MHz, 3-dB gain 89
fIN = 300 MHz 73
THD Total harmonic distortion fIN = 10 MHz 82 dBc
fIN = 70 MHz 84
fIN = 100 MHz 85
fIN = 170 MHz, 0-dB gain 70 83
fIN = 170 MHz, 3-dB gain 86
fIN = 300 MHz 72
HD2 Second-harmonic distortion fIN = 10 MHz 95 dBc
fIN = 70 MHz 93
fIN = 100 MHz 98
fIN = 170 MHz, 0-dB gain 73 89
fIN = 170 MHz, 3-dB gain 94
fIN = 300 MHz 80
HD3 Third-harmonic distortion fIN = 10 MHz 83 dBc
fIN = 70 MHz 87
fIN = 100 MHz 86
fIN = 170 MHz, 0-dB gain 73 85
fIN = 170 MHz, 3-dB gain 89
fIN = 300 MHz 73
Worst spur
(other than second and third harmonics)		 fIN = 10 MHz 100 dBc
fIN = 70 MHz 100
fIN = 100 MHz 100
fIN = 170 MHz, 0-dB gain 84 95
fIN = 170 MHz, 3-dB gain 97
fIN = 300 MHz 94
IMD Two-tone intermodulation distortion f1 = 46 MHz, f2 = 50 MHz,
each tone at –7 dBFS		 88 dBFS
f1 = 185 MHz, f2 = 190 MHz,
each tone at –7 dBFS		 83
Crosstalk 10-MHz full-scale signal on channel under observation; 170-MHz full-scale signal on other channel > 85 dB
Input overload recovery Recovery to within 1%
(of full-scale) for 6-dB overload with sine-wave input		 1 Clock cycle
PSRR AC power-supply rejection ratio For 50-mVPP signal on AVDD supply 30 dB
ENOB Effective number of bits fIN = 170 MHz 11.4 LSBs

8.6 Electrical Characteristics: General

Typical values are at 25°C, AVDD = 1.9 V, AVDD_BUF = 3.3 V, DRVDD = 1.8 V, 50% clock duty cycle, and –1-dBFS differential analog input, unless otherwise noted. Minimum and maximum values are across the full temperature range: TMIN = –40°C to TMAX = 85°C, AVDD = 1.9 V, AVDD_BUF = 3.3 V, and DRVDD = 1.8 V.
PARAMETER MIN TYP MAX UNIT
ANALOG INPUTS
VID Differential input voltage range 2 VPP
Differential input resistance (at 170 MHz) 1.2 kΩ
Differential input capacitance (at 170 MHz) 2.2 pF
Analog input bandwidth
(with 50-Ω source impedance, and 50-Ω termination)		 700 MHz
VCM Common-mode output voltage 1.9(2) V
VCM output current capability 10 mA
DC ACCURACY
Offset error –20 3 20 mV
EGREF Gain error as a result of internal reference inaccuracy alone –2 2 %FS
EGCHAN Gain error of channel alone –5 %FS
Temperature coefficient of EGCHAN 0.005 Δ%/°C
POWER SUPPLY
IAVDD Analog supply current 186 225 mA
IAVDD_BUF Analog buffer supply current 67 90 mA
IDRVDD Output buffer supply current LVDS interface, 350-mV swing with 100-Ω external termination, fIN = 2.5 MHz 151 180 mA
CMOS interface, 8-pF external load capacitance,
fIN = 2.5 MHz(1)		 128 mA
Analog power 353 mW
Analog buffer power 224 mW
Digital power, LVDS interface, 350-mV swing with 100-Ω external termination, fIN = 2.5 MHz 272 mW
Digital power, CMOS interface, 8-pF external load capacitance,(1) fIN = 2.5 MHz 230 mW
Total power, LVDS interface, 350-mV swing with 100-Ω external termination, fIN = 2.5 MHz 850 925 mW
Global power-down 20 mW
(1) In CMOS mode, the DRVDD current scales with the sampling frequency, the load capacitance on output pins, input frequency, and the supply voltage (see the CMOS Interface Power Dissipation section in the Application Information).
(2) After the HIGH PERF MODE[10:0] bits are set.

8.7 Digital Characteristics

At AVDD = 1.9 V, AVDD_BUF = 3.3 V, and DRVDD = 1.8 V, unless otherwise noted. DC specifications refer to the condition where the digital outputs do not switch, but are permanently at a valid logic level 0 or 1.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DIGITAL INPUTS (RESET, SCLK, SDATA, SEN, CTRL1, CTRL2, CTRL3)(1)
VIH High-level input voltage All digital inputs support 1.8-V and 3.3-V CMOS logic levels 1.3 V
VIL Low-level input voltage 0.4 V
IIH High-level input current SDATA, SCLK(2) VHIGH = 1.8 V 10 µA
SEN(3) VHIGH = 1.8 V 0
IIL Low-level input current SDATA, SCLK VLOW = 0 V 0 µA
SEN VLOW = 0 V 10
DIGITAL OUTPUTS, CMOS INTERFACE (DA[13:0], DB[13:0], CLKOUT, SDOUT)
VOH High-level output voltage DRVDD – 0.1 DRVDD V
VOL Low-level output voltage 0 0.1 V
CO Output capacitance (internal to device) pF
DIGITAL OUTPUTS, LVDS INTERFACE
VODH High-level output differential voltage With an external
100-Ω termination		 275 350 425 mV
VODL Low-level output differential voltage With an external
100-Ω termination		 –425 –350 –275 mV
VOCM Output common-mode voltage 0.9 1.05 1.25 V
(1) SCLK, SDATA, and SEN function as digital input pins in serial configuration mode.
(2) SDATA and SCLK have an internal 150-kΩ pull-down resistor.
(3) SEN has an internal 150-kΩ pull-up resistor to AVDD. Because the pull-up resistor is weak, SEN can also be driven by 1.8-V or 3.3-V CMOS buffers.

8.8 Timing Requirements: LVDS and CMOS Modes

Typical values are at 25°C, AVDD = 1.9 V, AVDD_BUF = 3.3 V, DRVDD = 1.8 V, sampling frequency = 250 MSPS, sine wave input clock, CLOAD = 3.3 pF, and RLOAD = 100 Ω, unless otherwise noted. Minimum and maximum values are across the full temperature range: TMIN = –40°C to TMAX = 85°C, AVDD = 1.9 V, AVDD_BUF = 3.3 V, and DRVDD = 1.7 V to 2 V.
MIN NOM MAX UNIT
tA Aperture delay 0.5 0.8 1.1 ns
Aperture delay matching Between two channels of the same device ±70 ps
Variation of aperture delay Between two devices at the same temperature and DRVDD supply ±150 ps
tJ Aperture jitter 120 fS rms
Wakeup time Time to valid data after coming out of STANDBY mode 50 µs
Time to valid data after coming out of GLOBAL power-down mode 100 µs
ADC latency(4) Default latency after reset 11 Clock cycles
Digital functions enabled (EN DIGITAL = 1) 19 Clock cycles
DDR LVDS MODE(1)(2)
tSU_RISE Data setup time on rising edge of CLKOUTP Data valid to zero-crossing of differential output clock (CLKOUTP – CLKOUTM)(3) 0.32 0.68 ns
tHO_RISE Data hold time on rising edge of CLKOUTP Zero-crossing of differential output clock (CLKOUTP – CLKOUTM) to data becoming invalid(3) 0.5 0.82 ns
tSU_FALL Data setup time on falling edge of CLKOUTP Data valid to zero-crossing of differential output clock (CLKOUTP – CLKOUTM)(3) 0.63 1.04 ns
tHO_FALL Data hold time on falling edge of CLKOUTP Zero-crossing of differential output clock (CLKOUTP – CLKOUTM) to data becoming invalid(3) 0.18 0.58 ns
tPDI Clock propagation delay Input clock rising edge cross-over to output clock (CLKOUTP – CLKOUTM) rising edge cross-over 7.6 8.9 10.2 ns
LVDS bit clock duty cycle Duty cycle of differential clock
(CLKOUTP – CLKOUTM)		 57%
tFALL,
tRISE		 Data fall time,
Data rise time		 Rise time measured from –100 mV to 100 mV
1 MSPS ≤ Sampling frequency ≤ 250 MSPS		 0.13 ns
tCLKRISE,
tCLKFALL		 Output clock rise time,
Output clock fall time		 Rise time measured from –100 mV to 100 mV
1 MSPS ≤ Sampling frequency ≤ 250 MSPS		 0.13 ns
tRISE,
tFALL		 Data rise time,
Data fall time		 Rise time measured from 20% to 80% of DRVDD
1 MSPS ≤ Sampling frequency ≤ 250 MSPS 		0.13 ns
tCLKRISE,
tCLKFALL		 Output clock rise time,
Output clock fall time		 Rise time measured from 20% to 80% of DRVDD
1 MSPS ≤ Sampling frequency ≤ 250 MSPS 		0.13 ns
PARALLEL CMOS MODE
tPDI Clock propagation delay Input clock rising edge cross-over to output clock rising edge cross-over 5.9 8.3 10.6 ns
Output clock duty cycle Duty cycle of output clock, CLKOUT
1 MSPS ≤ Sampling frequency ≤ 200 MSPS		 50%
tRISE,
tFALL		 Data rise time,
Data fall time 		Rise time measured from 20% to 80% of DRVDD
Fall time measured from 80% to 20% of DRVDD
1 MSPS ≤ Sampling frequency ≤ 200 MSPS		 0.7 ns
tCLKRISE,
tCLKFALL		 Output clock rise time
Output clock fall time 		Rise time measured from 20% to 80% of DRVDD
Fall time measured from 80% to 20% of DRVDD
1 MSPS ≤ Sampling frequency ≤ 200 MSPS		 0.7 ns
(1) Setup and hold values in DDR LVDS mode are taken with a delayed output clock by writing register 42h, value 30h.
(2) Measurements are done with a transmission line of a 100-Ω characteristic impedance between the device and load. Setup and hold time specifications take into account the effect of jitter on the output data and clock.
(3) Data valid refers to a logic high of 100 mV and a logic low of –100 mV.
(4) Overall latency = ADC latency + tPDI. At 250 MSPS, tPDI is greater than two clock periods. Therefore, overall latency at 250 MSPS = ADC latency + 2 clock cycles.

8.9 Serial Interface Timing Characteristics

Typical values at 25°C; minimum and maximum values across the full temperature range: TMIN = –40°C to TMAX = 85°C, AVDD = 1.9 V, AVDD_BUF = 3.3 V, and DRVDD = 1.8 V, unless otherwise noted.
MIN NOM MAX UNIT
fSCLK SCLK frequency (equal to 1 / tSCLK) > dc 20 MHz
tSLOADS SEN to SCLK setup time 25 ns
tSLOADH SCLK to SEN hold time 25 ns
tDSU SDATA setup time 25 ns
tDH SDATA hold time 25 ns

8.10 Reset Timing (Only When Serial Interface is Used)

Typical values at 25°C; minimum and maximum values across the full temperature range: TMIN = –40°C to TMAX = 85°C, unless otherwise noted.
MIN NOM MAX UNIT
t1 Power-on delay Delay from AVDD and DRVDD power-up to active RESET pulse 1 ms
t2 Reset pulse width Active RESET signal pulse width 10 ns
1 µs
t3 Register write delay Delay from RESET disable to SEN active 100 ns

8.11 LVDS Timings at Lower Sampling Frequencies(1)

SAMPLING FREQUENCY (MSPS) SETUP TIME (ns) HOLD TIME (ns) CLOCK PROPAGATION
DELAY (ns)
tSU_RISE tSU_FALL tHO_RISE tHO_FALL tPDI
MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX
100 0.36 0.72 0.67 1.10 3.37 3.80 3.02 3.48 10.4 11.8 13.1
125 0.35 0.72 0.66 1.08 2.43 2.82 2.09 2.51 9.4 10.8 12.1
150 0.35 0.70 0.66 1.07 1.77 2.15 1.47 1.86 8.8 10.1 11.5
175 0.35 0.70 0.63 1.07 1.32 1.67 1.00 1.40 8.3 9.7 11.0
200 0.38 0.70 0.68 1.08 0.93 1.29 0.66 1.04 8.0 9.4 10.8
230 0.33 0.69 0.67 1.06 0.63 0.97 0.35 0.74 7.7 9.1 10.5
(1) Setup and hold values in DDR LVDS mode belong to delayed output clock by writing register 42h, value 30h.

8.12 CMOS Timings at Lower Sampling Frequencies

SAMPLING FREQUENCY (MSPS) SETUP TIME(1)
(tSU, ns)		 HOLD TIME(1)
(tHO, ns)		 CLOCK PROPAGATION DELAY
(tPDI, ns)
MIN TYP MAX MIN TYP MAX MIN TYP MAX
100 3.91 4.40 3.68 4.18 9.5 11.5 13.3
125 2.81 3.40 2.73 3.14 8.5 10.5 12.3
150 2.00 2.64 2.09 2.52 7.9 9.9 11.7
175 1.43 2.14 1.67 2.06 7.6 9.4 11.4
200 1.01 1.76 1.25 1.68 6.4 8.9 11.1
(1) In CMOS mode, setup time is measured from the beginning of data valid to the mid-point of the CLKOUT rising edge, whereas hold time is measured from the mid-point of the CLKOUT rising edge to data becoming invalid.

8.13 Typical Characteristics

8.13.1 ADS42B49

At TA = 25°C, AVDD = 1.9 V, AVDD_BUF = 3.3 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input clock, 1.5-VPP differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, high-performance mode disabled, 0-dB gain, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted.
ADS42B49 G001_FFT_FOR_10MHz_INPUT_SIGNAL.png Figure 1. Input Signal (10 MHz)
ADS42B49 G003_FFT_FOR_300MHz_INPUT_SIGNAL.png Figure 3. Input Signal (300 MHz)
ADS42B49 G005_FFT_FOR_TWO-TONE_INPUT_SIGNAL_M36dBFS_46MHz_50MHz.png Figure 5. Two-Tone Input Signal
ADS42B49 G007_FFT_FOR_TWO-TONE_INPUT_SIGNAL_M36dBFS_185MHz_190MHz.png Figure 7. Two-Tone Input Signal
ADS42B49 G009_IMD3_vs_INPUT_AMPLITUDE_185MHz_and_190MHz.png Figure 9. Two-Tone IMD3 vs Input Amplitude
ADS42B49 G011_SNR_vs_INPUT_FREQUENCY.png Figure 11. Signal-to-Noise Ratio vs Input Frequency
ADS42B49 G013_SNR_vs_DIGITAL_GAIN.png Figure 13. Signal-to-Noise Ratio
vs Gain and Input Frequency
ADS42B49 G015_PERFORMANCE_ACROSS_INPUT_AMPLITUDE_170MHz.png Figure 15. Performance vs Input Amplitude
ADS42B49 G017_PERFORMANCE_vs_INPUT_COMMON_MODE_VOLTAGE_170MHz.png Figure 17. Performance
vs Input Common-Mode Voltage
ADS42B49 G019_SNR_vs_AVDD_SUPPLY_and_TEMPERATURE_170MHz.png Figure 19. Signal-to-Noise Ratio
vs Temperature and AVDD Supply
ADS42B49 G021_SNR_vs_AVDD_BUF_SUPPLY_and_TEMPERATURE_170MHz.png Figure 21. Signal-to-Noise Ratio
vs Temperature and AVDD_BUF Supply
ADS42B49 G023_SNR_vs_DRVDD_SUPPLY_and_TEMPERATURE_170MHz.png Figure 23. Signal-to-Noise Ratio
vs Temperature and DRVDD Supply Voltage
ADS42B49 G025_PERFORMANCE_vs_CLOCK_DUTY_CYCLE_170MHz.png Figure 25. Performance vs Input Clock Duty Cycle
ADS42B49 G027_CMRR_vs_TEST_SIGNAL_FREQUENCY.png Figure 27. Common-Mode Rejection Ratio
vs Test Signal Frequency
ADS42B49 G029_PSRR_vs_TEST_SIGNAL_FREQUENCY.png Figure 29. Power-Supply Rejection Ratio
vs Test Signal Frequency
ADS42B49 G031_ANALOG_POWER_vs_SAMPLING_FREQUENCY.png Figure 31. Analog Power vs Sampling Frequency
ADS42B49 G002_FFT_FOR_170MHz_INPUT_SIGNAL.png Figure 2. Input Signal (170 MHz)
ADS42B49 G004_FFT_FOR_TWO-TONE_INPUT_SIGNAL_M7dBFS_46MHz_50MHz.png Figure 4. Two-Tone Input Signal
ADS42B49 G006_FFT_FOR_TWO-TONE_INPUT_SIGNAL_M7dBFS_185MHz_190MHz.png Figure 6. Two-Tone Input Signal
ADS42B49 G008_IMD3_vs_INPUT_AMPLITUDE_46MHz_and_50MHz.png Figure 8. Two-Tone IMD3 vs Input Amplitude
ADS42B49 G010_SFDR_vs_INPUT_FREQUENCY.png Figure 10. Spurious-Free Dynamic Range
vs Input Frequency
ADS42B49 G012_SFDR_vs_DIGITAL_GAIN.png Figure 12. Spurious-Free Dynamic Range
vs Gain and Input Frequency
Figure 14. Performance vs Input Amplitude
ADS42B49 G016_PERFORMANCE_vs_INPUT_COMMON_MODE_VOLTAGE_40MHz.png Figure 16. Performance
vs Input Common-Mode Voltage
ADS42B49 G018_SFDR_vs_AVDD_SUPPLY_and_TEMPERATURE_170MHz.png Figure 18. Spurious-Free Dynamic Range
vs Temperature and AVDD Supply
ADS42B49 G020_SFDR_vs_AVDD_BUF_SUPPLY_and_TEMPERATURE_170MHz.png Figure 20. Spurious-Free Dynamic Range
vs Temperature and AVDD_BUF Supply
ADS42B49 G022_SFDR_vs_DRVDD_SUPPLY_and_TEMPERATURE_170MHz.png Figure 22. Spurious-Free Dynamic Range
vs Temperature and DRVDD Supply Voltage
ADS42B49 G024_PERFORMANCE_vs_CLOCK_AMPLITUDE_170MHz.png Figure 24. Performance vs Input Clock Amplitude
ADS42B49 G026_CMRR_FFT.png Figure 26. Common-Mode Rejection Ratio Plot
ADS42B49 G028_PSRR_FFT_FOR_AVDD_SUPPLY.png Figure 28. Power-Supply Rejection Ratio Plot
ADS42B49 G030_TOTAL_POWER_vs_SAMPLING_FREQUENCY.png Figure 30. Total Power vs Sampling Frequency
ADS42B49 G032_DIGITAL_POWER_vs_SAMPLING_FREQUENCY.png Figure 32. Digital Power vs Sampling Frequency

8.13.2 Contour

All graphs are at 25°C, AVDD = 1.8 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input clock. 1.5-VPP differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, high-performance mode disabled, 0-dB gain, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted.
ADS42B49 tc_contour_sfdr_0db_bas558.gif Figure 33. Spurious-Free Dynamic Range (0-dB Gain)
ADS42B49 tc_contour_snr_0db_bas558.gif Figure 35. Signal-to-Noise Ratio (0-dB Gain)
ADS42B49 tc_contour_sfdr_6db_bas558.gif Figure 34. Spurious-Free Dynamic Range (6-dB Gain)
ADS42B49 tc_contour_snr_6db_bas558.gif Figure 36. Signal-to-Noise Ratio (6-dB Gain)