SLAS525D July   2007  – December 2017 ADS5474

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Clock Inputs
      2. 7.3.2 Digital Outputs
    4. 7.4 Device Functional Modes
      1. 7.4.1 External Voltage Reference
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Clocking Source for ADC5474
        2. 8.2.2.2 Amplifier Selection
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Power Supplies
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 PowerPAD Package
        1. 10.1.1.1 Assembly Process
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

PFP Package
80-Pin HTQFP With PowerPAD
Top View
ADS5474 po_slas525.gif
1. NC - No internal connection.

Pin Functions

PIN DESCRIPTION
NAME NO. TYPE
AIN 16 I Differential input signal (positive)
AIN 17 I Differential input signal (negative)
AVDD5 3 Analog power supply (5 V)
8
13
14
19
21
23
25
27
31
AVDD3 35 Analog power supply (3.3 V) (suggestion for ≤ 250 MSPS: leave option to connect to 5 V for ADS5440, ADS5444 13-bit compatibility)
37
39
DVDD3 1 Digital and output driver power supply (3.3 V)
51
66
AGND 7 Analog Ground
9
12
15
18
20
22
24
26
28
30
32
34
36
38
40
DGND 2 Digital Ground
52
65
CLK 10 I Differential input clock (positive). Conversion is initiated on rising edge, digital outputs on falling edge.
CLK 11 I Differential input clock (negative)
D0 48 O LVDS digital output pair, least significant bit (LSB)
D0 47
D1 50 O LVDS digital output pairs
D1 49
D2 54
D2 53
D3 56
D3 55
D4 58
D4 57
D5 60
D5 59
D6 62
D6 61
D7 64
D7 63
D8 68
D8 67
D9 70
D9 69
D10 72
D10 71
D11 74
D11 73
D12 76
D12 75
D13 78 O LVDS digital output pair, most significant bit (MSB)
D13 77
DRY 80 O Data ready LVDS output pair
DRY 79
NC 4 - No connection (pins 4 and 5 should be left floating)
5
43 - No connection (pins 43 to 46 are possible future bit additions for this pinout and therefore can be connected to a digital bus or left floating)
44
45
46
OVR 42 O Overrange indicator LVDS output. A logic high signals an analog input in excess of the full-scale range.
OVR 41
VCM 29 O Common-mode voltage output (3.1 V nominal). Commonly used in DC-coupled applications to set the input signal to the correct common-mode voltage. A 0.1-μF capacitor from VCM to AGND is recommended, but not required.
(This pin is not used on the ADS5440, ADS5444, and ADS5463)
PWD 33 Power-down (active high). Device is in sleep mode when PWD pin is logic HIGH. ADC converter is awake when PWD is logic LOW (grounded).
(This pin is not used on the ADS5440, ADS5444, and ADS5463)
VREF 6 Reference voltage input/output (2.4 V nominal). A 0.1-μF capacitor from VREF to AGND is recommended, but not required.
(Power Pad) (not numbered) Power Pad for thermal relief, also Analog Ground