SBAS756A February 2016 – March 2016 ADS54J42
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
The steps described in Table 66 are recommended as the power-up sequence with the ADS54J42 in 20X mode (LMFS = 8224).
|STEP||SEQUENCE||DESCRIPTION||PAGE BEING PROGRAMMED||COMMENT|
|1||Power-up the device||Bring up the supplies to IOVDD = 1.15 V, DVDD = AVDD = 1.9 V, and AVDD3V = 3.0 V.||—||These supplies can be brought up in any order.|
|2||Reset the device||Hardware reset|
|Apply a hardware reset by pulsing pin 48 (low → high → low).||A hardware reset clears all registers to their default values.|
|Register writes are equivalent to a hardware reset.||—|
|Write address 0-000h with 81h.||General register||Reset registers in the ADC and master pages of the analog bank.|
|This bit is a self-clearing bit.|
|Write address 4-001h with 00h and address 4-002h with 00h.||Unused page||Clear any unwanted content from the unused pages of the JESD bank.|
|Write address 4-003h with 00h and address 4-004h with 68h.||—||Select the main digital page of the JESD bank.|
|Write address 6-0F7h with 01h for channel A.||Main digital page
|Use the DIG RESET register bit to reset all pages in the JESD bank.|
|This bit is a self-clearing bit.|
|Write address 6-000h with 01h, then address 6-000h with 00h.||Pulse the PULSE RESET register bit for channel A.|
|3||Performance modes||Write address 0-011h with 80h.||—||Select the master page of the analog bank.|
|Write address 0-059h with 20h.||Master page
|Set the ALWAYS WRITE 1 bit.|
|Write address 0-039h with C0h.
Write address 0-03Ah with 40h.
Write address 0-056h with 04h.
Set these register bits for better SFDR when input frequency > 400 MHz.
|4||Program desired registers for
decimation options and
JESD link configuration
|Default register writes for DDC modes and JESD link configuration (LMFS 8224).|
|Write address 4-003h with 00h and address 4-004h with 69h.||—||Select the JESD digital page.|
|Write address 6-000h with 80h.||JESD
|Set the CTRL K bit for both channels by programming K according to the SYSREF signal later on in the sequence.|
|JESD link is configured with LMFS = 8224 by default with no decimation.||See Table 13 for configuring the JESD digital page registers for the desired LMFS and programming appropriate DDC mode.|
|Write address 4-003h with 00h and address 4-004h with 6Ah.||—||Select the JESD analog page.|
|JESD link is configured with LMFS = 8224 by default with no decimation.||JESD
|See Table 13 for configuring the JESD analog page registers for the desired LMFS and programming appropriate DDC mode.|
|Write address 6-017h with 40h.||PLL reset.|
|Write address 6-017h with 00h.||PLL reset.|
|Write address 4-003h with 00h and address 4-004h with 68h.||—||Select the main digital page.|
|JESD link is configured with LMFS = 8224 by default with no decimation.||Main digital page
|See Table 13 for configuring the main digital page registers for the desired LMFS and programming appropriate DDC mode.|
|Write address 6-000h with 01h and address 6-000h with 00h.||Pulse the PULSE RESET register bit. All settings programmed in the main digital page take effect only after this bit is pulsed.|
|5||Set the value of K and the SYSREF signal frequency accordingly||Write address 4-003h with 00h and address 4-004h with 69h.||—||Select the JESD digital page.|
|Write address 6-006h with XXh (choose the value of K).||JESD
|See the SYSREF Signal section to choose the correct frequency for SYSREF.|
|6||JESD lane alignment||Pull the SYNCB pin (pin 63) low.||—||Transmit K28.5 characters.|
|Pull the SYNCB pin high.||After the receiver is synchronized, initiate an ILA phase and subsequent transmissions of ADC data.|
|t1||Power-on delay: delay from power-up to an active high RESET pulse||1||ms|
|t2||Reset pulse duration: active high RESET pulse duration||10||ns|
|t3||Register write delay from RESET disable to SEN active||100||ns|
The signal-to-noise ratio (SNR) of the ADC is limited by three different factors: quantization noise, thermal noise, and jitter, as shown in Equation 4. The quantization noise is typically not noticeable in pipeline converters and is 86 dBFS for a 14-bit ADC. The thermal noise limits SNR at low input frequencies and the clock jitter sets SNR for higher input frequencies.
The SNR limitation resulting from sample clock jitter can be calculated by Equation 5:
The total clock jitter (TJitter) has two components: the internal aperture jitter (130 fs) is set by the noise of the clock input buffer and the external clock jitter. TJitter can be calculated by Equation 6:
External clock jitter can be minimized by using high-quality clock sources and jitter cleaners as well as band-pass filters at the clock input. A faster clock slew rate also improves the ADC aperture jitter.
The ADS54J42 has a thermal noise of approximately 71.1 dBFS and an internal aperture jitter of 120 fS. SNR, depending on the amount of external jitter for different input frequencies, is shown in Figure 132.
The ADS54J42 is designed for wideband receiver applications demanding excellent dynamic range over a large input frequency range. A typical schematic for an ac-coupled receiver is shown in Figure 133.
NOTE:GND = AGND and DGND are connected in the PCB layout.
Typical applications involving transformer-coupled circuits are discussed in this section. Transformers (such as ADT1-1WT or WBC1-1) can be used up to 300 MHz to achieve good phase and amplitude balances at the ADC inputs. When designing dc-driving circuits, the ADC input impedance must be considered. Figure 134 and Figure 135 show the impedance (ZIN = RIN || CIN) across the ADC input pins.
By using the simple drive circuit of Figure 136, uniform performance can be obtained over a wide frequency range. The buffers present at the analog inputs of the device help isolate the external drive source from the switching currents of the sampling circuit.
For optimum performance, the analog inputs must be driven differentially. This architecture improves common-mode noise immunity and even-order harmonic rejection. A small resistor (5 Ω to 10 Ω) in series with each input pin is recommended to damp out ringing caused by package parasitics, as shown in Figure 136.
|SNR = 71 dBFS, SINAD = 70.9 dBFS,
SFDR = 85 dBc, THD = 84 dBc, IL spur = 87 dBc,
non HD2, HD3 spur = 93 dBc
|SNR = 70.4 dBFS, SINAD = 69.9 dBFS,
IL spur = 89 dBc, SFDR = 80 dBc, THD = 79 dBc,
non HD2, HD3 spur = 91 dBc