SBAS756A February   2016  – March 2016 ADS54J42


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  AC Characteristics
    7. 7.7  Digital Characteristics
    8. 7.8  Timing Characteristics
    9. 7.9  Typical Characteristics
    10. 7.10 Typical Characteristics: Contour
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog Inputs
      2. 8.3.2 DDC Block
        1. Decimate-by-2 Filter
        2. Decimate-by-4 Filter Using a Digital Mixer
        3. Decimate-by-4 Filter with IQ Outputs
      3. 8.3.3 SYSREF Signal
      4. 8.3.4 Overrange Indication
        1. Fast OVR
      5. 8.3.5 Power-Down Mode
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device Configuration
        1. Serial Interface
        2. Serial Register Write: Analog Bank
        3. Serial Register Readout: Analog Bank
        4. JESD Bank SPI Page Selection
        5. Serial Register Write: JESD Bank
          1. Individual Channel Programming
        6. Serial Register Readout: JESD Bank
      2. 8.4.2 JESD204B Interface
        1. JESD204B Initial Lane Alignment (ILA)
        2. JESD204B Test Patterns
        3. JESD204B Frame
        4. JESD204B Frame
        5. JESD204B Frame Assembly with Decimation
          1. JESD Transmitter Interface
          2. Eye Diagrams
    5. 8.5 Register Maps
      1. 8.5.1 Detailed Register Info
      2. 8.5.2 Example Register Writes
      3. 8.5.3 Register Descriptions
        1. General Registers
          1. Register 0h (address = 0h)
          2. Register 3h (address = 3h)
          3. Register 4h (address = 4h)
          4. Register 5h (address = 5h)
          5. Register 11h (address = 11h)
        2. Master Page (080h) Registers
          1.  Register 20h (address = 20h), Master Page (080h)
          2.  Register 21h (address = 21h), Master Page (080h)
          3.  Register 23h (address = 23h), Master Page (080h)
          4.  Register 24h (address = 24h), Master Page (080h)
          5.  Register 26h (address = 26h), Master Page (080h)
          6.  Register 39h (address = 39h), Master Page (080h)
          7.  Register 3Ah (address = 3Ah), Master Page (080h)
          8.  Register 4Fh (address = 4Fh), Master Page (080h)
          9.  Register 53h (address = 53h), Master Page (080h)
          10. Register 55h (address = 55h), Master Page (080h)
          11. Register 56h (address = 56h), Master Page (080h)
          12. Register 59h (address = 59h), Master Page (080h)
        3. ADC Page (0Fh) Register
          1. Register 5F (addresses = 5F), ADC Page (0Fh)
        4. Main Digital Page (6800h) Registers
          1.  Register 0h (address = 0h), Main Digital Page (6800h)
          2.  Register 41h (address = 41h), Main Digital Page (6800h)
          3.  Register 42h (address = 42h), Main Digital Page (6800h)
          4.  Register 43h (address = 43h), Main Digital Page (6800h)
          5.  Register 44h (address = 44h), Main Digital Page (6800h)
          6.  Register 4Bh (address = 4Bh), Main Digital Page (6800h)
          7.  Register 4Dh (address = 4Dh), Main Digital Page (6800h)
          8.  Register 4Eh (address = 4Eh), Main Digital Page (6800h)
          9.  Register 52h (address = 52h), Main Digital Page (6800h)
          10. Register 72h (address = 72h), Main Digital Page (6800h)
          11. Register ABh (address = ABh), Main Digital Page (6800h)
          12. Register ADh (address = ADh), Main Digital Page (6800h)
          13. Register F7h (address = F7h), Main Digital Page (6800h)
        5. JESD Digital Page (6900h) Registers
          1.  Register 0h (address = 0h), JESD Digital Page (6900h)
          2.  Register 1h (address = 1h), JESD Digital Page (6900h)
          3.  Register 2h (address = 2h), JESD Digital Page (6900h)
          4.  Register 3h (address = 3h), JESD Digital Page (6900h)
          5.  Register 5h (address = 5h), JESD Digital Page (6900h)
          6.  Register 6h (address = 6h), JESD Digital Page (6900h)
          7.  Register 7h (address = 7h), JESD Digital Page (6900h)
          8.  Register 16h (address = 16h), JESD Digital Page (6900h)
          9.  Register 31h (address = 31h), JESD Digital Page (6900h)
          10. Register 32h (address = 32h), JESD Digital Page (6900h)
        6. JESD Analog Page (6A00h) Registers
          1. Registers 12h-5h (addresses = 12h-5h), JESD Analog Page (6A00h)
          2. Register 16h (address = 16h), JESD Analog Page (6A00h)
          3. Register 17h (address = 17h), JESD Analog Page (6A00h)
          4. Register 1Ah (address = 1Ah), JESD Analog Page (6A00h)
          5. Register 1Bh (address = 1Bh), JESD Analog Page (6A00h)
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Start-Up Sequence
      2. 9.1.2 Hardware Reset
      3. 9.1.3 SNR and Clock Jitter
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. Transformer-Coupled Circuits
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9 Application and Implementation


Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

9.1 Application Information

9.1.1 Start-Up Sequence

The steps described in Table 66 are recommended as the power-up sequence with the ADS54J42 in 20X mode (LMFS = 8224).

Table 66. Initialization Sequence

1 Power-up the device Bring up the supplies to IOVDD = 1.15 V, DVDD = AVDD = 1.9 V, and AVDD3V = 3.0 V. These supplies can be brought up in any order.
2 Reset the device Hardware reset
Apply a hardware reset by pulsing pin 48 (low → high → low). A hardware reset clears all registers to their default values.
Register writes are equivalent to a hardware reset.
Write address 0-000h with 81h. General register Reset registers in the ADC and master pages of the analog bank.
This bit is a self-clearing bit.
Write address 4-001h with 00h and address 4-002h with 00h. Unused page Clear any unwanted content from the unused pages of the JESD bank.
Write address 4-003h with 00h and address 4-004h with 68h. Select the main digital page of the JESD bank.
Write address 6-0F7h with 01h for channel A. Main digital page
(JESD bank)
Use the DIG RESET register bit to reset all pages in the JESD bank.
This bit is a self-clearing bit.
Write address 6-000h with 01h, then address 6-000h with 00h. Pulse the PULSE RESET register bit for channel A.
3 Performance modes Write address 0-011h with 80h. Select the master page of the analog bank.
Write address 0-059h with 20h. Master page
(analog bank)
Set the ALWAYS WRITE 1 bit.
Write address 0-039h with C0h.
Write address 0-03Ah with 40h.
Write address 0-056h with 04h.
Set these register bits for better SFDR when input frequency > 400 MHz.
4 Program desired registers for
decimation options and
JESD link configuration
Default register writes for DDC modes and JESD link configuration (LMFS 8224).
Write address 4-003h with 00h and address 4-004h with 69h. Select the JESD digital page.
Write address 6-000h with 80h. JESD
digital page
(JESD bank)
Set the CTRL K bit for both channels by programming K according to the SYSREF signal later on in the sequence.
JESD link is configured with LMFS = 8224 by default with no decimation. See Table 13 for configuring the JESD digital page registers for the desired LMFS and programming appropriate DDC mode.
Write address 4-003h with 00h and address 4-004h with 6Ah. Select the JESD analog page.
JESD link is configured with LMFS = 8224 by default with no decimation. JESD
analog page
(JESD bank)
See Table 13 for configuring the JESD analog page registers for the desired LMFS and programming appropriate DDC mode.
Write address 6-017h with 40h. PLL reset.
Write address 6-017h with 00h. PLL reset.
Write address 4-003h with 00h and address 4-004h with 68h. Select the main digital page.
JESD link is configured with LMFS = 8224 by default with no decimation. Main digital page
(JESD bank)
See Table 13 for configuring the main digital page registers for the desired LMFS and programming appropriate DDC mode.
Write address 6-000h with 01h and address 6-000h with 00h. Pulse the PULSE RESET register bit. All settings programmed in the main digital page take effect only after this bit is pulsed.
5 Set the value of K and the SYSREF signal frequency accordingly Write address 4-003h with 00h and address 4-004h with 69h. Select the JESD digital page.
Write address 6-006h with XXh (choose the value of K). JESD
digital page
(JESD bank)
See the SYSREF Signal section to choose the correct frequency for SYSREF.
6 JESD lane alignment Pull the SYNCB pin (pin 63) low. Transmit K28.5 characters.
Pull the SYNCB pin high. After the receiver is synchronized, initiate an ILA phase and subsequent transmissions of ADC data.

9.1.2 Hardware Reset

Figure 131 and Table 67 show the timing for a hardware reset.

ADS54J42 hardware_reset_tmng_dgm_sbas706.gif Figure 131. Hardware Reset Timing Diagram

Table 67. Timing Requirements for Figure 131

t1 Power-on delay: delay from power-up to an active high RESET pulse 1 ms
t2 Reset pulse duration: active high RESET pulse duration 10 ns
t3 Register write delay from RESET disable to SEN active 100 ns

9.1.3 SNR and Clock Jitter

The signal-to-noise ratio (SNR) of the ADC is limited by three different factors: quantization noise, thermal noise, and jitter, as shown in Equation 4. The quantization noise is typically not noticeable in pipeline converters and is 86 dBFS for a 14-bit ADC. The thermal noise limits SNR at low input frequencies and the clock jitter sets SNR for higher input frequencies.

Equation 4. ADS54J42 sgnl_to_noise_ratio_eq_sbas706.png

The SNR limitation resulting from sample clock jitter can be calculated by Equation 5:

Equation 5. ADS54J42 snr_limitation_eq_sbas706.png

The total clock jitter (TJitter) has two components: the internal aperture jitter (130 fs) is set by the noise of the clock input buffer and the external clock jitter. TJitter can be calculated by Equation 6:

Equation 6. ADS54J42 total_jitter_eq_sbas706.png

External clock jitter can be minimized by using high-quality clock sources and jitter cleaners as well as band-pass filters at the clock input. A faster clock slew rate also improves the ADC aperture jitter.

The ADS54J42 has a thermal noise of approximately 71.1 dBFS and an internal aperture jitter of 120 fS. SNR, depending on the amount of external jitter for different input frequencies, is shown in Figure 132.

ADS54J42 D052_SBAS756.gif
Figure 132. SNR versus Input Frequency and External Clock Jitter

9.2 Typical Application

The ADS54J42 is designed for wideband receiver applications demanding excellent dynamic range over a large input frequency range. A typical schematic for an ac-coupled receiver is shown in Figure 133.

ADS54J42 ac_cpld_rcvr_sbas706.gif


GND = AGND and DGND are connected in the PCB layout.
Figure 133. AC-Coupled Receiver

9.2.1 Design Requirements Transformer-Coupled Circuits

Typical applications involving transformer-coupled circuits are discussed in this section. Transformers (such as ADT1-1WT or WBC1-1) can be used up to 300 MHz to achieve good phase and amplitude balances at the ADC inputs. When designing dc-driving circuits, the ADC input impedance must be considered. Figure 134 and Figure 135 show the impedance (ZIN = RIN || CIN) across the ADC input pins.

ADS54J42 D103_SBAS685.gif
Figure 134. RIN vs Input Frequency
ADS54J42 D102_SBAS685.gif
Figure 135. CIN vs Input Frequency

By using the simple drive circuit of Figure 136, uniform performance can be obtained over a wide frequency range. The buffers present at the analog inputs of the device help isolate the external drive source from the switching currents of the sampling circuit.

ADS54J42 ai_input_drive_cir_bas591.gif Figure 136. Input Drive Circuit

9.2.2 Detailed Design Procedure

For optimum performance, the analog inputs must be driven differentially. This architecture improves common-mode noise immunity and even-order harmonic rejection. A small resistor (5 Ω to 10 Ω) in series with each input pin is recommended to damp out ringing caused by package parasitics, as shown in Figure 136.

9.2.3 Application Curves

Figure 137 and Figure 138 show the typical performance at 170 MHz and 230 MHz, respectively.

ADS54J42 D003_SBAS756.gif
SNR = 71 dBFS, SINAD = 70.9 dBFS,
SFDR = 85 dBc, THD = 84 dBc, IL spur = 87 dBc,
non HD2, HD3 spur = 93 dBc
Figure 137. FFT for 170-MHz Input Signal
ADS54J42 D004_SBAS756.gif
SNR = 70.4 dBFS, SINAD = 69.9 dBFS,
IL spur = 89 dBc, SFDR = 80 dBc, THD = 79 dBc,
non HD2, HD3 spur = 91 dBc
Figure 138. FFT for 230-MHz Input Signal