SBAS745A November   2015  – December 2015 ADS54J66

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  AC Performance
    7. 6.7  Digital Characteristics
    8. 6.8  Timing Characteristics
    9. 6.9  Typical Characteristics: General (DDC Mode-8)
    10. 6.10 Typical Characteristics: Mode 2
    11. 6.11 Typical Characteristics: Mode 0
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Inputs
      2. 7.3.2 Recommended Input Circuitry
    4. 7.4 Device Functional Modes
      1. 7.4.1 Digital Features
      2. 7.4.2 Mode 0, Decimation-by-2 with IQ Outputs for up to 220 MHz of IQ Bandwidth
      3. 7.4.3 Mode 2, Decimation-by-2 for up to 110 MHz of Real Bandwidth
      4. 7.4.4 Modes 4 and 7, Decimation-by-2 with Real Outputs for up to 110 MHz of Bandwidth
      5. 7.4.5 Mode 5, Decimation-by-2 with IQ Outputs for up to 110 MHz of IQ Bandwidth
      6. 7.4.6 Mode 6, Decimation-by-4 with IQ Outputs for up to 110 MHz of IQ Bandwidth
      7. 7.4.7 Overrange Indication
      8. 7.4.8 Power-Down Mode
    5. 7.5 Programming
      1. 7.5.1 Device Configuration
        1. 7.5.1.1 Details of the Serial Interface
        2. 7.5.1.2 Serial Register Write: Analog Bank
        3. 7.5.1.3 Serial Register Readout: Analog Bank
        4. 7.5.1.4 JESD Bank SPI Page Selection
        5. 7.5.1.5 Serial Register Write: Digital Bank
        6. 7.5.1.6 Individual Channel Programming
        7. 7.5.1.7 Serial Register Readout: JESD Bank
      2. 7.5.2 JESD204B Interface
        1. 7.5.2.1 JESD204B Initial Lane Alignment (ILA)
        2. 7.5.2.2 JESD204B Frame Assembly
        3. 7.5.2.3 JESD Output Switch
          1. 7.5.2.3.1 SERDES Transmitter Interface
          2. 7.5.2.3.2 SYNCb Interface
          3. 7.5.2.3.3 Eye Diagram
    6. 7.6 Register Maps
      1. 7.6.1 Detailed Register Information
      2. 7.6.2 Example Register Writes
      3. 7.6.3 Register Descriptions
        1. 7.6.3.1 General Registers
          1. 7.6.3.1.1 Register 0h (offset = 0h) [reset = 0h]
          2. 7.6.3.1.2 Register 3h, 4h (offset = 3h, 4h) [reset = 0h]
          3. 7.6.3.1.3 Register 5h (offset = 5h) [reset = 0h]
          4. 7.6.3.1.4 Register 11h (offset = 11h) [reset = 0h]
        2. 7.6.3.2 Master Page (80h)
          1. 7.6.3.2.1  Register 20h (address = 20h) [reset = 0h], Master Page (080h)
          2. 7.6.3.2.2  Register 21h (address = 21h) [reset = 0h], Master Page (080h)
          3. 7.6.3.2.3  Register 23h (address = 23h), Master Page (080h)
          4. 7.6.3.2.4  Register 24h (address = 24h) [reset = 0h], Master Page (080h)
          5. 7.6.3.2.5  Register 26h (address = 26h), Master Page (080h)
          6. 7.6.3.2.6  Register 3Ah (address = 3Ah) [reset = 0h], Master Page (80h)
          7. 7.6.3.2.7  Register 39h (address = 39h) [reset = 0h], Master Page (80h)
          8. 7.6.3.2.8  Register 53h (address = 53h) [reset = 0h], Master Page (80h)
          9. 7.6.3.2.9  Register 55h (address = 55h) [reset = 0h], Master Page (80h)
          10. 7.6.3.2.10 Register 56h (address = 56h) [reset = 0h], Master Page (80h)
          11. 7.6.3.2.11 Register 59h (address = 59h) [reset = 0h], Master Page (80h)
        3. 7.6.3.3 ADC Page (0Fh)
          1. 7.6.3.3.1  Register 5Fh (address = 5Fh) [reset = 0h], ADC Page (0Fh)
          2. 7.6.3.3.2  Register 60h (address = 60h) [reset = 0h], ADC Page (0Fh)
          3. 7.6.3.3.3  Register 61h (address = 61h) [reset = 0h], ADC Page (0Fh)
          4. 7.6.3.3.4  Register 6Ch (address = 6Ch) [reset = 0h], ADC Page (0Fh)
          5. 7.6.3.3.5  Register 6Dh (address = 6Dh) [reset = 0h], ADC Page (0Fh)
          6. 7.6.3.3.6  Register 74h (address = 74h) [reset = 0h], ADC Page (0Fh)
          7. 7.6.3.3.7  Register 75h (address = 75h) [reset = 0h], ADC Page (0Fh)
          8. 7.6.3.3.8  Register 76h (address = 76h) [reset = 0h], ADC Page (0Fh)
          9. 7.6.3.3.9  Register 77h (address = 77h) [reset = 0h], ADC Page (0Fh)
          10. 7.6.3.3.10 Register 78h (address = 78h) [reset = 0h], ADC Page (0Fh)
        4. 7.6.3.4 Interleaving Engine Page (6100h)
          1. 7.6.3.4.1 Register 18h (address = 18h) [reset = 0h], Interleaving Engine Page (6100h)
          2. 7.6.3.4.2 Register 68h (address = 68h) [reset = 0h], Interleaving Engine Page (6100h)
        5. 7.6.3.5 Decimation Filter Page (6141h) Registers
          1. 7.6.3.5.1 Register 0h (address = 0h) [reset = 0h], Decimation Filter Page (6141h)
          2. 7.6.3.5.2 Register 1h (address = 1h) [reset = 0h], Decimation Filter Page (6141h)
          3. 7.6.3.5.3 Register 2h (address = 2h) [reset = 0h], Decimation Filter Page (6141h)
        6. 7.6.3.6 Main Digital Page (6800h) Registers
          1. 7.6.3.6.1 Register 0h (address = 0h) [reset = 0h], Main Digital Page (6800h)
          2. 7.6.3.6.2 Register 42h (address = 42h) [reset = 0h], Main Digital Page (6800h)
          3. 7.6.3.6.3 Register 4Eh (address = 4Eh) [reset = 0h], Main Digital Page (6800h)
          4. 7.6.3.6.4 Register ABh (address = ABh) [reset = 0h], Main Digital Page (6800h)
          5. 7.6.3.6.5 Register ADh (address = ADh) [reset = 0h], Main Digital Page (6800h)
          6. 7.6.3.6.6 Register F7h (address = F7h) [reset = 0h], Main Digital Page (68h)
        7. 7.6.3.7 JESD Digital Page (6900h) Registers
          1. 7.6.3.7.1  Register 0h (address = 0h) [reset = 0h], JESD Digital Page (6900h)
          2. 7.6.3.7.2  Register 1h (address = 1h) [reset = 0h], JESD Digital Page (6900h)
          3. 7.6.3.7.3  Register 2h (address = 2h) [reset = 0h], JESD Digital Page (6900h)
          4. 7.6.3.7.4  Register 3h (address = 3h) [reset = 0h], JESD Digital Page (6900h)
          5. 7.6.3.7.5  Register 5h (address = 5h) [reset = 0h], JESD Digital Page (6900h)
          6. 7.6.3.7.6  Register 6h (address = 6h) [reset = 0h], JESD Digital Page (6900h)
          7. 7.6.3.7.7  Register 19h (address = 19h) [reset = 0h], JESD Digital Page (6900h)
          8. 7.6.3.7.8  Register 1Ah (address = 1Ah) [reset = 0h], JESD Digital Page (6900h)
          9. 7.6.3.7.9  Register 1Bh (address = 1Bh) [reset = 0h], JESD Digital Page (6900h)
          10. 7.6.3.7.10 Register 1Ch (address = 1Ch) [reset = 0h], JESD Digital Page (6900h)
          11. 7.6.3.7.11 Register 1Dh (address = 1Dh) [reset = 0h], JESD Digital Page (6900h)
          12. 7.6.3.7.12 Register 1Eh (address = 1Eh) [reset = 0h], JESD Digital Page (6900h)
          13. 7.6.3.7.13 Register 1Fh (address = 1Fh) [reset = 0h], JESD Digital Page (6900h)
          14. 7.6.3.7.14 Register 20h (address = 20h) [reset = 0h], JESD Digital Page (6900h)
          15. 7.6.3.7.15 Register 21h (address = 21h) [reset = 0h], JESD Digital Page (6900h)
          16. 7.6.3.7.16 Register 22h (address = 22h) [reset = 0h], JESD Digital Page (6900h)
        8. 7.6.3.8 JESD Analog Page (6A00h) Register
          1. 7.6.3.8.1 Register 12h, 13h (address 12h, 13h) [reset = 0h], JESD Analog Page (6Ah)
          2. 7.6.3.8.2 16h (address = 16h) [reset = 0h], JESD Analog Page (6A00h)
          3. 7.6.3.8.3 Register 1Bh (address = 1Bh) [reset = 0h], JESD Analog Page (6Ah)
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Start-Up Sequence
      2. 8.1.2 Hardware Reset
        1. 8.1.2.1 Register Initialization
      3. 8.1.3 SNR and Clock Jitter
      4. 8.1.4 ADC Test Pattern
        1. 8.1.4.1 ADC Section
        2. 8.1.4.2 Transport Layer Pattern
        3. 8.1.4.3 Link Layer Pattern
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Community Resources
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Detailed Description

7.1 Overview

The ADS54J66 is a low-power, wide-bandwidth, 14-bit, 500-MSPS, quad-channel, telecom receiver device. The ADS54J66 supports the JESD204B serial interface with data rates up to 10 Gbps supporting one lane per channel. The buffered analog input provides uniform input impedance across a wide frequency range and minimizes sample-and-hold glitch energy. The ADS54J66 provides excellent spurious-free dynamic range (SFDR) over a large input frequency range with very low power consumption. The device digital block includes a 2x and 4x decimation low-pass filter with fS / 4 and k × fS / 16 mixers to support a receive bandwidth up to 200 MHz for use as a Digital Pre-Distortion (DPD) observation receiver.

The JESD204B interface reduces the number of interface lines allowing high system integration density. An internal phase locked loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock which is used to serialize the 14-bit data from each channel.

7.2 Functional Block Diagram

ADS54J66 fbd_sbas745.gif

7.3 Feature Description

7.3.1 Analog Inputs

The ADS54J66 analog signal inputs are designed to be driven differentially. The analog input pins have internal analog buffers that drive the sampling circuit. As a result of the analog buffer, the input pins present a high impedance input across a very wide frequency range to the external driving source which enables great flexibility in the external analog filter design as well as excellent 50-Ω matching for RF applications. The buffer also helps isolate the external driving circuit from the internal switching currents of the sampling circuit, thus resulting in a more constant SFDR performance across input frequencies.

The common-mode voltage of the signal inputs is internally biased to 1.9 V using 600-Ω resistors which allows for ac coupling of the input drive network. Each input pin (INP, INM) must swing symmetrically between (VCM + 0.475 V) and (VCM – 0.475 V), resulting in a 1.9-VPP (default) differential input swing. The input sampling circuit has a 3-dB bandwidth that extends up to 900 MHz.

7.3.2 Recommended Input Circuitry

In order to achieve optimum ac performance the circuitry shown in Figure 51 is recommended at the analog inputs.

ADS54J66 recomm_input_circ_bas717.gif Figure 51. Analog Input Driving Circuit

7.4 Device Functional Modes

7.4.1 Digital Features

The ADS54J66 supports decimation-by-2 and -4 and un-decimated output. The four channels can be configured as pairs (A, B and C, D; however, the same decimation factor must be chosen for all four channels).

Figure 52 shows signal processing done in the digital down-conversion (DDC) block of the ADS54J66. Table 1 shows available modes of operation for this block.

ADS54J66 sgnl_prcssng_blck_sbas745.gif Figure 52. Digital Down-Conversion Block Diagram

Table 1. Overview of Operating Modes

OPERATING
MODE
DESCRIPTION DIGITAL
MIXER
DECIMATION BANDWIDTH OUTPUT
FORMAT
MAX OUTPUT
RATE
491 MSPS 368 MSPS
0 Decimation ±fS / 4 2 200 MHz 150 MHz Complex 250 MSPS
2 2 100 MHz 75 MHz Real 250 MSPS
4 N × fS / 16 2 100 MHz 75 MHz Real 250 MSPS
5 N × fS / 16 2 200 MHz 150 MHz Complex 250 MSPS
6 N × fS / 16 4 100 MHz 75 MHz Complex 125 MSPS
7 N × fS / 16 2 100 MHz 75 MHz Real 500 MSPS
8 No decimation 245.76 MHz 184.32 MHz Real 500 MSPS

Table 2 shows characteristics of different blocks of DDC signal processing blocks active in different modes.

Table 2. Features of DDC Block in Different Modes

MODE fmix1 FILTER AND DECIMATION fmix2 OUTPUT
0 fS / 4 LPF cutoff at fS / 4, decimation-by-2 Not used I, Q data at 250 MSPS each are given out
2 Not used LPF or HPF cutoff at fS / 4, decimation-by-2 Not used Straight 250 MSPS data are given out
4 k fS / 16 LPF cutoff at fS / 8, decimation-by-2 fS / 8 Real data at 250 MSPS are given out
5 k fS / 16 LPF cutoff at fS / 8, decimation-by-2 Not used I, Q data at 250 MSPS each are given out
6 k fS / 16 LPF cutoff at fS / 8, decimation-by-4 Not used I, Q data at 125 MSPS each are given out
7 k fS / 16 LPF cutoff at fS8, decimation-by-2 fS / 8 Real data are up-scaled, zero-padded and given out at 500 MSPS
Default Not used Not used Not used Straight 500-MSPS, 14-bit data are given out

7.4.2 Mode 0, Decimation-by-2 with IQ Outputs for up to 220 MHz of IQ Bandwidth

In this configuration, the DDC block includes a fixed frequency ±fS / 4 complex digital mixer preceding the digital filter, so the IQ passband is approximately ±110 MHz (3 dB) centered at fS / 4. Mixing with +fS / 4 inverts the spectrum. The stop-band attenuation is approximately 90 dB and the pass-band flatness is ±0.1 dB. Figure 53 shows mixing operation in DDC mode 0. Table 3 shows corner frequencies of decimation filter in DDC mode 0. Figure 54 and Figure 55 show frequency response of the filter.

ADS54J66 dcc_mode_0_bas717.gif Figure 53. Mixing in Mode 0

Table 3. Filter Specification Details, Mode 0

CORNERS LOW PASS
–0.1 dB 0.204 × fS
–0.5 dB 0.211 × fS
–1 dB 0.216 × fS
–3 dB 0.226 × fS
ADS54J66 D052_SBAS717.gif Figure 54. Frequency Response of Filter in Mode 0
ADS54J66 D053_SBAS717.gif Figure 55. Zoomed View of Frequency Response

7.4.3 Mode 2, Decimation-by-2 for up to 110 MHz of Real Bandwidth

In this configuration, the DDC block only includes a 2x decimation filter (high pass or low pass) with real outputs. The pass band is approximately 110 MHz (3 dB). Figure 56 shows the filtering operation in DDC mode 2. Table 4 shows corner frequencies of decimation filter in DDC mode 2. Figure 57 and Figure 58 show frequency response of the filter.

ADS54J66 dcc_mode_2_bas717.gif Figure 56. Filtering in Mode 2

Table 4. Filter Specification Details, Mode 2

CORNERS LOW PASS HIGH PASS
–0.1 dB 0.204 × fS 0.296 × fS
–0.5 dB 0.211 × fS 0.290 × fS
–1 dB 0.216 × fS 0.284 × fS
–3 dB 0.226 × fS 0.274 × fS
ADS54J66 D056_SBAS717.gif Figure 57. Frequency Response for Decimate-by-2
Low-Pass and High-Pass Filter (in Mode 2)
ADS54J66 D057_SBAS717.gif Figure 58. Zoomed View of Frequency Response

7.4.4 Modes 4 and 7, Decimation-by-2 with Real Outputs for up to 110 MHz of Bandwidth

In this configuration, the DDC block includes a selectable N × fS / 16 complex digital mixer (N from –8 to +7) preceding the decimation-by-2 digital filter also with an IQ passband of approximately ±55 MHz (3 dB) centered at N × fS / 16. A positive value for N inverts the spectrum. In addition, a fS / 8 complex digital mixer is added after the decimation filter transforming the output back to real format and centers the output spectrum within the Nyquist zone.

In addition, the ADS54J66 supports a 0-pad feature where a sample with value = 0 is added after each sample. In this way the output data rate is interpolated to 500 MSPS (real) with a second image inverted at fS / 2 – fIN.

The stop-band attenuation is approximately 90 dB for in-band aliases from negative frequencies and approximately 55 dB for out-of-band aliases. The passband flatness is ±0.1 dB. Figure 59 shows the filtering operation in DDC mode 4 and 7. Table 5 shows corner frequencies of decimation filter in DDC mode 4 and 7. Figure 60 and Figure 61 show frequency response of the filter.

ADS54J66 dcc_mode_4_bas717.gif Figure 59. Mixing and Filtering in Modes 4 and 7

Table 5. Filter Specification Details, Modes 4 and 7

CORNERS LOW PASS
–0.1 dB 0.102 × fS
–0.5 dB 0.105 × fS
–1 dB 0.108 × fS
–3 dB 0.113 × fS
ADS54J66 D050_SBAS717.gif Figure 60. Frequency Response for Decimate-by-2,
Low-Pass Filter (in Modes 4 and 7)
ADS54J66 D051_SBAS717.gif Figure 61. Zoomed View of Frequency Response

7.4.5 Mode 5, Decimation-by-2 with IQ Outputs for up to 110 MHz of IQ Bandwidth

In this configuration, the DDC block includes a selectable N × fS / 16 complex digital mixer (N from –8 to +7) preceding the decimation-by-2 digital filter, so the IQ passband is approximately ±55 MHz (3 dB) centered at N × fS / 16. A positive value for N inverts the spectrum.

The stop-band attenuation is approximately 90 dB for in-band aliases from negative frequencies. The pass-band flatness is ±0.1 dB. Figure 62 shows the filtering operation in DDC mode 5. Table 6 shows corner frequencies of decimation filter in DDC mode 5. Figure 63 and Figure 64 show frequency response of the filter. Figure 62 shows the filtering operation in DDC mode 5. Table 6 shows corner frequencies of decimation filter in DDC mode 5. Figure 63 and Figure 64 show frequency response of the filter.

ADS54J66 dcc_mode_5_bas717.gif Figure 62. Mixing and Filtering in Mode 5

Table 6. Filter Specification Details, Mode 5

CORNERS LOW PASS
–0.1 dB 0.102 × fS
–0.5 dB 0.105 × fS
–1 dB 0.108 × fS
–3 dB 0.113 × fS
ADS54J66 D050_SBAS717.gif Figure 63. Frequency Response for Decimate-by-2,
Low-Pass Filter (In Mode 5)
ADS54J66 D051_SBAS717.gif Figure 64. Zoomed View of Frequency Response

7.4.6 Mode 6, Decimation-by-4 with IQ Outputs for up to 110 MHz of IQ Bandwidth

In this configuration, the DDC block includes a selectable N × fS / 16 complex digital mixer (n from –8 to +7) preceding the decimation-by-4 digital filter, so the IQ passband is approximately ±55 MHz (3 dB) centered at N × fS / 16. A positive value for N inverts the spectrum. Figure 65 shows the filtering operation in DDC mode 6. Table 7 shows corner frequencies of decimation filter in DDC mode 6. The decimation-by-4 filter is a cascade of two decimation-by-2 filters with frequency response shown in Figure 66 and Figure 67.

The stop-band attenuation is approximately 90 dB for in-band aliases from negative frequencies and approximately 55 dB for out-of-band aliases. The pass-band flatness is ±0.1 dB.

ADS54J66 dcc_mode_6_bas717.gif Figure 65. Mixing and Filtering in Mode 6

Table 7. Filter Specification Details, Mode 6

CORNERS LOW PASS
–0.1 dB 0.102 × fS
–0.5 dB 0.105 × fS
–1 dB 0.108 × fS
–3 dB 0.113 × fS
ADS54J66 D050_SBAS717.gif Figure 66. Frequency Response for Decimate-by-2,
Low-Pass Filter (in Mode 6)
ADS54J66 D051_SBAS717.gif Figure 67. Zoomed View of Frequency Response

7.4.7 Overrange Indication

The ADS54J66 provides a fast overrange indication (FOVR) that can be presented in the digital output data stream via SPI configuration. When the FOVR indication is embedded in the output data stream, it replaces the LSB (normal 0) of the 16 bit going to the 8b/10b encoder as shown in Figure 68.

One threshold is set per channel pair A, B and C, D.

ADS54J66 over-range_indic_bas717.gif Figure 68. Timing Diagram for FOVR

The fast OVR is triggered if the input voltage exceeds the programmable overrange threshold and it gets presented after just 44 input clock cycles enabling a quicker reaction to an overrange event.

The input voltage level at which the overload is detected is referred to as the threshold. It is programmable using the FOVR THRESHOLD bits.

The input voltage level that fast OVR is triggered is:
Full-scale × [the decimal value of the FOVR threshold bits] / 255)
The default threshold is E3h (227), corresponding to a threshold of –1 dBFS.

In terms of full-scale input, the fast OVR threshold can be calculated as shown in Equation 1:

Equation 1. 20 × log (<FOVR Threshold> / 255).

Table 8 is an example register write to set the FOVR threshold for all four channels.

Table 8. Register Sequence for FOVR Configuration

ADDRESS DATA COMMENT
11h 80h Go to master page
59h 20h Set the ALWAYS WRITE 1 bit. This bit configures the OVR signal as fast OVR.
11h FFh Go to ADC page
5Fh FFh Set FOVR threshold for all channels to 255
4004h 68h Go to main digital page of the JESD bank
4003h 00h
60ABh 01h Enable bit D0 overwrite
70ABh 01h
60ADh 03h Select FOVR to replace bit D0
70ADh 03h
6000h 01h Pulse the IL RESET register bit. Register writes in main digital page take effect when the IL RESET register bit is pulsed.
7000h 01h
6000h 00h
7000h 00h

7.4.8 Power-Down Mode

The ADS54J66 provides a highly-configurable power-down mode. Power-down can be enabled using the PDN pin or SPI register writes.

A power-down mask can be configured that allows a trade-off between wake-up time and power consumption in power-down mode. Two independent power-down masks can be configured: MASK 1 and MASK 2, as shown in Table 9. See the master page registers in Table 15 for further details.

Table 9. Register Address for Power-Down Modes

REGISTER ADDRESS
A[7:0] (Hex)
COMMENT REGISTER DATA
7 6 5 4 3 2 1 0
MASTER PAGE (80h)
20 MASK 1 PDN ADC CHAB PDN ADC CHCD
21 PDN BUFFER CHCD PDN BUFFER CHAB 0 0 0 0
23 MASK 2 PDN ADC CHAB PDN ADC CHCD
24 PDN BUFFER CHCD PDN BUFFER CHAB 0 0 0 0
26 CONFIG GLOBAL PDN OVERRIDE PDN PIN PDN MASK SEL 0 0 0 0 0
53 0 MASK SYSREF 0 0 0 0 0 0
55 0 0 0 PDN MASK 0 0 0 0

To save power, the device can be put in complete power down by using the GLOBAL PDN register bit. However, when JESD link must remain up when putting the device in power down, the ADC and analog buffer can be powered down by using the PDN ADC CHx and PDN BUFFER CHx register bits after enabling the PDN MASK register bit. The PDN MASK SEL register bit can be used to select between MASK 1 or MASK 2. Table 10 shows power consumption for different combinations of the GLOBAL PDN, PDN ADC CHx, and PDN BUFF CHx register bits.

Table 10. Power Consumption in Different Power-Down Settings

REGISTER BIT COMMENT IAVDD3V (mA) IAVDD (mA) IDVDD (mA) IIOVDD (mA) TOTAL POWER (W)
Default After reset, with a full-scale input signal to both channels 0.340 0.365 0.184 0.533 2.675
GBL PDN = 1 The device is in complete power-down state 0.002 0.006 0.012 0.181 0.247
GBL PDN = 0,
PDN ADC CHx = 1
(x = AB or CD)
The ADCs of one pair of channels are powered down 0.277 0.225 0.123 0.496 2.063
GBL PDN = 0,
PDN BUFF CHx = 1
(x = AB or CD)
The input buffers of one pair of channels are powered down 0.266 0.361 0.187 0.527 2.445
GBL PDN = 0,
PDN ADC CHx = 1, PDN BUFF CHx = 1
(x = AB or CD)
The ADCs and input buffers of one pair of channels are powered down 0.200 0.224 0.126 0.492 1.830
GBL PDN = 0,
PDN ADC CHx = 1, PDN BUFF CHx = 1
(x = AB and CD)
The ADCs and input buffers of all channels are powered down 0.060 0.080 0.060 0.448 0.960

7.5 Programming

7.5.1 Device Configuration

The ADS54J66 can be configured using a serial programming interface, as described in this section. In addition, the device has one dedicated parallel pin (PDN) for controlling the power-down modes. The ADS54J66 supports a 24-bit (16-bit address, 8-bit data) SPI operation and uses paging (see the Detailed Register Information section) to access all register bits. Figure 69 shows timing diagram for serial interface signals. SPI registers are grouped in two banks with each bank containing different pages (see Figure 84).

First 4 MSBs of 16-bit address are special bits carrying information about register bank, page and channel to be programmed. Table 11 lists the purpose of each special bit.

ADS54J66 spi_tmng_dgm_sbas706.gif Figure 69. Serial Interface Timing Diagram

Table 11. Programing Details of Serial Interface

SPI BITS DESCRIPTION OPTIONS
R/W Read/write bit 0 = SPI write
1 = SPI read back
M SPI bank access 0 = Analog SPI bank (master and ADC page)
1 = Digital SPI bank (main digital, analog JESD, and digital JESD pages)
P JESD page selection bit 0 = Page access
1 = Register access
CH SPI access for a specific channel of the digital SPI bank 0 = Channel AB
1 = Channel CD
By default, both channels are being addressed.
ADDR [11:0] SPI address bits
DATA [7:0] SPI data bits

7.5.1.1 Details of the Serial Interface

The ADC has a set of internal registers that can be accessed by the serial interface formed by the SEN (serial interface enable), SCLK (serial interface clock) and SDIN (serial interface data) pins. Serially shifting bits into the device is enabled when SEN is low. Serial data on SDIN are latched at every SCLK rising edge when SEN is active (low). The interface can function with SCLK frequencies from 5 MHz down to very low speeds (of a few hertz) and also with a non-50% SCLK duty cycle.

Figure 74 shows timing requirements for serial interface signals.

Table 12. Serial Interface Timing Requirements(1)

MIN MAX UNIT
fSCLK SCLK frequency (equal to 1 / tSCLK) > dc 20 MHz
tSLOADS SEN to SCLK setup time 25 ns
tSLOADH SCLK to SEN hold time 25 ns
tDSU SDATA setup time 25 ns
tDH SDATA hold time 25 ns
(1) Typical values are at 25°C. Minimum and maximum values are across the full temperature range of TMIN = –40°C to TMAX = 100°C, AVDD3V = 3 V, AVDD = 1.9 V, and DRVDD = 1.8 V, unless otherwise noted.

7.5.1.2 Serial Register Write: Analog Bank

The analog SPI bank contains of two pages (the master and ADC page). The internal register of the ADS54J66 analog SPI bank can be programmed by:

  1. Drive the SEN pin low.
  2. Initiate a serial interface cycle specifying the page address of the register whose content must be written.
    • Master page: write address 0011h with 80h.
    • ADC page: write address 0011h with 0Fh.
  3. Write the register content as shown in Figure 70. When a page is selected, multiple writes into the same page can be done.

ADS54J66 srl_rgstr_write_tmng_dgm_sbas706.gif Figure 70. Serial Register Write Timing Diagram

7.5.1.3 Serial Register Readout: Analog Bank

The content from one of the two analog banks can be read out by:

  1. Drive the SEN pin low.
  2. Select the page address of the register whose content must be read.
    • Master page: write address 0011h with 80h.
    • ADC page: write address 0011h with 0Fh.
  3. Set the R/W bit to 1 and write the address to be read back.
  4. Read back the register content on the SDOUT pin, as shown in Figure 71. When a page is selected, multiple read backs from the same page can be done.

ADS54J66 srl_rgstr_read_tmng_dgm_sbas706.gif Figure 71. Serial Register Read Timing Diagram

7.5.1.4 JESD Bank SPI Page Selection

The JESD SPI bank contains five pages (main digital, interleaving engine, decimation filter, JESD digital, and JESD analog). The individual pages can be selected following these steps:

  1. Drive the SEN pin low.
  2. Set the M bit to 1 and specify the page with two register writes (Note: the P bit is set to 0)
    • Write address 4003h with 00h (LSB byte of the page address)
    • Write address 4004h MSB byte of the page address
    • spacer

    • Main digital page: write address = 4004h with 68h (default)
    • Digital JESD page: write address = 4004h with 69h
    • Analog JESD page: write address = 4004h with 6Ah
    • Interleaving engine page: write address = 4004h with 61h
    • Decimation filter page: write address = 4004h with 61h and 4003h with 41h

Figure 72 shows the serial interface signals when pages in the JESD bank are being accessed. Note that the P bit is set to 0.

ADS54J66 digital_bank_spi_page_bas717.gif Figure 72. SPI Timing Diagram for Accessing a Page in the JESD Bank

7.5.1.5 Serial Register Write: Digital Bank

The ADS54J66 is a quad-channel device and the JESD204B portion is configured individually for two channels (A, B and C, D) using the CH bit. Note that the P bit must be set to 1 for register writes.

  1. Drive the SEN pin low.
  2. Select the JESD bank page (Note: M bit = 1, P bit = 0)
    • Write address 4003h with 00h
    • Main digital page: write address = 4004h with 68h (default)
    • Digital JESD page: write address = 4004h with 69h
    • Analog JESD page: write address = 4004h with 6Ah
    • Interleaving Engine page: write address = 4004h with 61h
    • Decimation Filter page: write address = 4004h with 61h and 4003h with 41h
  3. Set the M and P bit to 1 and select channels A, B (CH = 0) or C, D (CH = 1) and write the register content. When a page is selected, multiple writes into the same page can be done.
    By default, register writes are applied to both channel pairs (broadcast mode). To disable broadcast mode and enable individual channel writes, write address 4005h with 01h (default is 00h).

Figure 73 shows the serial interface signals when a register in the desired page of the JESD bank is programmed (note that the P bit must be set to 1 in this step).

ADS54J66 serial_reg_write_dig_bank_bas717.gif Figure 73. SPI Timing Diagram for Writing a Register in the JESD Bank (After Page is Accessed)

7.5.1.6 Individual Channel Programming

By default, register writes are applied to both channels in a group (for example, the register writes are applied to channels A and B if the CH bit is 0, or the register writes are applied to channels C and D if the CH bit is 1). This form of programming is referred to as broadcast mode.

For pages located in the JESD bank, the device gives flexibility to program each channel individually. To enable individual channel writes, write address 4005h with 01h (default is 00h).

7.5.1.7 Serial Register Readout: JESD Bank

SPI read out of content in one of the three digital banks can be accomplished with the following steps:

  1. Drive the SEN pin low.
  2. Select the digital bank page (Note: M bit = 1, P bit = 0)
    • Write address 4003h with 00h
    • Main digital page: write address = 4004h with 68h
    • Digital JESD page: write address = 4004h with 69h
    • Analog JESD page: write address = 4004h with 6Ah
    • Interleaving engine page: write address = 4004h with 61h
    • Decimation filter page: write address = 4004h with 61h and 4003h with 41h
  3. Set the R/W bit, M and P bit to 1 and select channels A, B or C, D and write the address to be read back.
  4. Read back register content on the SDOUT pin. When a page is selected, multiple read backs from the same page can be done.

Figure 74 shows the serial interface signals when the contents of a register in the desired page of the JESD bank are being read-back (note that the P bit must be set to 1 in this step).

ADS54J66 serial_reg_readout_dig_bank_bas717.gif Figure 74. Serial Register Read Timing Diagram

7.5.2 JESD204B Interface

The ADS54J66 supports device subclass 1 with a maximum output data rate of 10 Gbps for each serial transmitter. Figure 75 shows JESD20B block inside ADS54J66.

An external SYSREF signal is used to align all internal clock phases and the local multi frame clock to a specific sampling clock edge. This process allows synchronization of multiple devices in a system and minimizes timing and alignment uncertainty. The ADS54J66 supports single (for all four JESD links) or dual (for channel A, B and C, D) SYNCb inputs and can be configured via SPI as shown in Figure 76.

ADS54J66 jesd204b_bd_bas717.gif Figure 75. JESD Interface Block Diagram
ADS54J66 JESD_trsmttr_blk_sbas717.gif Figure 76. JESD204B Transmitter Block

Depending on the ADC sampling rate, the JESD204B output interface can be operated with one lane per channel. The JESD204B setup and configuration of the frame assembly parameters is handled via SPI interface.

The JESD204B transmitter block consists of the transport layer, the data scrambler and the link layer. The transport layer maps the ADC output data into the selected JESD204B frame data format and manages if the ADC output data or test patterns are being transmitted. The link layer performs the 8b/10b data encoding as well as the synchronization and initial lane alignment using the SYNC input signal. Optionally data from the transport layer can be scrambled.

7.5.2.1 JESD204B Initial Lane Alignment (ILA)

The initial lane alignment process is started by the receiving device by de-asserting the SYNCb signal. Upon detecting a logic low on the SYNC input pins, the ADS54J66 starts transmitting comma (K28.5) characters to establish code group synchronization as shown in Figure 77.

When synchronization is completed the receiving device re-asserts the SYNCb signal and the ADS54J66 starts the initial lane alignment sequence with the next local multi frame clock boundary. The ADS54J66 transmits four multi-frames each containing K frames (K is SPI programmable). Each of the multi-frames contains the frame start and end symbols and the second multi-frame also contains the JESD204 link configuration data.

ADS54J66 jesd204b_initial_lane_align_bas717.gif Figure 77. ILA Sequence

7.5.2.2 JESD204B Frame Assembly

The JESD204B standard defines the following parameters:

  • L is the number of lanes per link.
  • M is the number of converters per device.
  • F is the number of octets per frame clock period.
  • S is the number of samples per frame.

Table 13 lists the available JESD204B formats and valid ranges for the ADS54J66. The ranges are limited by the Serdes line rate and the maximum ADC sample frequency.

Table 13. Available JESD204B Formats and Valid Ranges for the ADS54J66

L M F S OPERATING MODE DIGITAL MODE OUTPUT FORMAT JESD MODE(1) JESD PLL MODE(2) MAX ADC OUTPUT
RATE (MSPS)
MAX fSERDES
(Gbps)
4 8 4 1 0,5 2x decimation Complex 40x 40x 250 10.0
4 4 2 1 2,4 2x decimation Real 20x 20x 250 5.0
2 4 4 1 2,4 2x decimation Real 40x 40x 250 10.0
4 8 4 1 6 4x decimation Complex 40x 20x 125 5.0
2 8 8 1 6 4x decimation Complex 80x 40x 125 10.0
4 4 2 1 7 2x decimation with 0-pad Real 20x 40x 500 10.0
4 4 2 1 8 No decimation Real 20x 40x 500 10.0
(1) In register 01h of the JESD digital page.
(2) In register 16h of the JESD analog page.

The detailed frame assembly is shown in Table 14.

Table 14. Detailed Frame Assembly

LMFS = 4841 LMFS = 4421 LMFS = 4421 (0-Pad)
DA AI0[15:8] AI0[7:0] AQ0[15:8] AQ0[7:0] A0[15:8] A0[7:0] A1[15:8] A1[7:0] A0[15:8] A0[7:0] 0000 0000 0000 0000
DB BI0[15:8] BI0[7:0] BQ0[15:8] BQ0[7:0] B0[15:8] B0[7:0] B1[15:8] B1[7:0] B0[15:8] B0[7:0] 0000 0000 0000 0000
DC CI0[15:8] CI0[7:0] CQ0[15:8] CQ0[7:0] C0[15:8] C0[7:0] C1[15:8] C1[7:0] C0[15:8] C0[7:0] 0000 0000 0000 0000
DD DI0[15:8] DI0[7:0] DQ0[15:8] DQ0[7:0] D0[15:8] D0[7:0] D1[15:8] D1[7:0] D0[15:8] D0[7:0] 0000 0000 0000 0000
LMFS = 2441 LMFS = 2881
DB A0[15:8] A0[7:0] B0[15:8] B0[7:0] AI0[15:8] AI0[7:0] AQ0[15:8] AQ0[7:0] BI0[15:8] BI0[7:0] BQ0[15:8] BQ0[7:0]
DC C0[15:8] C0[7:0] D0[15:8] D0[7:0] CI0[15:8] CI0[7:0] CQ0[15:8] CQ0[7:0] DI0[15:8] DI0[7:0] DQ0[15:8] DQ0[7:0]

7.5.2.3 JESD Output Switch

The ADS54J66 provides a digital cross point switch in the JESD204B block which allows internal routing of any output of the two ADCs within one channel pair to any of the two JESD204B serial transmitters in order to ease layout constraints. The cross-point switch routing is configured via SPI (address 21h in the JESD digital page, as shown in Figure 78).

ADS54J66 jesd_output_switch_bes717.gif Figure 78. Switching the Output Lanes

7.5.2.3.1 SERDES Transmitter Interface

Each of the 10 Gbps serdes transmitter outputs requires ac coupling between transmitter and receiver. The differential pair must be terminated with 100 Ω as close to the receiving device as possible to avoid unwanted reflections and signal degradation as shown in Figure 79.

ADS54J66 cml_serdes_trans_interf_bas717.gif Figure 79. SERDES Transmitter Connection to Receiver

7.5.2.3.2 SYNCb Interface

The ADS54J66 supports single (either SYNCb input controls all four JESD204B links) or dual (one SYNCb input controls two JESD204B lanes (DA, DB and DC, DD) SYNCb control. When using single SYNCb control, connect the unused input to differential logic low (SYNCbxxP = 0 V, SYNCbxxM = IOVDD).

7.5.2.3.3 Eye Diagram

Figure 80 to Figure 83 show the serial output eye diagrams of the ADS54J66 at 5 Gbps and 10 Gbps with default and increased output voltage swing against the JESD204B mask.

ADS54J66 eye_dgm1_sbas706.png Figure 80. Eye at 5-Gbps Bit Rate with
Default Output Swing
ADS54J66 eye_dgm3_sbas706.png Figure 82. Eye at 10-Gbps Bit Rate with
Default Output Swing
ADS54J66 eye_dgm2_sbas706.png Figure 81. Eye at 5-Gbps Bit Rate with
Increased Output Swing
ADS54J66 eye_dgm4_sbas706.png Figure 83. Eye at 10-Gbps Bit Rate with
Increased Output Swing

7.6 Register Maps

The conceptual diagram of the serial registers is shown in Figure 84.

ADS54J66 serial_intrfc_rgstrs_sbas745.gif Figure 84. Serial Interface Registers

7.6.1 Detailed Register Information

The ADS54J66 contains two main SPI banks. The analog SPI bank gives access to the ADC cores and the digital SPI bank controls the serial interface. The analog SPI bank is divided into two pages (master and ADC) and the digital SPI bank is divided into five pages (main digital, interleaving engine, decimation filter, JESD digital, and JESD analog; see Figure 84). Table 15 gives a summary of all programmable registers in the pages of different banks in the ADS54J66.

Table 15. Register Map

REGISTER ADDRESS
A[7:0] (Hex)
REGISTER DATA
7 6 5 4 3 2 1 0
GENERAL REGISTERS
0 RESET 0 0 0 0 0 0 RESET
3 JESD BANK PAGE SEL [7:0]
4 JESD BANK PAGE SEL [15:8]
5 0 0 0 0 0 0 0 DIS BROADCAST
11 ANALOG PAGE SELECTION [7:0]
MASTER PAGE (80h)
20 PDN ADC CHAB PDN ADC CHCD
21 PDN BUFFER CHCD PDN BUFFER CHAB 0 0 0 0
23 PDN ADC CHAB PDN ADC CHCD
24 PDN BUFFER CHCD PDN BUFFER CHAB 0 0 0 0
26 GLOBAL PDN OVERRIDE PDN PIN PDN MASK SEL 0 0 0 0 0
3A 0 BUFFER CURR INCREASE 0 0 0 0 0 0
39 ALWAYS WRITE 1 0 0 0 0 0 0
53 CLK DIV MASK SYSREF 0 0 0 0 0 0
55 0 0 0 PDN MASK 0 0 0 0
56 0 0 0 0 INPUT BUFF CURR EN 0 0 0
59 0 0 ALWAYS WRITE 1 0 0 0 0 0
ADC PAGE (0Fh)
5F FOVR THRESH
60 PULSE BIT CHC 0 0 0 0 0 0 0
61 0 0 0 0 HD3 NYQ2 CHCD 0 0 PULSE BIT CHD
6C PULSE BIT CHA 0 0 0 0 0 0 0
6D 0 0 0 0 HD3 NYQ2 CHAB 0 0 PULSE BIT CHB
74 TEST PATTERN ON CHANNEL 0 0 0 0
75 CUSTOM PATTERN 1 [13:6]
76 CUSTOM PATTERN 1 [5:0] 0 0
77 CUSTOM PATTERN 2 [13:6]
78 CUSTOM PATTERN 2 [5:0] 0 0
INTERLEAVING ENGINE PAGE (6100h)
18 0 0 0 0 0 0 IL BYPASS
68 0 0 0 0 0 DC CORR DIS 0
DECIMATION FILTER PAGE (6141h)
0 CHB/C FINE MIX DDC MODE
1 0 0 0 0 DDC MODE6 EN1 ALWAYS WRITE 1 CHB/C HPF EN CHB/C COARSE MIX
2 0 0 CHA/D HPF EN CHA/D COARSE MIX CHA/D FINE MIX
MAIN DIGITAL PAGE (6800h)
0 0 0 0 0 0 0 0 IL RESET
42 0 0 0 0 0 NYQUIST ZONE
4E CTRL NYQUIST ZONE 0 0 0 0 0 0 0
AB 0 0 0 0 0 0 0 OVR EN
AD 0 0 0 0 OVR ON LSB
F7 0 0 0 0 0 0 0 DIG RESET
JESD DIGITAL PAGE (6900h)
0 CTRL K JESD MODE EN DDC MODE6 EN2 TESTMODE EN 0 LANE ALIGN FRAME ALIGN TX LINK DIS
1 SYNC REG SYNC REG EN SYNCB SEL AB/CD 0 DDC MODE6 EN3 0 JESD MODE
2 LINK LAYER TESTMODE LINK LAYER RPAT LMFC MASK RESET 0 0 0
3 FORCE LMFC COUNT LMFC COUNT INIT RELEASE ILANE SEQ
5 SCRAMBLE EN 0 0 0 0 0 0 0
6 0 0 0 FRAMES PER MULTI FRAME (K)
19 0 0 0 0 LC [27:24]
1A LC [23:16]
1B LC [15:8]
1C LC [7:0]
1D 0 0 0 0 HC [27:24]
1E HC [23:16]
1F HC [15:8]
20 HC [7:0]
21 OUPUT CHA MUX SEL OUTPUT CHB MUX SEL OUTPUT CHC MUX SEL OUTPUT CHD MUX SEL
22 0 0 0 0 OUT CHA INV OUT CHB INV OUT CHC INV OUT CHD INV
JESD ANALOG PAGE (6A00h)
12 SEL EMP LANE A/D 0 0
13 SEL EMP LANE B/C 0 0
16 0 0 0 0 0 0 JESD PLL MODE
1B JESD SWING 0 0 0 0 0

7.6.2 Example Register Writes

Global power down:

ADDRESS DATA COMMENT
11h 80h Set master page
00h26 80h Set global power down

Change decimation mode 0 to mode 4 adjusting both the LMFS configuration (LMFS = 4841 to 4421) as well as serial output data rate (10 Gbps to 5 Gbps):

ADDRESS DATA COMMENT
4004h 69h Select digital JESD page
4003h 00h
6000h 40h Enables JESD mode overwrite
6001h 01h Select digital to 20x mode
4004h 6Ah Select analog JESD page
6016h 00h Set serdes PLL to 20x mode
4004h 61h Select decimation filter page
4003h 41h
6000h CCh Select mode 4
Digital mixer for channel AB set to –4 (fS / 4)
6002h 0Ch Digital mixer for channel CD set to –4 (fS / 4)

7.6.3 Register Descriptions

7.6.3.1 General Registers

7.6.3.1.1 Register 0h (offset = 0h) [reset = 0h]

Figure 85. Register 0h
7 6 5 4 3 2 1 0
RESET 0 0 0 0 0 0 RESET
R/W-0h W-0h W-0h W-0h W-0h W-0h W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 16. Register 0h Field Description

Bit Name Type Reset Description
7(1) RESET R/W 0h 0 = Normal operation
1 = Internal software reset, clears back to 0
6-0 0 W 0h Must write 0.
0(1) RESET R/W 0h 0 = Normal operation
1 = Internal software reset, clears back to 0
(1) Both bits (7, 0) must be set simultaneously to exercise reset.

7.6.3.1.2 Register 3h, 4h (offset = 3h, 4h) [reset = 0h]

Figure 86. Register 3h
7 6 5 4 3 2 1 0
JESD BANK PAGE SEL [7:0]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Figure 87. Register 4h
7 6 5 4 3 2 1 0
JESD BANK PAGE SEL [16:8]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset

Table 17. Register 3h, 4h Field Description

Bit Name Type Reset Description
7-0 JESD BANK PAGE SEL R/W 0h Program these bits to access the desired page in the JESD bank.
6100h = Interleaving engine page selected
6141h = Decimation filter page selected
6800h = Main digital page selected
6900h = JESD digital page selected
6A00h = JESD analog page selected

7.6.3.1.3 Register 5h (offset = 5h) [reset = 0h]

Figure 88. Register 5h
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 DIS BROADCAST
W-0h W-0h W-0h W-0h W-0h W-0h W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 18. Register 5h Field Description

Bit Name Type Reset Description
7-1 0 W 0h Must write 0.
0 DIS BROADCAST R/W 0h 0 = Normal operation. Channel A and B are programmed as a pair. Channel C and D are programmed as a pair.
1 = channel A and B can be individually programmed based on the CH bit. Similarly channel C and D can be individually programmed based on the CH bit.

7.6.3.1.4 Register 11h (offset = 11h) [reset = 0h]

Figure 89. Register 11h
7 6 5 4 3 2 1 0
ANALOG PAGE SELECTION [7:0]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset

Table 19. Register 11h Field Descriptions

Bit Name Type Reset Description
7-0 ANALOG PAGE SELECTION [7:0] R/W 0h Register page (only one page at a time can be addressed).
Master page = 80h
ADC page = 0Fh
The five digital pages (main digital, interleaving engine, analog JESD, digital JESD, and decimation filter) are selected via the M bit. See Table 11 in the Details of the Serial Interface section for more details.

7.6.3.2 Master Page (80h)

7.6.3.2.1 Register 20h (address = 20h) [reset = 0h], Master Page (080h)

Figure 90. Register 20h
7 6 5 4 3 2 1 0
PDN ADC CHAB PDN ADC CHCD
R/W-0h R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset

Table 20. Registers 20h Field Descriptions

Bit Field Type Reset Description
7-4 PDN ADC CHAB R/W 0h There are two power-down masks that are controlled via the PDN mask register bit in address 55h. The power-down mask 1 or mask 2 are selected via register bit 5 in address 26h.
Power-down mask 1: addresses 20h and 21h.
Power-down mask 2: addresses 23h and 24h.
See the Power-Down Mode section for details.
3-0 PDN ADC CHCD R/W 0h

7.6.3.2.2 Register 21h (address = 21h) [reset = 0h], Master Page (080h)

Figure 91. Register 21h
7 6 5 4 3 2 1 0
PDN BUFFER CHCD PDN BUFFER CHAB 0 0 0 0
R/W-0h R/W-0h W-0h R/W-0h R/W-0h W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 21. Register 21h Field Descriptions

Bit Field Type Reset Description
7-6 PDN BUFFER CHCD R/W 0h There are two power-down masks that are controlled via the PDN mask register bit in address 55h. The power-down mask 1 or mask 2 are selected via register address 26h, bit 5.
Power-down mask 1: addresses 20h and 21h.
Power-down mask 2: addresses 23h and 24h.
See the Power-Down Mode section for details.
5-4 PDN BUFFER CHAB R/W 0h
3-0 0 W 0h Must write 0.

7.6.3.2.3 Register 23h (address = 23h), Master Page (080h)

Figure 92. Register 23h
7 6 5 4 3 2 1 0
PDN ADC CHAB PDN ADC CHCD
R/W-0h W-0h R/W-0h R/W-0h W-0h
LEGEND: R/W = Read/Write; -n = value after reset

Table 22. Register 23h Field Descriptions

Bit Field Type Reset Description
7-4 PDN ADC CHAB R/W 0h There are two power-down masks that are controlled via the PDN mask register bit in address 55h. The power-down mask 1 or mask 2 are selected via register bit 5 in address 26h.
Power-down mask 1: addresses 20h and 21h.
Power-down mask 2: addresses 23h and 24h.
See the Power-Down Mode section for details.
3-0 PDN ADC CHCD R/W 0h

7.6.3.2.4 Register 24h (address = 24h) [reset = 0h], Master Page (080h)

Figure 93. Register 24h
7 6 5 4 3 2 1 0
PDN BUFFER CHCD PDN BUFFER CHAB 0 0 0 0
R/W-0h R/W-0h W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 23. Register 24h Field Descriptions

Bit Field Type Reset Description
7-6 PDN BUFFER CHCD R/W 0h There are two power-down masks that are controlled via the PDN mask register bit in address 55h. The power-down mask 1 or mask 2 are selected via register address 26h, bit 5.
Power-down mask 1: addresses 20h and 21h.
Power-down mask 2: addresses 23h and 24h.
See the Power-Down Mode section for details.
5-4 PDN BUFFER CHAB R/W 0h
3-0 0 W 0h Must write 0.

7.6.3.2.5 Register 26h (address = 26h), Master Page (080h)

Figure 94. Register 26h
7 6 5 4 3 2 1 0
GLOBAL PDN OVERRIDE PDN PIN PDN MASK SEL 0 0 0 0 0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset

Table 24. Register 26h Field Descriptions

Bit Field Type Reset Description
7 GLOBAL PDN R/W 0h Bit 6 (OVERRIDE PDN PIN) must be set before this bit can be programmed.
0 = Normal operation
1 = Global power-down via the SPI
6 OVERRIDE PDN PIN R/W 0h This bit ignores the power-down pin control.
0 = Normal operation
1 = Ignores inputs on the power-down pin
5 PDN MASK SEL R/W 0h This bit selects power-down mask 1 or mask 2.
0 = Power-down mask 1
1 = Power-down mask 2
4-0 0 R/W 0h Must write 0

7.6.3.2.6 Register 3Ah (address = 3Ah) [reset = 0h], Master Page (80h)

Figure 95. Register 3Ah
7 6 5 4 3 2 1 0
0 BUFFER CURR INCREASE 0 0 0 0 0 0
W-0h R/W-0h W-0h W-0h W-0h W-0h W-0h W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 25. Register 3Ah Field Descriptions

Bit Name Type Reset Description
7 0 W 0h Must write 0.
6 BUFFER CURR INCREASE R/W 0h 0 = Normal operation
1 = Increases AVDD3V current by 30 mA., improves HD3, helpful for second Nyquist application. Ensure that the INPUT BUF CUR EN regiser bit is also set to 1.
5-0 0 W 0h Must write 0.

7.6.3.2.7 Register 39h (address = 39h) [reset = 0h], Master Page (80h)

Figure 96. Register 39h
7 6 5 4 3 2 1 0
ALWAYS WRITE 1 0 0 0 0 0 0
R/W-0h W-0h W-0h W-0h W-0h W-0h W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 26. Register 39h Field Descriptions

Bit Name Type Reset Description
7-6 ALWAYS WRITE 1 R/W 0h Always set these bits to 11.
5-0 0 W 0h Must write 0.

7.6.3.2.8 Register 53h (address = 53h) [reset = 0h], Master Page (80h)

Figure 97. Register 53h Register
7 6 5 4 3 2 1 0
CLK DIV MASK SYSREF 0 0 0 0 0 0
R/W-0h R/W-0h W-0h W-0h W-0h W-0h W-0h W-0h
LEGEND: R/W = Read/Write; -n = value after reset

Table 27. Register 53h Field Descriptions

Bit Name Type Reset Description
7 CLK DIV R/W 0h This bit configures the input clock divider.
0 = Divide-by-4
1= Divide-by-2 (must be enabled for proper operation of the ADS54J66)
6 MASK SYSREF R/W 0h 0 = Normal operation
1 = Ignores the SYSREF input
5-0 0 W 0h Must write 0.

7.6.3.2.9 Register 55h (address = 55h) [reset = 0h], Master Page (80h)

Figure 98. Register 55h
7 6 5 4 3 2 1 0
0 0 0 PDN MASK 0 0 0 0
W-0h W-0h W-0h R/W-0h W-0h W-0h W-0h W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 28. Register 55h Field Descriptions

Bit Name Type Reset Description
7-5 0 W 0h Must write 0.
4 PDN MASK R/W 0h Power-down via register bit.
0 = Normal operation
1 = Power down enabled powering down internal blocks specified in the selected power-down mask
3-0 0 W 0h Must write 0.

7.6.3.2.10 Register 56h (address = 56h) [reset = 0h], Master Page (80h)

Figure 99. Register 56h
7 6 5 4 3 2 1 0
0 0 0 0 INPUT BUFF CURR EN 0 0 0
W-0h W-0h W-0h W-0h R/W-0h W-0h W-0h W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 29. Register 56h Field Descriptions

Bit Name Type Reset Description
7-4 0 W 0h Must write 0.
3 INPUT BUFF CURR EN R/W 0h 0 = Normal operation
1 = Increases AVDD3V current by 30 mA., improves HD3, helpful for second Nyquist application. Ensure that the BUFFER CURR INCREASE register bit is also set to 1.
2-0 0 W 0h Must write 0.

7.6.3.2.11 Register 59h (address = 59h) [reset = 0h], Master Page (80h)

Figure 100. Register 59h
7 6 5 4 3 2 1 0
0 0 ALWAYS WRITE 1 0 0 0 0 0
W-0h W-0h R/W-0h W-0h W-0h W-0h W-0h W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 30. Register 59h Field Descriptions

Bit Name Type Reset Description
7-6 0 W 0h Must write 0.
5 ALWAYS WRITE 1 R/W 0h Always set this bit to 1.
4-0 0 W 0h Must write 0.

7.6.3.3 ADC Page (0Fh)

7.6.3.3.1 Register 5Fh (address = 5Fh) [reset = 0h], ADC Page (0Fh)

Figure 101. Register 5Fh
7 6 5 4 3 2 1 0
FOVR THRESH
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset

Table 31. Register 5Fh Field Descriptions

Bit Name Type Reset Description
7-0 FOVR THRESH R/W 0h These bits control the location of FAST OVR threshold for all four channels together; see the Overrange Indication section.

7.6.3.3.2 Register 60h (address = 60h) [reset = 0h], ADC Page (0Fh)

Figure 102. Register 60h
7 6 5 4 3 2 1 0
PULSE BIT CHC 0 0 0 0 0 0 0
R/W-0h W-0h W-0h W-0h W-0h W-0h W-0h W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 32. Register 60h Field Descriptions

Bit Name Type Reset Description
7 PULSE BIT CHC R/W 0h Pulse this bit to improve HD3 for 2nd Nyquist frequencies (fIN > 250 MHz) for channel C.(1)
Before pulsing this bit, the HD3 NYQ2 CHCD register bit must be set to 1.
6-0 0 W 0h Must write 0.
(1) Pulsing = set the bit to 1 and then reset to 0.

7.6.3.3.3 Register 61h (address = 61h) [reset = 0h], ADC Page (0Fh)

Figure 103. Register 61h
7 6 5 4 3 2 1 0
0 0 0 0 HD3 NYQ2 CHCD 0 0 PULSE BIT CHD
W-0h W-0h W-0h W-0h R/W-0h W-0h W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 33. Register 61h Field Descriptions

Bit Name Type Reset Description
7-4 0 W 0h Must write 0.
3 HD3 NYQ2 CHCD R/W 0h Set this bit to improve HD3 for 2nd Nyquist frequencies (fIN > 250 MHz) for channel C and D. When this bit is set, the PULSE BIT CHx register bits must be pulsed to obtain the improvement in corresponding channels.
2-1 0 W 0h Must write 0.
0 PULSE BIT CHD R/W 0h Pulse this bit to improve HD3 for 2nd Nyquist frequencies (fIN > 250 MHz) for channel D.(1)
Before pulsing this bit, the HD3 NYQ2 CHCD register bit must be set to 1.
(1) Pulsing = set the bit to 1 and then reset to 0.

7.6.3.3.4 Register 6Ch (address = 6Ch) [reset = 0h], ADC Page (0Fh)

Figure 104. Register 6Ch
7 6 5 4 3 2 1 0
PULSE BIT CHA 0 0 0 0 0 0 0
R/W-0h W-0h W-0h W-0h W-0h W-0h W-0h W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 34. Register 6Ch Field Descriptions

Bit Name Type Reset Description
7 PULSE BIT CHA R/W 0h Pulse this bit to improve HD3 for 2nd Nyquist frequencies (fIN > 250 MHz) for channel A.(1)
Before pulsing this bit, the HD3 NYQ2 CHCAB register bit must be set to 1.
6-0 0 W 0h Must write 0.
(1) Pulsing = set the bit to 1 and then reset to 0.

7.6.3.3.5 Register 6Dh (address = 6Dh) [reset = 0h], ADC Page (0Fh)

Figure 105. Register 6Dh
7 6 5 4 3 2 1 0
0 0 0 0 HD3 NYQ2 CHAB 0 0 PULSE BIT CHB
W-0h W-0h W-0h W-0h R/W-0h W-0h W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 35. Register 6Dh Field Descriptions

Bit Name Type Reset Description
7-4 0 W 0h Must write 0.
3 HD3 NYQ2 CHAB R/W 0h Set this bit to improve HD3 for 2nd Nyquist frequencies (fIN > 250 MHz) for channel A and B. When this bit is set, the PULSE BIT CHx register bits must be pulsed to obtain the improvement in corresponding channels.
2-1 0 W 0h Must write 0.
0 PULSE BIT CHB R/W 0h Pulse this bit to improve HD3 for 2nd Nyquist frequencies (fIN > 250 MHz) for channel B.(1)
Before pulsing this bit, the HD3 NYQ2 CHAB register bit must be set to 1.
(1) Pulsing = set the bit to 1 and then reset to 0.

7.6.3.3.6 Register 74h (address = 74h) [reset = 0h], ADC Page (0Fh)

Figure 106. Register 74h
7 6 5 4 3 2 1 0
TEST PATTERN ON CHANNEL 0 0 0 0
R/W-0h W-0h W-0h W-0h W-0h
LEGEND: R/W = Read/Write; -n = value after reset

Table 36. Register 74h Field Descriptions

Bit Field Type Reset Description
7-4 TEST PATTERN ON CHANNEL R/W 0h Test pattern output on channel A and B
0000 = Normal operation using ADC output data
0001 = Outputs all 0s
0010 = Outputs all 1s
0011 = Outputs toggle pattern: Output data are an alternating sequence of 101010101010 and 010101010101
0100 = Output digital ramp: output data increment by one LSB every clock cycle from code 0 to 16384
0110 = Single pattern: output data are custom pattern 1 (75h and 76h)
0111 = Double pattern: output data alternate between custom pattern 1 and custom pattern 2
1000 = Deskew pattern: output data are 2AAAh
1001 = SYNC pattern: output data are 3FFFh
See the ADC Test Pattern section for more details.
3-0 0 W 0h Must write 0.

7.6.3.3.7 Register 75h (address = 75h) [reset = 0h], ADC Page (0Fh)

Figure 107. Register 75h
7 6 5 4 3 2 1 0
CUSTOM PATTERN 1[13:6]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset

Table 37. Register 75h Field Descriptions

Bit Name Type Reset Description
7-0 CUSTOM PATTERN R/W 0h These bits set the custom pattern (13-6) for all channels; see the ADC Test Pattern section for more details.

7.6.3.3.8 Register 76h (address = 76h) [reset = 0h], ADC Page (0Fh)

Figure 108. Register 76h
7 6 5 4 3 2 1 0
CUSTOM PATTERN 1[ 5:0] 0 0
R/W-0h W-0h W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 38. Register 76h Field Descriptions

Bit Name Type Reset Description
7-2 CUSTOM PATTERN R/W 0h These bits set the custom pattern (5-0) for all channels; see the ADC Test Pattern section for more details.
1-0 0 W 0h Must write 0.

7.6.3.3.9 Register 77h (address = 77h) [reset = 0h], ADC Page (0Fh)

Figure 109. Register 77h
7 6 5 4 3 2 1 0
CUSTOM PATTERN 2[13:6]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset

Table 39. Register 77h Field Descriptions

Bit Name Type Reset Description
7-0 CUSTOM PATTERN R/W 0h These bits set the custom pattern (13-6) for all channels; see the ADC Test Pattern section for more details.

7.6.3.3.10 Register 78h (address = 78h) [reset = 0h], ADC Page (0Fh)

Figure 110. Register 78h
7 6 5 4 3 2 1 0
CUSTOM PATTERN 2[ 5:0] 0 0
R/W-0h W-0h W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 40. Register 78h Field Descriptions

Bit Name Type Reset Description
7-2 CUSTOM PATTERN R/W 0h These bits set the custom pattern (5-0) for all channels; see the ADC Test Pattern section for more details.
1-0 0 W 0h Must write 0.

7.6.3.4 Interleaving Engine Page (6100h)

7.6.3.4.1 Register 18h (address = 18h) [reset = 0h], Interleaving Engine Page (6100h)

Figure 111. Register 18h
7 6 5 4 3 2 1 0
0 0 0 0 0 0 IL BYPASS
W-0h W-0h W-0h W-0h W-0h W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 41. Register 18h Field Descriptions

Bit Name Type Reset Description
7-2 0 W 0h Must write 0.
1-0 IL BYPASS R/W 0h These bits allow bypassing of the interleaving correction, which is to be used when ADC test patterns are enabled.
00 = Interleaving correction enabled
11 = Interleaving correction bypassed

7.6.3.4.2 Register 68h (address = 68h) [reset = 0h], Interleaving Engine Page (6100h)

Figure 112. Register 68h
7 6 5 4 3 2 1 0
0 0 0 0 0 DC CORR DIS 0
W-0h W-0h W-0h W-0h W-0h R/W-0h W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 42. Register 68h Field Descriptions

Bit Name Type Reset Description
7-3 0 W 0h Must write 0.
2-1 DC CORR DIS R/W 0h These bits enable the dc offset correction loop.
00 = DC offset correction enabled
11 = DC offset correction disabled
Others = Do not use
0 0 W 0h Must write 0.

7.6.3.5 Decimation Filter Page (6141h) Registers

7.6.3.5.1 Register 0h (address = 0h) [reset = 0h], Decimation Filter Page (6141h)

Figure 113. Register 0h
7 6 5 4 3 2 1 0
CHB/C FINE MIX DDC MODE
R/W-0h R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset

Table 43. 0h Field Descriptions

Bit Field Type Reset Description
7-4 CHB/C FINE MIX R/W 0h These bits select fine mixing frequency for the N × fS / 16 mixer, where N is a twos complement number varying from –8 to 7.
0000 = N is 0
0001 = N is 1
0010 = N is 2
...
0111 = N is 7
1000 = N is –8
...
1111 = N is –1
3-0 DDC MODE R/W 0h These bits select DDC mode for all channels; see Table 44 for bit settings.

Table 44. DDC MODE Bit Settings

SETTING MODE DESCRIPTION
000 0 fS / 4 mixing with decimation-by-2, complex output
001 N/A
010 2 Decimation-by-2, high or low pass filter, real output
011 N/A
100 4 Decimation-by-2, N × fS / 16 mixer, real output
101 5 Decimation-by-2, N × fS / 16 mixer, complex output
110 6 Decimation-by-4, N × fS / 16 mixer, complex output. Ensure that the DDC MODE 6 EN[3:1] register bits are also set to 111.
111 7 Decimation-by-2, N × fS / 16 mixer, insert 0, real output
1000 8 No decimation, no mixing, straight 500-MSPS data output
Others Do not use

7.6.3.5.2 Register 1h (address = 1h) [reset = 0h], Decimation Filter Page (6141h)

Figure 114. Register 1h
7 6 5 4 3 2 1 0
0 0 0 0 DDC MODE6 EN1 ALWAYS WRITE 1 CHB/C HPF EN CHB/C COARSE MIX
W-0h W-0h W-0h W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 45. Register 1h Field Descriptions

Bit Name Type Reset Description
7-4 0 W 0h Must write 0.
3 DDC MODE6 EN1 R/W 0h Set this bit along with the DDC MODE6 EN2 and DDC MODE6 EN3 register bits for proper operation of mode 6.
0 = Default
1 = Use for proper operation of DDC mode 6
2 ALWAYS WRITE 1 R/W 0h Always write this bit to 1.
1 CHB/C HPF EN R/W 0h This bit enables the high-pass filter for DDC mode 2 for channel B and C.
0 = Low-pass filter enabled
1 = High-pass filter enabled
0 CHB/C COARSE MIX R/W 0h This bit selects the fS / 4 mixer phase for DDC mode 0 for channel B and C.
0 = Mix with fS / 4
1 = Mix with –fS / 4

7.6.3.5.3 Register 2h (address = 2h) [reset = 0h], Decimation Filter Page (6141h)

Figure 115. Register 2h
7 6 5 4 3 2 1 0
0 0 CHA/D HPF EN CHA/D COARSE MIX CHA/D FINE MIX
W-0h W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 46. 2h Field Descriptions

Bit Name Type Reset Description
7-6 0 W 0h Must write 0.
5 CHA/D HPF EN R/W 0h This bit enables the high-pass filter for DDC mode 2 for channel A and D.
0 = Low-pass filter enabled
1 = High-pass filter enabled
4 CHA/D COARSE MIX R/W 0h This bit selects the fS / 4 mixer phase for DDC mode 0 for channel A and D.
0 = Mix with fS / 4
1 = Mix with –fS / 4
3-0 CHA/D FINE MIX R/W 0h These bits select the fine mixing frequency for the N × fS / 16 mixer, where N is a twos complement number varying from –8 to 7.
0000 = N is 0
0001 = N is 1
0010 = N is 2
...
0111 = N is 7
1000 = N is –8
...
1111 = N is –1

7.6.3.6 Main Digital Page (6800h) Registers

7.6.3.6.1 Register 0h (address = 0h) [reset = 0h], Main Digital Page (6800h)

Figure 116. Register 0h
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 IL RESET
W-0h W-0h W-0h W-0h W-0h W-0h W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 47. Register 0h Field Descriptions

Bit Name Type Reset Description
7-1 0 W 0h Must write 0.
0 IL RESET R/W 0h This bit resets the interleaving engine. This bit is not a self-clearing bit and must be pulsed(1).
Any register bit in the main digital page (6800h) takes effect only after this bit is pulsed. Also, note that pulsing this bit clears registers in the interleaving page (6100h).
0 = Normal operation
0 → 1 → 0 = Interleaving engine reset
(1) Pulsing = set the bit to 1 and then reset to 0.

7.6.3.6.2 Register 42h (address = 42h) [reset = 0h], Main Digital Page (6800h)

Figure 117. Register 42h
7 6 5 4 3 2 1 0
0 0 0 0 0 NYQUIST ZONE
W-0h W-0h W-0h W-0h W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 48. Register 42h Field Descriptions

Bit Name Type Reset Description
7-3 0 W 0h Must write 0.
2-0 NYQUIST ZONE R/W 0h These bits provide Nyquist zone information to the interleaving engine. Ensure that the CTRL NYQUIST register bit is set to 1.
000 = 1st Nyquist zone (input frequencies between 0 to fS / 2)
001 = 2nd Nyquist zone (input frequencies between fS / 2 to fS)
010 = 3rd Nyquist zone (input frequencies between fS to 3 fS / 2)
...
111 = 8th Nyquist zone (input frequencies between 7 fS / 2 to 4 fS)

7.6.3.6.3 Register 4Eh (address = 4Eh) [reset = 0h], Main Digital Page (6800h)

Figure 118. Register 4Eh
7 6 5 4 3 2 1 0
CTRL NYQUIST 0 0 0 0 0 0 0
R/W-0h W-0h W-0h W-0h W-0h W-0h W-0h W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 49. Register 4Eh Field Descriptions

Bit Name Type Reset Description
7 CTRL NYQUIST R/W 0h Enables Nyquist zone control using register bits NYQUIST ZONE.
0 = Selection disabled
1 = Selection enabled
6-0 0 W 0h Must write 0.

7.6.3.6.4 Register ABh (address = ABh) [reset = 0h], Main Digital Page (6800h)

Figure 119. Register ABh
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 OVR EN
W-0h W-0h W-0h W-0h W-0h W-0h W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 50. Register ABh Field Descriptions

Bit Field Type Reset Description
7-1 0 W 0h Must write 0.
0 OVR EN R/W 0h Set this bit to enable the OVR ON LSB register bit.
0 = Normal operation
1 = OVR ON LSB enabled

7.6.3.6.5 Register ADh (address = ADh) [reset = 0h], Main Digital Page (6800h)

Figure 120. Register ADh
7 6 5 4 3 2 1 0
0 0 0 0 OVR ON LSB
W-0h W-0h W-0h W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 51. Register ADh Field Descriptions

Bit Field Type Reset Description
7-4 0 W 0h Must write 0.
3-0 OVR EN R/W 0h Set this bit to bring OVR on two LSBs of the 16-bit output. Ensure that the OVR EN register bit is set to 1.
0000 = Bits 0 and 1 of the 16-bit data are noise bits
0011 = OVR comes on bit 0 of the 16-bit data
1100 = OVR comes on bit 1 of the 16-bit data
1111 = OVR comes on both bits 0 and 1 of the 16-bit data

7.6.3.6.6 Register F7h (address = F7h) [reset = 0h], Main Digital Page (68h)

Figure 121. Register F7h
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 DIG RESET
W-0h W-0h W-0h W-0h W-0h W-0h W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 52. Register F7h Field Descriptions

Bit Field Type Reset Description
7-1 0 W 0h Must write 0.
0 DIG RESET R/W 0h Self-clearing reset for the digital block. Does not include the interleaving correction.
0 = Normal operation
1 = Digital reset

7.6.3.7 JESD Digital Page (6900h) Registers

7.6.3.7.1 Register 0h (address = 0h) [reset = 0h], JESD Digital Page (6900h)

Figure 122. Register 0h
7 6 5 4 3 2 1 0
CTRL K JESD MODE EN DDC MODE6 EN2 TESTMODE EN 0 LANE ALIGN FRAME ALIGN TX LINK DIS
R/W-0h R/W-0h R/W-0h R/W-0h W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 53. Register 0h Field Descriptions

Bit Name Type Reset Description
7 CTRL K R/W 0h Enable bit for a number of frames per multi frame.
0 = Default is five frames per multi frame
1 = Frames per multi frame can be set in register 06h
6 JESD MODE EN R/W 0h Allows changing the JESD MODE setting in register 01h (bits 1-0)
0 = Disabled
1 = Enables changing the JESD MODE setting
5 DDC MODE6 EN2 R/W 0h Set this bit along with the DDC MODE6 EN1 and DDC MODE6 EN3 register bits for proper operation of mode 6.
0 = Default
1 = Use for proper operation of DDC mode 6
4 TESTMODE EN R/W 0h This bit generates the long transport layer test pattern mode, as per section 5.1.6.3 of the JESD204B specification.
0 = Test mode disabled
1 = Test mode enabled
3 0 W 0h Must write 0.
2 LANE ALIGN R/W 0h This bit inserts the lane alignment character (K28.3) for the receiver to align to lane boundary, as per section 5.3.3.5 of the JESD204B specification.
0 = Normal operation
1 = Inserts lane alignment characters
1 FRAME ALIGN R/W 0h This bit inserts the lane alignment character (K28.7) for the receiver to align to lane boundary, as per section 5.3.3.5 of the JESD204B specification.
0 = Normal operation
1 = Inserts frame alignment characters
0 TX LINK DIS R/W 0h This bit disables sending the initial link alignment (ILA) sequence when SYNC is de-asserted.
0 = Normal operation
1 = ILA disabled

7.6.3.7.2 Register 1h (address = 1h) [reset = 0h], JESD Digital Page (6900h)

Figure 123. Register 1h
7 6 5 4 3 2 1 0
SYNC REG SYNC REG EN SYNCB SEL AB/CD 0 DDC MODE6 EN3 0 JESD MODE
R/W-0h R/W-0h R/W-0h W-0h R/W-0h W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 54. Register 1h Field Descriptions

Bit Name Type Reset Description
7 SYNC REG R/W 0h SYNC register (bit 6 must be enabled).
0 = Normal operation
1 = ADC output data are replaced with K28.5 characters
6 SYNC REG EN R/W 0h Enables bit for SYNC operation.
0 = Normal operation
1 = ADC output data overwrite enabled
5 SYNCB SEL AB/CD R/W 0h This bit selects which SYNCb input controls the JESD interface; must be configured for ch AB and ch CD.
0 = SYNCbAB
1 = SYNCbCD
4 0 W 0h Must write 0.
3 DDC MODE6 EN3 R/W 0h Set this bit along with the DDC MODE6 EN1 and DDC MODE6 EN2 register bits for proper operation of mode 6.
0 = Default
1 = Use for proper operation of DDC mode 6
2 0 W 0h Must write 0.
1-0 JESD MODE R/W 0h These bits select the number of serial JESD output lanes per ADC. The JESD MODE EN (00h) and JESD PLL MODE register (JESD ANALOG page, register 16h) must also be set accordingly.
01 = 20x mode
10 = 40x mode
11 = 80x mode
All others = Not used

7.6.3.7.3 Register 2h (address = 2h) [reset = 0h], JESD Digital Page (6900h)

Figure 124. Register 2h
7 6 5 4 3 2 1 0
LINK LAYER TESTMODE LINK LAYER RPAT LMFC MASK RESET 0 0 0
R/W-0h R/W-0h R/W-0h W-0h W-0h W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 55. Register 2h Field Descriptions

Bit Name Type Reset Description
7-5 LINK LAYER TESTMODE R/W 0h These bits generate a pattern according to clause 5.3.3.8.2 of the JESD204B document.
000 = Normal ADC data
001 = D21.5 (high-frequency jitter pattern)
010 = K28.5 (mixed-frequency jitter pattern)
011 = Repeat initial lane alignment (generates a K28.5 character and continuously repeats lane alignment sequences)
100 = 12-octet RPAT jitter pattern
4 LINK LAYER RPAT R/W 0h This bit changes the running disparity in the modified RPAT pattern test mode (only when the link layer test mode = 100).
0 = Normal operation
1 = Changes disparity
3 LMFC MASK RESET R/W 0h 0 = Default
1 = Resets the LMFC mask
2-0 0 W 0h Must write 0.

7.6.3.7.4 Register 3h (address = 3h) [reset = 0h], JESD Digital Page (6900h)

Figure 125. Register 3h
7 6 5 4 3 2 1 0
FORCE LMFC COUNT LMFC COUNT INIT RELEASE ILANE SEQ
R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset

Table 56. Register 3h Field Descriptions

Bit Name Type Reset Description
7 FORCE LMFC COUNT R/W 0h This bit forces the LMFC count.
0 = Normal operation
1 = Enables using a different starting value for the LMFC counter
6-2 LMFC COUNT INIT R/W 0h SYSREF coming to the digital block resets the LMFC count to 0 and K28.5 stops coming when the LMFC count reaches 31. The initial value that the LMFC count resets to can be set using LMFC COUNT INIT. In this manner, Rx can be synchronized early because it receives the LANE ALIGNMENT SEQUENCE early. The FORCE LMFC COUNT register bit must be enabled.
1-0 RELEASE ILANE SEQ R/W 0h These bits delay the generation of lane alignment sequence by 0, 1, 2, or 3 multi frames after code group synchronization.
00 = 0
01 = 1
10 = 2
11 = 3

7.6.3.7.5 Register 5h (address = 5h) [reset = 0h], JESD Digital Page (6900h)

Figure 126. Register 5h
7 6 5 4 3 2 1 0
SCRAMBLE EN 0 0 0 0 0 0 0
R/W-0h W-0h W-0h W-0h W-0h W-0h W-0h W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 57. Register 5h Field Descriptions

Bit Name Type Reset Description
7 SCRAMBLE EN R/W 0h Scramble enable bit in the JESD204B interface.
0 = Scrambling disabled
1 = Scrambling enabled
6-0 0 W 0h Must write 0.

7.6.3.7.6 Register 6h (address = 6h) [reset = 0h], JESD Digital Page (6900h)

Figure 127. Register 6h
7 6 5 4 3 2 1 0
0 0 0 FRAMES PER MULTI FRAME (K)
W-0h W-0h W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 58. Register 6h Field Descriptions

Bit Name Type Reset Description
7-5 0 W 0h Must write 0.
4-0 FRAMES PER MULTI FRAME (K) R/W 0h These bits set the number of multi frames.
Actual K is the value in hex + 1 (that is, 0Fh is K = 16).

7.6.3.7.7 Register 19h (address = 19h) [reset = 0h], JESD Digital Page (6900h)

Figure 128. Register 19h
7 6 5 4 3 2 1 0
0 0 0 0 LC[27:24]
W-0h W-0h W-0h W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 59. Register 19h Field Descriptions

Bit Name Type Reset Description
7-4 0 W 0h Must write 0.
3-0 LC[27:24] R/W 0h These bits set the low resolution counter value. When programming LC[27:0], first program LC[7:0], then LC[15:8], then LC[23:16], and then LC[27:24] in the same order.

7.6.3.7.8 Register 1Ah (address = 1Ah) [reset = 0h], JESD Digital Page (6900h)

Figure 129. Register 1Ah
7 6 5 4 3 2 1 0
LC[23:16]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset

Table 60. 1Ah Field Descriptions

Bit Name Type Reset Description
7-0 LC[23:16] R/W 0h These bits set the low resolution counter value. When programming LC[27:0], first program LC[7:0], then LC[15:8], then LC[23:16], and then LC[27:24] in the same order.

7.6.3.7.9 Register 1Bh (address = 1Bh) [reset = 0h], JESD Digital Page (6900h)

Figure 130. Register 1Bh
7 6 5 4 3 2 1 0
LC[15:8]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset

Table 61. Register 1Bh Field Descriptions

Bit Name Type Reset Description
7-0 LC[15:8] R/W 0h These bits set the low resolution counter value. When programming LC[27:0], first program LC[7:0], then LC[15:8], then LC[23:16], and then LC[27:24] in the same order.

7.6.3.7.10 Register 1Ch (address = 1Ch) [reset = 0h], JESD Digital Page (6900h)

Figure 131. Register 1Ch
7 6 5 4 3 2 1 0
LC[7:0]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset

Table 62. Register 1Ch Field Descriptions

Bit Name Type Reset Description
7-0 LC[7:0] R/W 0h These bits set the low resolution counter value. When programming LC[27:0], first program LC[7:0], then LC[15:8], then LC[23:16], and then LC[27:24] in the same order.

7.6.3.7.11 Register 1Dh (address = 1Dh) [reset = 0h], JESD Digital Page (6900h)

Figure 132. Register 1Dh
7 6 5 4 3 2 1 0
0 0 0 0 HC[27:24]
W-0h W-0h W-0h W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 63. Register 1Dh Field Descriptions

Bit Name Type Reset Description
7-4 0 W 0h Must write 0.
3-0 HC [xx:xx] R/W 0h These bits set the high resolution counter value. When programming HC[27:0], first program HC[7:0], then HC[15:8], then HC[23:16], and then HC[27:24] in the same order.

7.6.3.7.12 Register 1Eh (address = 1Eh) [reset = 0h], JESD Digital Page (6900h)

Figure 133. Register 1Eh
7 6 5 4 3 2 1 0
HC[23:16]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset

Table 64. Register 1Eh Field Descriptions

Bit Name Type Reset Description
7-0 HC[23:16] R/W 0h These bits set the high resolution counter value. When programming HC[27:0], first program HC[7:0], then HC[15:8], then HC[23:16], and then HC[27:24] in the same order.

7.6.3.7.13 Register 1Fh (address = 1Fh) [reset = 0h], JESD Digital Page (6900h)

Figure 134. Register 1Fh
7 6 5 4 3 2 1 0
HC[15:8]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset

Table 65. Register 1Fh Field Descriptions

Bit Name Type Reset Description
7-0 HC[15:8] R/W 0h These bits set the high resolution counter value. When programming HC[27:0], first program HC[7:0], then HC[15:8], then HC[23:16], and then HC[27:24] in the same order.

7.6.3.7.14 Register 20h (address = 20h) [reset = 0h], JESD Digital Page (6900h)

Figure 135. Register 20h
7 6 5 4 3 2 1 0
HC[7:0]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset

Table 66. Register 20h Field Descriptions

Bit Name Type Reset Description
7-0 HC[7:0] R/W 0h These bits set the high resolution counter value. When programming HC[27:0], first program HC[7:0], then HC[15:8], then HC[23:16], and then HC[27:24] in the same order.

7.6.3.7.15 Register 21h (address = 21h) [reset = 0h], JESD Digital Page (6900h)

Figure 136. Register 21h
7 6 5 4 3 2 1 0
OUTPUT CHA MUX SEL OUTPUT CHB MUX SEL OUTPUT CHC MUX SEL OUTPUT CHD MUX SEL
R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset

Table 67. 21h Field Descriptions

Bit Name Type Reset Description
7-6 OUTPUT CHA MUX SEL R/W 0h SERDES lane swap with ch B.
00 = Ch A is output on lane DA
10 = Ch A is output on lane DB
01, 11 = Do not use
5-4 OUTPUT CHB MUX SEL R/W 0h SERDES lane swap with ch A.
00 = Ch B is output on lane DB
10 = Ch B is output on lane DA
01, 11 = Do not use
3-2 OUTPUT CHC MUX SEL R/W 0h SERDES lane swap with ch D.
00 = Ch C is output on lane DC
10 = Ch C is output on lane DD
01, 11 = Do not use
1-0 OUTPUT CHD MUX SEL R/W 0h SERDES lane swap with ch C.
00 = Ch D is output on lane DD
10 = Ch D is output on lane DC
01, 11 = Do not use

7.6.3.7.16 Register 22h (address = 22h) [reset = 0h], JESD Digital Page (6900h)

Figure 137. Register 22h
7 6 5 4 3 2 1 0
0 0 0 0 OUT CHA INV OUT CHB INV OUT CHC INV OUT CHD INV
W-0h W-0h W-0h W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 68. 22h Field Descriptions

Bit Name Type Reset Description
7-4 0 W 0h Must write 0.
3 OUT CHA INV R/W 0h Polarity inversion of JESD output of ch A.
0 = Normal operation
1 = Output polarity inverted
2 OUT CHB INV R/W 0h Polarity inversion of JESD output of ch B.
0 = Normal operation
1 = Output polarity inverted
1 OUT CHC INV R/W 0h Polarity inversion of JESD output of ch C.
0 = Normal operation
1 = Output polarity inverted
0 OUT CHD INV R/W 0h Polarity inversion of JESD output of ch D.
0 = Normal operation
1 = Output polarity inverted

7.6.3.8 JESD Analog Page (6A00h) Register

7.6.3.8.1 Register 12h, 13h (address 12h, 13h) [reset = 0h], JESD Analog Page (6Ah)

Figure 138. Register 12h
7 6 5 4 3 2 1 0
SEL EMP LANE DA/DD 0 0
R/W-0h W-0h W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Figure 139. Register 13h
7 6 5 4 3 2 1 0
SEL EMP LANE DB/DC 0 0
R/W-0h W-0h W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 69. 12h, 13h Field Descriptions

Bit Name Type Reset Description
7-2 SEL EMP LANE DA/DD
SEL EMP LANE DB/DC
R/W 0h Selects the amount of de-emphasis for the JESD output transmitter. The de-emphasis value in dB is measured as the ratio between the peak value after the signal transition to the settled value of the voltage in one bit period.
0 = 0 dB
1 = –1 dB
3 = –2 dB
7 = –4.1 dB
15 = –6.2 dB
31 = –8.2 dB
63 = –11.5 dB
1-0 0 W 0h Must write 0.

7.6.3.8.2 16h (address = 16h) [reset = 0h], JESD Analog Page (6A00h)

Figure 140. Register 16h
7 6 5 4 3 2 1 0
0 0 0 0 0 0 JESD PLL MODE
W-0h W-0h W-0h W-0h W-0h W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 70. 16h Field Descriptions

Bit Name Type Reset Description
7-1 0 W 0h Must write 0.
0 JESD PLL MODE R/W 0h This bit selects the JESD PLL multiplication factor.
0 = 20x mode
1 = 40x mode

7.6.3.8.3 Register 1Bh (address = 1Bh) [reset = 0h], JESD Analog Page (6Ah)

Figure 141. Register 1Bh
7 6 5 4 3 2 1 0
JESD SWING 0 0 0 0 0
R/W-0h W-0h W-0h W-0h W-0h W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 71. 1Bh Field Descriptions

Bit Name Type Reset Description
7-5 JESD SWING R/W 0h This bit programs the SERDES output swing.
0 = 860 mVPP
1 = 810 mVPP
2 = 770 mVPP
3 = 745 mVPP
4 = 960 mVPP
5 = 930 mVPP
6 = 905 mVPP
7 = 880 mVPP
4-3 0 W 0h Must write 0.