Product details

Sample rate (Max) (MSPS) 500 Resolution (Bits) 14 Number of input channels 4 Interface type JESD204B Analog input BW (MHz) 900 Features High Performance Rating Catalog Input range (Vp-p) 1.9 Power consumption (Typ) (mW) 2700 Architecture Pipeline SNR (dB) 74.1 ENOB (Bits) 11.4 SFDR (dB) 97 Operating temperature range (C) -40 to 85 Input buffer Yes
Sample rate (Max) (MSPS) 500 Resolution (Bits) 14 Number of input channels 4 Interface type JESD204B Analog input BW (MHz) 900 Features High Performance Rating Catalog Input range (Vp-p) 1.9 Power consumption (Typ) (mW) 2700 Architecture Pipeline SNR (dB) 74.1 ENOB (Bits) 11.4 SFDR (dB) 97 Operating temperature range (C) -40 to 85 Input buffer Yes
VQFNP (RMP) 72 100 mm² 10 x 10
  • Quad Channel
  • 14-Bit Resolution
  • Maximum Clock Rate: 500 MSPS
  • Input Bandwidth (3 dB): 900 MHz
  • On-Chip Dither
  • Analog Input Buffer with High-Impedance Input
  • Output Options:
    • Rx: Decimate-by-2 and -4 Options with
      Low-Pass Filter
    • 200-MHz Complex Bandwidth or 100-MHz
      Real Bandwidth Support
    • DPD FB: 500 MSPS
  • 1.9-VPP Differential Full-Scale Input
  • JESD204B Interface:
    • Subclass 1 Support
    • 1 Lane per ADC Up to 10 Gbps
    • Dedicated SYNC Pin for Pair of Channels
  • Support for Multi-Chip Synchronization
  • 72-Pin VQFN Package (10 mm × 10 mm)
  • Key Specifications:
    • Power Dissipation: 675 mW/ch
    • Spectral Performance (Un-Decimated)
      • fIN = 190 MHz IF at –1 dBFS:
        • SNR: 69.5 dBFS
        • NSD: -153.5 dBFS/Hz
        • SFDR: 86 dBc (HD2, HD3),
          93 dBFS (non HD2, HD3)
      • fIN = 370 MHz IF at –3 dBFS:
        • SNR: 68.5 dBFS
        • NSD: –152.5 dBFS/Hz
        • SFDR: 81 dBc (HD2, HD3),
          86 dBFS (Non HD2, HD3)
  • Quad Channel
  • 14-Bit Resolution
  • Maximum Clock Rate: 500 MSPS
  • Input Bandwidth (3 dB): 900 MHz
  • On-Chip Dither
  • Analog Input Buffer with High-Impedance Input
  • Output Options:
    • Rx: Decimate-by-2 and -4 Options with
      Low-Pass Filter
    • 200-MHz Complex Bandwidth or 100-MHz
      Real Bandwidth Support
    • DPD FB: 500 MSPS
  • 1.9-VPP Differential Full-Scale Input
  • JESD204B Interface:
    • Subclass 1 Support
    • 1 Lane per ADC Up to 10 Gbps
    • Dedicated SYNC Pin for Pair of Channels
  • Support for Multi-Chip Synchronization
  • 72-Pin VQFN Package (10 mm × 10 mm)
  • Key Specifications:
    • Power Dissipation: 675 mW/ch
    • Spectral Performance (Un-Decimated)
      • fIN = 190 MHz IF at –1 dBFS:
        • SNR: 69.5 dBFS
        • NSD: -153.5 dBFS/Hz
        • SFDR: 86 dBc (HD2, HD3),
          93 dBFS (non HD2, HD3)
      • fIN = 370 MHz IF at –3 dBFS:
        • SNR: 68.5 dBFS
        • NSD: –152.5 dBFS/Hz
        • SFDR: 81 dBc (HD2, HD3),
          86 dBFS (Non HD2, HD3)

The ADS54J66 is a low-power, wide-bandwidth, 14-bit, 500-MSPS, quad-channel, telecom receiver device. The ADS54J66 supports a JESD204B serial interface with data rates up to 10 Gbps with one lane per channel. The buffered analog input provides uniform input impedance across a wide frequency range and minimizes sample-and-hold glitch energy. The ADS54J66 provides excellent spurious-free dynamic range (SFDR) over a large input frequency range with very low power consumption. The digital signal processing block includes complex mixers followed by low-pass filters with decimate-by-2 and -4 options supporting up to 200-MHz receive bandwidth.

The JESD204B interface reduces the number of interface lines, thus allowing high system integration density. An internal phase locked loop (PLL) multiplies the incoming analog-to-digital converter (ADC) sampling clock to derive the bit clock, which is used to serialize the 14-bit data from each channel.

The ADS54J66 is a low-power, wide-bandwidth, 14-bit, 500-MSPS, quad-channel, telecom receiver device. The ADS54J66 supports a JESD204B serial interface with data rates up to 10 Gbps with one lane per channel. The buffered analog input provides uniform input impedance across a wide frequency range and minimizes sample-and-hold glitch energy. The ADS54J66 provides excellent spurious-free dynamic range (SFDR) over a large input frequency range with very low power consumption. The digital signal processing block includes complex mixers followed by low-pass filters with decimate-by-2 and -4 options supporting up to 200-MHz receive bandwidth.

The JESD204B interface reduces the number of interface lines, thus allowing high system integration density. An internal phase locked loop (PLL) multiplies the incoming analog-to-digital converter (ADC) sampling clock to derive the bit clock, which is used to serialize the 14-bit data from each channel.

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Technical documentation

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Type Title Date
* Data sheet ADS54J66 Quad-Channel, 14-Bit, 500-MSPS ADC with Integrated DDC datasheet (Rev. A) PDF | HTML 14 Dec 2015
EVM User's guide ADS54J/58J6x Evaluation Module User's Guide (Rev. D) 13 Jan 2016

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

ADS54J66EVM — ADS54J66 Quad-Channel, 14-Bit, 500-MSPS Analog-to-Digital Converter Evaluation Module

The ADS54J66EVM is an evaluation module (EVM) that allows for the evaluation of Texas Instruments’ ADS54J66 and LMK04828 clock jitter cleaner. The ADS54J66 is a low power, 14-bit, 500-MSPS analog to digital converter (ADC) with a buffered analog input and outputs featuring a JESD204B (...)

Not available on TI.com
Firmware

TI-JESD204-IP — JESD204 Rapid Design IP for FPGAs connected to TI high-speed data converters

The JESD204 rapid design IP has been designed to enable FPGA engineers to achieve an accelerated path to a working JESD204 system. The IP has been architected in a way that downstream digital processing and other application logic are isolated from most of the performance- and timing-critical (...)
GUI for evaluation module (EVM)

ADS54Jxx EVM GUI (Rev. I)

SLAC594I.ZIP (163948 KB)
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Support software

DATACONVERTERPRO-SW — High-speed data converter pro software

This high-speed data converter pro GUI is a PC (Windows® XP/7/10 compatible) program designed to aid in evaluation of most TI high-speed data converter and analog front-end (AFE) platforms. Designed to support the entire TSW14xxx series of data-capture and pattern-generation cards, (...)
Simulation model

ADS54J66 IBIS-AMI Model

SBAM313.ZIP (2639 KB) - IBIS-AMI Model
Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Gerber file

ADS54Jxx Design File (Rev. A)

SBAC155A.ZIP (3977 KB)
Package Pins Download
VQFN (RMP) 72 View options

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