ADS54J66

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Quad-Channel, 14-Bit, 500-MSPS Analog-to-Digital Converter (ADC)

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Product details

Parameters

Sample rate (Max) (MSPS) 500 Resolution (Bits) 14 Number of input channels 4 Interface type JESD204B Analog input BW (MHz) 900 Features High Performance Rating Catalog Input range (Vp-p) 1.9 Power consumption (Typ) (mW) 2700 Architecture Pipeline SNR (dB) 74.1 ENOB (Bits) 11.4 SFDR (dB) 97 Operating temperature range (C) -40 to 85 Input buffer Yes open-in-new Find other High-speed ADCs (>10MSPS)

Package | Pins | Size

VQFNP (RMP) 72 100 mm² 10 x 10 open-in-new Find other High-speed ADCs (>10MSPS)

Features

  • Quad Channel
  • 14-Bit Resolution
  • Maximum Clock Rate: 500 MSPS
  • Input Bandwidth (3 dB): 900 MHz
  • On-Chip Dither
  • Analog Input Buffer with High-Impedance Input
  • Output Options:
    • Rx: Decimate-by-2 and -4 Options with
      Low-Pass Filter
    • 200-MHz Complex Bandwidth or 100-MHz
      Real Bandwidth Support
    • DPD FB: 500 MSPS
  • 1.9-VPP Differential Full-Scale Input
  • JESD204B Interface:
    • Subclass 1 Support
    • 1 Lane per ADC Up to 10 Gbps
    • Dedicated SYNC Pin for Pair of Channels
  • Support for Multi-Chip Synchronization
  • 72-Pin VQFN Package (10 mm × 10 mm)
  • Key Specifications:
    • Power Dissipation: 675 mW/ch
    • Spectral Performance (Un-Decimated)
      • fIN = 190 MHz IF at –1 dBFS:
        • SNR: 69.5 dBFS
        • NSD: -153.5 dBFS/Hz
        • SFDR: 86 dBc (HD2, HD3),
          93 dBFS (non HD2, HD3)
      • fIN = 370 MHz IF at –3 dBFS:
        • SNR: 68.5 dBFS
        • NSD: –152.5 dBFS/Hz
        • SFDR: 81 dBc (HD2, HD3),
          86 dBFS (Non HD2, HD3)
open-in-new Find other High-speed ADCs (>10MSPS)

Description

The ADS54J66 is a low-power, wide-bandwidth, 14-bit, 500-MSPS, quad-channel, telecom receiver device. The ADS54J66 supports a JESD204B serial interface with data rates up to 10 Gbps with one lane per channel. The buffered analog input provides uniform input impedance across a wide frequency range and minimizes sample-and-hold glitch energy. The ADS54J66 provides excellent spurious-free dynamic range (SFDR) over a large input frequency range with very low power consumption. The digital signal processing block includes complex mixers followed by low-pass filters with decimate-by-2 and -4 options supporting up to 200-MHz receive bandwidth.

The JESD204B interface reduces the number of interface lines, thus allowing high system integration density. An internal phase locked loop (PLL) multiplies the incoming analog-to-digital converter (ADC) sampling clock to derive the bit clock, which is used to serialize the 14-bit data from each channel.

open-in-new Find other High-speed ADCs (>10MSPS)
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Technical documentation

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Type Title Date
* Data sheet ADS54J66 Quad-Channel, 14-Bit, 500-MSPS ADC with Integrated DDC datasheet (Rev. A) Dec. 14, 2015
Technical article Keys to quick success using high-speed data converters Oct. 13, 2020
Technical article How to achieve fast frequency hopping Mar. 03, 2019
Technical article RF sampling: Learning more about latency Feb. 09, 2017
Technical article Why phase noise matters in RF sampling converters Nov. 28, 2016
User guide ADS54J/58J6x Evaluation Module User's Guide (Rev. D) Jan. 13, 2016

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARD Download
document-generic User guide
799
Description

The ADS54J66EVM is an evaluation module (EVM) that allows for the evaluation of Texas Instruments’ ADS54J66 and LMK04828 clock jitter cleaner. The ADS54J66 is a low power, 14-bit, 500-MSPS analog to digital converter (ADC) with a buffered analog input and outputs featuring a JESD204B (...)

Features
  • Flexible transformer coupled analog input to allow for a variety of sources and frequencies
  • Easy to use software GUI to configure the ADS54J66 and LMK04828 for a variety of configurations through a USB interface
  • Quickly evaluate ADC performance through High Speed Data Converter Pro software
  • Simple (...)

Software development

FIRMWARE Download
JESD204 Rapid Design IP for FPGAs connected to TI high-speed data converters
TI-JESD204-IP The JESD204 rapid design IP has been designed to enable FPGA engineers to achieve an accelerated path to a working JESD204 system. The IP has been architected in a way that downstream digital processing and other application logic are isolated from most of the performance- and timing-critical (...)
Features
  • Compatible with JEDEC JESD204a/b/c protocols
  • Supports subclass 1 deterministic latency and multidevice synchronization
  • Supported lane rates
    • Up to 16.375 Gbps in 8b/10b mode
    • Up to 20 Gbps in 64b/66b mode
  • Supports all protocol related error detection and reporting features
  • Integrated transport layer (...)
SUPPORT SOFTWARE Download
High-speed data converter pro software
DATACONVERTERPRO-SW This high-speed data converter pro GUI is a PC (Windows® XP/7/10 compatible) program designed to aid in evaluation of most TI high-speed data converter and analog front-end (AFE) platforms. Designed to support the entire TSW14xxx series of data-capture and pattern-generation cards (...)
Features
  • Compatible with TSW1400, TSW1405, TSW1406, TSW14J10, TSW14J50, TSW14J56, TSW14J57 and TSW14J58 pattern-generation and data-capture platforms
  • Works with all TI high-speed DAC, ADC, and AFE products
  • Provides time-domain and frequency-domain analysis
  • Supports single-tone, multi-tone, and modulated (...)

Design tools & simulation

SIMULATION MODEL Download
SBAM313.ZIP (2639 KB) - IBIS-AMI Model
SIMULATION TOOL Download
PSpice® for TI design and simulation tool
PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Features
  • Leverages Cadence PSpice Technology
  • Preinstalled library with a suite of digital models to enable worst-case timing analysis
  • Dynamic updates ensure you have access to most current device models
  • Optimized for simulation speed without loss of accuracy
  • Supports simultaneous analysis of multiple products
  • (...)
GERBER FILE Download
SBAC155A.ZIP (3977 KB)

CAD/CAE symbols

Package Pins Download
VQFN (RMP) 72 View options

Ordering & quality

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  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring

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