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ADC3669 ACTIVE 16-bit two-channel 500MSPS ADC with LVDS interface and up to 32768x decimation Lower power, higher SNR, smaller package size, LVDS interface

Product details

Sample rate (max) (Msps) 500 Resolution (Bits) 14 Number of input channels 4 Interface type JESD204B Analog input BW (MHz) 900 Features High Performance Rating Catalog Peak-to-peak input voltage range (V) 1.9 Power consumption (typ) (mW) 2700 Architecture Pipeline SNR (dB) 74.1 ENOB (Bits) 11.4 SFDR (dB) 97 Operating temperature range (°C) -40 to 85 Input buffer Yes
Sample rate (max) (Msps) 500 Resolution (Bits) 14 Number of input channels 4 Interface type JESD204B Analog input BW (MHz) 900 Features High Performance Rating Catalog Peak-to-peak input voltage range (V) 1.9 Power consumption (typ) (mW) 2700 Architecture Pipeline SNR (dB) 74.1 ENOB (Bits) 11.4 SFDR (dB) 97 Operating temperature range (°C) -40 to 85 Input buffer Yes
VQFNP (RMP) 72 100 mm² 10 x 10
  • Quad channel
  • 14-Bit resolution
  • Maximum clock rate: 500 MSPS
  • Input bandwidth (3 dB): 900 MHz
  • On-chip dither
  • Analog Input buffer with high-impedance input
  • Output options:
    • Rx: decimate-by-2 and -4 options with Low-Pass lFilter
    • 200-MHz Complex bandwidth or 100-MHz real bandwidth support
    • DPD FB: 500 MSPS
  • 1.9-VPP Differential full-scale input
  • JESD204B interface:
    • Subclass 1 support
    • 1 Lane per ADC Up to 10 Gbps
    • Dedicated SYNC pin for pair of channels
  • Support for multi-chip synchronization
  • 72-Pin VQFN package (10 mm × 10 mm)
  • Key specifications:
    • Power dissipation: 675 mW/ch
    • Spectral performance (un-decimated)
      • fIN = 190 MHz IF at –1 dBFS:
        • SNR: 69.5 dBFS
        • NSD: –153.5 dBFS/Hz
        • SFDR: 86 dBc (HD2, HD3), 93 dBFS (Non HD2, HD3)
      • fIN = 370 MHz IF at –3 dBFS:
        • SNR: 68.5 dBFS
        • NSD: –152.5 dBFS/Hz
        • SFDR: 81 dBc (HD2, HD3), 86 dBFS (Non HD2, HD3)
  • Quad channel
  • 14-Bit resolution
  • Maximum clock rate: 500 MSPS
  • Input bandwidth (3 dB): 900 MHz
  • On-chip dither
  • Analog Input buffer with high-impedance input
  • Output options:
    • Rx: decimate-by-2 and -4 options with Low-Pass lFilter
    • 200-MHz Complex bandwidth or 100-MHz real bandwidth support
    • DPD FB: 500 MSPS
  • 1.9-VPP Differential full-scale input
  • JESD204B interface:
    • Subclass 1 support
    • 1 Lane per ADC Up to 10 Gbps
    • Dedicated SYNC pin for pair of channels
  • Support for multi-chip synchronization
  • 72-Pin VQFN package (10 mm × 10 mm)
  • Key specifications:
    • Power dissipation: 675 mW/ch
    • Spectral performance (un-decimated)
      • fIN = 190 MHz IF at –1 dBFS:
        • SNR: 69.5 dBFS
        • NSD: –153.5 dBFS/Hz
        • SFDR: 86 dBc (HD2, HD3), 93 dBFS (Non HD2, HD3)
      • fIN = 370 MHz IF at –3 dBFS:
        • SNR: 68.5 dBFS
        • NSD: –152.5 dBFS/Hz
        • SFDR: 81 dBc (HD2, HD3), 86 dBFS (Non HD2, HD3)

The ADS54J66 is a low-power, wide-bandwidth, 14-bit, 500-MSPS, quad-channel, telecom receiver device. The ADS54J66 supports a JESD204B serial interface with data rates up to 10 Gbps with one lane per channel. The buffered analog input provides uniform input impedance across a wide frequency range and minimizes sample-and-hold glitch energy. The ADS54J66 provides excellent spurious-free dynamic range (SFDR) over a large input frequency range with very low power consumption. The digital signal processing block includes complex mixers followed by low-pass filters with decimate-by-2 and -4 options supporting up to 200-MHz receive bandwidth.

The JESD204B interface reduces the number of interface lines, thus allowing high system integration density. An internal phase-locked loop (PLL) multiplies the incoming analog-to-digital converter (ADC) sampling clock to derive the bit clock, which is used to serialize the 14-bit data from each channel.

The ADS54J66 is a low-power, wide-bandwidth, 14-bit, 500-MSPS, quad-channel, telecom receiver device. The ADS54J66 supports a JESD204B serial interface with data rates up to 10 Gbps with one lane per channel. The buffered analog input provides uniform input impedance across a wide frequency range and minimizes sample-and-hold glitch energy. The ADS54J66 provides excellent spurious-free dynamic range (SFDR) over a large input frequency range with very low power consumption. The digital signal processing block includes complex mixers followed by low-pass filters with decimate-by-2 and -4 options supporting up to 200-MHz receive bandwidth.

The JESD204B interface reduces the number of interface lines, thus allowing high system integration density. An internal phase-locked loop (PLL) multiplies the incoming analog-to-digital converter (ADC) sampling clock to derive the bit clock, which is used to serialize the 14-bit data from each channel.

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* Data sheet ADS54J66 Quad-channel, 14-bit, 500-MSPS ADC with Integrated DDC datasheet (Rev. B) PDF | HTML 03 Jan 2023

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

ADS54J66EVM — ADS54J66 Quad-Channel, 14-Bit, 500-MSPS Analog-to-Digital Converter Evaluation Module

The ADS54J66EVM is an evaluation module (EVM) that allows for the evaluation of Texas Instruments’ ADS54J66 and LMK04828 clock jitter cleaner. The ADS54J66 is a low power, 14-bit, 500-MSPS analog to digital converter (ADC) with a buffered analog input and outputs featuring a JESD204B (...)

User guide: PDF
Not available on TI.com
Firmware

TI204C-IP Request for JESD204 rapid design IP

The JESD204 rapid design IP has been designed to enable FPGA engineers to achieve an accelerated path to a working JESD204 system. The IP has been architected in a way that downstream digital processing and other application logic are isolated from most of the performance- and timing-critical (...)

Supported products & hardware

Supported products & hardware

GUI for evaluation module (EVM)

DATACONVERTERPRO-SW High Speed Data Converter Pro GUI Installer, v5.31

This high-speed data converter pro GUI is a PC (Windows® XP/7/10 compatible) program designed to aid in evaluation of most TI high-speed data converter [analog-to-digital converter (ADC) and digital-to-analog converter (DAC)] and analog front-end (AFE) platforms. Designed to support the entire (...)

Supported products & hardware

Supported products & hardware

GUI for evaluation module (EVM)

SLAC594 ADS54Jxx EVM GUI

Supported products & hardware

Supported products & hardware

Simulation model

ADS54J66 IBIS-AMI Model

SBAM313.ZIP (2639 KB) - IBIS-AMI Model
Calculation tool

ANALOG-ENGINEER-CALC PC software analog engineer's calculator

The analog engineer’s calculator is designed to speed up many of the repetitive calculations that analog circuit design engineers use on a regular basis. This PC-based tool provides a graphical interface with a list of various common calculations ranging from setting operational-amplifier (...)

Supported products & hardware

Supported products & hardware

Gerber file

ADS54Jxx Design File (Rev. A)

SBAC155A.ZIP (3977 KB)
Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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VQFNP (RMP) 72 Ultra Librarian

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