SBAS745A November   2015  – December 2015 ADS54J66

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  AC Performance
    7. 6.7  Digital Characteristics
    8. 6.8  Timing Characteristics
    9. 6.9  Typical Characteristics: General (DDC Mode-8)
    10. 6.10 Typical Characteristics: Mode 2
    11. 6.11 Typical Characteristics: Mode 0
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Inputs
      2. 7.3.2 Recommended Input Circuitry
    4. 7.4 Device Functional Modes
      1. 7.4.1 Digital Features
      2. 7.4.2 Mode 0, Decimation-by-2 with IQ Outputs for up to 220 MHz of IQ Bandwidth
      3. 7.4.3 Mode 2, Decimation-by-2 for up to 110 MHz of Real Bandwidth
      4. 7.4.4 Modes 4 and 7, Decimation-by-2 with Real Outputs for up to 110 MHz of Bandwidth
      5. 7.4.5 Mode 5, Decimation-by-2 with IQ Outputs for up to 110 MHz of IQ Bandwidth
      6. 7.4.6 Mode 6, Decimation-by-4 with IQ Outputs for up to 110 MHz of IQ Bandwidth
      7. 7.4.7 Overrange Indication
      8. 7.4.8 Power-Down Mode
    5. 7.5 Programming
      1. 7.5.1 Device Configuration
        1. 7.5.1.1 Details of the Serial Interface
        2. 7.5.1.2 Serial Register Write: Analog Bank
        3. 7.5.1.3 Serial Register Readout: Analog Bank
        4. 7.5.1.4 JESD Bank SPI Page Selection
        5. 7.5.1.5 Serial Register Write: Digital Bank
        6. 7.5.1.6 Individual Channel Programming
        7. 7.5.1.7 Serial Register Readout: JESD Bank
      2. 7.5.2 JESD204B Interface
        1. 7.5.2.1 JESD204B Initial Lane Alignment (ILA)
        2. 7.5.2.2 JESD204B Frame Assembly
        3. 7.5.2.3 JESD Output Switch
          1. 7.5.2.3.1 SERDES Transmitter Interface
          2. 7.5.2.3.2 SYNCb Interface
          3. 7.5.2.3.3 Eye Diagram
    6. 7.6 Register Maps
      1. 7.6.1 Detailed Register Information
      2. 7.6.2 Example Register Writes
      3. 7.6.3 Register Descriptions
        1. 7.6.3.1 General Registers
          1. 7.6.3.1.1 Register 0h (offset = 0h) [reset = 0h]
          2. 7.6.3.1.2 Register 3h, 4h (offset = 3h, 4h) [reset = 0h]
          3. 7.6.3.1.3 Register 5h (offset = 5h) [reset = 0h]
          4. 7.6.3.1.4 Register 11h (offset = 11h) [reset = 0h]
        2. 7.6.3.2 Master Page (80h)
          1. 7.6.3.2.1  Register 20h (address = 20h) [reset = 0h], Master Page (080h)
          2. 7.6.3.2.2  Register 21h (address = 21h) [reset = 0h], Master Page (080h)
          3. 7.6.3.2.3  Register 23h (address = 23h), Master Page (080h)
          4. 7.6.3.2.4  Register 24h (address = 24h) [reset = 0h], Master Page (080h)
          5. 7.6.3.2.5  Register 26h (address = 26h), Master Page (080h)
          6. 7.6.3.2.6  Register 3Ah (address = 3Ah) [reset = 0h], Master Page (80h)
          7. 7.6.3.2.7  Register 39h (address = 39h) [reset = 0h], Master Page (80h)
          8. 7.6.3.2.8  Register 53h (address = 53h) [reset = 0h], Master Page (80h)
          9. 7.6.3.2.9  Register 55h (address = 55h) [reset = 0h], Master Page (80h)
          10. 7.6.3.2.10 Register 56h (address = 56h) [reset = 0h], Master Page (80h)
          11. 7.6.3.2.11 Register 59h (address = 59h) [reset = 0h], Master Page (80h)
        3. 7.6.3.3 ADC Page (0Fh)
          1. 7.6.3.3.1  Register 5Fh (address = 5Fh) [reset = 0h], ADC Page (0Fh)
          2. 7.6.3.3.2  Register 60h (address = 60h) [reset = 0h], ADC Page (0Fh)
          3. 7.6.3.3.3  Register 61h (address = 61h) [reset = 0h], ADC Page (0Fh)
          4. 7.6.3.3.4  Register 6Ch (address = 6Ch) [reset = 0h], ADC Page (0Fh)
          5. 7.6.3.3.5  Register 6Dh (address = 6Dh) [reset = 0h], ADC Page (0Fh)
          6. 7.6.3.3.6  Register 74h (address = 74h) [reset = 0h], ADC Page (0Fh)
          7. 7.6.3.3.7  Register 75h (address = 75h) [reset = 0h], ADC Page (0Fh)
          8. 7.6.3.3.8  Register 76h (address = 76h) [reset = 0h], ADC Page (0Fh)
          9. 7.6.3.3.9  Register 77h (address = 77h) [reset = 0h], ADC Page (0Fh)
          10. 7.6.3.3.10 Register 78h (address = 78h) [reset = 0h], ADC Page (0Fh)
        4. 7.6.3.4 Interleaving Engine Page (6100h)
          1. 7.6.3.4.1 Register 18h (address = 18h) [reset = 0h], Interleaving Engine Page (6100h)
          2. 7.6.3.4.2 Register 68h (address = 68h) [reset = 0h], Interleaving Engine Page (6100h)
        5. 7.6.3.5 Decimation Filter Page (6141h) Registers
          1. 7.6.3.5.1 Register 0h (address = 0h) [reset = 0h], Decimation Filter Page (6141h)
          2. 7.6.3.5.2 Register 1h (address = 1h) [reset = 0h], Decimation Filter Page (6141h)
          3. 7.6.3.5.3 Register 2h (address = 2h) [reset = 0h], Decimation Filter Page (6141h)
        6. 7.6.3.6 Main Digital Page (6800h) Registers
          1. 7.6.3.6.1 Register 0h (address = 0h) [reset = 0h], Main Digital Page (6800h)
          2. 7.6.3.6.2 Register 42h (address = 42h) [reset = 0h], Main Digital Page (6800h)
          3. 7.6.3.6.3 Register 4Eh (address = 4Eh) [reset = 0h], Main Digital Page (6800h)
          4. 7.6.3.6.4 Register ABh (address = ABh) [reset = 0h], Main Digital Page (6800h)
          5. 7.6.3.6.5 Register ADh (address = ADh) [reset = 0h], Main Digital Page (6800h)
          6. 7.6.3.6.6 Register F7h (address = F7h) [reset = 0h], Main Digital Page (68h)
        7. 7.6.3.7 JESD Digital Page (6900h) Registers
          1. 7.6.3.7.1  Register 0h (address = 0h) [reset = 0h], JESD Digital Page (6900h)
          2. 7.6.3.7.2  Register 1h (address = 1h) [reset = 0h], JESD Digital Page (6900h)
          3. 7.6.3.7.3  Register 2h (address = 2h) [reset = 0h], JESD Digital Page (6900h)
          4. 7.6.3.7.4  Register 3h (address = 3h) [reset = 0h], JESD Digital Page (6900h)
          5. 7.6.3.7.5  Register 5h (address = 5h) [reset = 0h], JESD Digital Page (6900h)
          6. 7.6.3.7.6  Register 6h (address = 6h) [reset = 0h], JESD Digital Page (6900h)
          7. 7.6.3.7.7  Register 19h (address = 19h) [reset = 0h], JESD Digital Page (6900h)
          8. 7.6.3.7.8  Register 1Ah (address = 1Ah) [reset = 0h], JESD Digital Page (6900h)
          9. 7.6.3.7.9  Register 1Bh (address = 1Bh) [reset = 0h], JESD Digital Page (6900h)
          10. 7.6.3.7.10 Register 1Ch (address = 1Ch) [reset = 0h], JESD Digital Page (6900h)
          11. 7.6.3.7.11 Register 1Dh (address = 1Dh) [reset = 0h], JESD Digital Page (6900h)
          12. 7.6.3.7.12 Register 1Eh (address = 1Eh) [reset = 0h], JESD Digital Page (6900h)
          13. 7.6.3.7.13 Register 1Fh (address = 1Fh) [reset = 0h], JESD Digital Page (6900h)
          14. 7.6.3.7.14 Register 20h (address = 20h) [reset = 0h], JESD Digital Page (6900h)
          15. 7.6.3.7.15 Register 21h (address = 21h) [reset = 0h], JESD Digital Page (6900h)
          16. 7.6.3.7.16 Register 22h (address = 22h) [reset = 0h], JESD Digital Page (6900h)
        8. 7.6.3.8 JESD Analog Page (6A00h) Register
          1. 7.6.3.8.1 Register 12h, 13h (address 12h, 13h) [reset = 0h], JESD Analog Page (6Ah)
          2. 7.6.3.8.2 16h (address = 16h) [reset = 0h], JESD Analog Page (6A00h)
          3. 7.6.3.8.3 Register 1Bh (address = 1Bh) [reset = 0h], JESD Analog Page (6Ah)
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Start-Up Sequence
      2. 8.1.2 Hardware Reset
        1. 8.1.2.1 Register Initialization
      3. 8.1.3 SNR and Clock Jitter
      4. 8.1.4 ADC Test Pattern
        1. 8.1.4.1 ADC Section
        2. 8.1.4.2 Transport Layer Pattern
        3. 8.1.4.3 Link Layer Pattern
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Community Resources
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Supply voltage range AVDD3V –0.3 3.6 V
AVDD –0.3 2.1
DVDD –0.3 2.1
IOVDD –0.2 1.4
Voltage between AGND and DGND –0.3 0.3 V
Voltage applied to input pins INAP, INBP, INAM, INBM, INCP, INDP, INCM, INDM –0.3 3 V
CLKINP, CLKINM –0.3 AVDD + 0.3
SYSREFP, SYSREFM –0.3 AVDD + 0.3
SCLK, SEN, SDIN, RESET, SPI_MODE, SYNCbABP, SYNCbABM, SYNCbCDP, SYNCbCDM, PDN –0.2 2
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±1000 V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)(2)
MIN NOM MAX UNIT
Supply voltage range AVDD3V 2.85 3 3.6 V
AVDD 1.8 1.9 2
DVDD 1.8 1.9 2
IOVDD 1.1 1.15 1.2
Analog inputs Differential input voltage range 1.9 VPP
Input common-mode voltage 2.0 ± 0.025 V
Clock inputs Input clock frequency, device clock frequency 250 500 MHz
Input clock amplitude differential
(VCLKP – VCLKM)
Sine wave, ac-coupled 1.5 VPP
LVPECL, ac-coupled 1.6
LVDS, ac-coupled 0.7
Input device clock duty cycle, default after reset 45% 50% 55%
Temperature Operating free-air, TA –40 85 ºC
Operating junction, TJ 105(1) 125
(1) Prolonged use above this junction temperature can increase the device failure-in-time (FIT) rate.
(2) SYSREF must be applied for the device initialization.

6.4 Thermal Information

THERMAL METRIC(1) ADS54J66 UNIT
RMP (VQFNP)
72 PINS
RθJA Junction-to-ambient thermal resistance 22.3 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 5.1 °C/W
RθJB Junction-to-board thermal resistance 2.4 °C/W
ψJT Junction-to-top characterization parameter 0.1 °C/W
ψJB Junction-to-board characterization parameter 2.3 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 0.4 °C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = 85°C, ADC sampling frequency = 500 MSPS, 50% clock duty cycle, AVDD3V = 3 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, –1-dBFS differential input for IF ≤ 250 MHz, and –3-dBFS differential input for IF > 250 MHz (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
GENERAL
ADC sampling rate 500 MSPS
Resolution 14 Bits
POWER SUPPLY
AVDD3V 3-V analog supply 2.85 3 3.6 V
AVDD 1.9-V analog supply 1.8 1.9 2 V
DVDD 1.9-V digital supply 1.8 1.9 2 V
IOVDD 1.15-V SERDES supply 1.1 1.15 1.2 V
IAVDD3V 3-V analog supply current 370-MHz, full-scale input on all four channels 340 mA
IAVDD 1.9-V analog supply current 370-MHz, full-scale input on all four channels 365 mA
IDVDD 1.9-V digital supply current 2x decimation (4 channels), 370 MHz, full-scale input on all four channels 190 mA
DDC mode-8 (no decimation), 370 MHz,
full-scale input on all four channels
184
IIOVDD 1.15-V SERDES supply current DDC mode-8 (no decimation), 370 MHz,
full-scale input on all four channels
533 mA
Pdis Total power dissipation 2x decimation (4 channels), 370 MHz, full-scale input on all four channels 2.68 W
DDC mode-8 (no decimation), 370 MHz,
full-scale input on all four channels
2.67
Global power-down power dissipation Full-scale input on all four channels 250 mW
ANALOG INPUTS
Differential input full-scale voltage 1.9 VPP
Input common-mode voltage 2.0 V
Differential input resistance At fIN = 370 MHz 0.5
Differential input capacitance At fIN = 370 MHz 2.5 pF
Analog input bandwidth (3 dB) 900 MHz
ISOLATION
Crosstalk(1) isolation between near channels
(channels A and B are near to each other, channels C and D are near to each other)
fIN = 10 MHz 105 dBFS
fIN = 100 MHz 104
fIN = 170 MHz 96
fIN = 270 MHz 97
fIN = 370 MHz 93
fIN = 470 MHz 85
Crosstalk(1) isolation between far channels
(channels A and B, and channels C and D are far channels)
fIN = 10 MHz 110 dBFS
fIN = 100 MHz 107
fIN = 170 MHz 96
fIN = 270 MHz 97
fIN = 370 MHz 95
fIN = 470 MHz 94
CLOCK INPUT
Internal clock biasing CLKINP and CLKINM pins are connected to internal biasing voltage through 400 Ω 1.15 V
(1) Crosstalk is measured with a –1-dBFS input signal on aggressor channel and no input on the victim channel.

6.6 AC Performance

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS NO DECIMATION,
500-MSPS OUTPUT
(DDC Mode 8)
DECIMATE-BY-2,
250-MSPS OUTPUT
(DDC Mode 2)
UNIT
MIN TYP MAX MIN TYP MAX
SNR Signal-to-noise ratio fIN = 10 MHz 70.8 74.1 dBFS
fIN = 70 MHz 70.5 74
fIN = 190 MHz, AIN = –1 dBFS 69.5 73.2
fIN = 190 MHz, AIN = –3 dBFS 65.6 70.3 73.6
fIN = 300 MHz 69 72.6
fIN = 350 MHz 68.7 72
fIN = 370 MHz 64.6 68.4 71.5
fIN = 470 MHz 67.5 70.7
NSD Noise spectral density fIN = 10 MHz 154.8 155.1 dBFS/Hz
fIN = 70 MHz 154.5 155
fIN = 190 MHz, AIN = –1 dBFS 153.5 154.2
fIN = 190 MHz, AIN = –3 dBFS 149.6 154.3 154.6
fIN = 300 MHz 153 153.6
fIN = 350 MHz 152.7 153
fIN = 370 MHz 148.6 152.4 152.5
fIN = 470 MHz 151.5 151.7
SINAD Signal-to-noise and distortion ratio fIN = 10 MHz 70.7 73.9 dBFS
fIN = 70 MHz 70.4 73.9
fIN = 190 MHz, AIN = –1 dBFS 69.4 73.1
fIN = 190 MHz, AIN = –3 dBFS 70.2 73.5
fIN = 300 MHz 68.9 72.5
fIN = 350 MHz 68.6 71.7
fIN = 370 MHz 68.2
fIN = 470 MHz 66.9 69.7
SFDR Spurious-free dynamic range fIN = 10 MHz 89 88 dBc
fIN = 70 MHz 87 95
fIN = 190 MHz, AIN = –1 dBFS 86 97
fIN = 190 MHz, AIN = –3 dBFS 78 88 96
fIN = 300 MHz 82 94
fIN = 350 MHz 82 82
fIN = 370 MHz 75 81
fIN = 470 MHz 73 74
HD2 Second-order harmonic distortion fIN = 10 MHz 89 91 dBc
fIN = 70 MHz 94 103
fIN = 190 MHz, AIN = –1 dBFS 86 101
fIN = 190 MHz, AIN = –3 dBFS 78 88 101
fIN = 300 MHz 82 97
fIN = 350 MHz 82 82
fIN = 370 MHz 75 81
fIN = 470 MHz 73 74
HD3 Third-order harmonic distortion fIN = 10 MHz 93 88 dBc
fIN = 70 MHz 87 99
fIN = 190 MHz, AIN = –1 dBFS 98 100
fIN = 190 MHz, AIN = –3 dBFS 78 97 98
fIN = 300 MHz 95 100
fIN = 350 MHz 90 96
fIN = 370 MHz 75 85
fIN = 470 MHz 83 83
Non HD2, HD3 Spurious-free
dynamic range
(excluding HD2, HD3)
fIN = 10 MHz 94 98 dBc
fIN = 70 MHz 94 95
fIN = 190 MHz, AIN = –1 dBFS 93 97
fIN = 190 MHz, AIN = –3 dBFS 87 93 96
fIN = 300 MHz 92 94
fIN = 350 MHz 91 94
fIN = 370 MHz 80 90
fIN = 470 MHz 87 93
THD Total harmonic distortion fIN = 10 MHz 88 86 dBc
fIN = 70 MHz 85 92
fIN = 190 MHz, AIN = –1 dBFS 85 92
fIN = 190 MHz, AIN = –3 dBFS 86 91
fIN = 300 MHz 81 89
fIN = 350 MHz 79 82
fIN = 370 MHz 78
fIN = 470 MHz 72 73
IMD3 Two-tone, third-order intermodulation distortion fIN = 185 MHz, fIN = 190 MHz, AIN = –7 dBFS 89 dBFS
fIN = 365 MHz, fIN = 370 MHz, AIN = –7 dBFS 82
fIN = 465 MHz, fIN = 470 MHz, AIN = –7 dBFS 77

6.7 Digital Characteristics

typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 500 MSPS, 50% clock duty cycle, AVDD3V = 3 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, and –1-dBFS differential input (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DIGITAL INPUTS (RESET, SCLK, SEN, SDIN, PDN)(1)
VIH High-level input voltage All digital inputs support 1.2-V and 1.8-V logic levels 0.8 V
VIL Low-level input voltage All digital inputs support 1.2-V and 1.8-V logic levels 0.4 V
IIH High-level input current SEN 0 µA
RESET, SCLK, SDIN, PDN 100
IIL Low-level input current SEN 50 µA
RESET, SCLK, SDIN, PDN 0
DIGITAL INPUTS (SYSREFP, SYSREFM, SYNCbABM, SYNCbABP, SYNCbCDM, SYNCbCDP)
VD Differential input voltage 0.35 0.45 1.4 V
V(CM_DIG) Common-mode voltage for SYSREF 1.3 V
DIGITAL OUTPUTS (SDOUT, PDN)
VOH High-level output voltage DVDD – 0.1 DVDD V
VOL Low-level output voltage 0.1 V
DIGITAL OUTPUTS (JESD204B Interface: DxP, DxM)(2)
VOD Output differential voltage With default swing setting 700 mVPP
VOC Output common-mode voltage 450 mV
Transmitter short-circuit current Transmitter pins shorted to any voltage between –0.25 V and 1.45 V –100 100 mA
zos Single-ended output impedance 50 Ω
Output capacitance Output capacitance inside the device,
from either output to ground
2 pF
(1) The RESET, SCLK, SDATA, and PDN pins have a 20-kΩ (typical) internal pulldown resistor to ground, and the SEN pin has a 20-kΩ (typical) pull up resistor to IOVDD.
(2) 50-Ω, single-ended external termination to IOVDD.

6.8 Timing Characteristics

typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 500 MSPS, 50% clock duty cycle, AVDD3V = 3 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, and –1-dBFS differential input (unless otherwise noted)
MIN TYP MAX UNIT
SAMPLE TIMING CHARACTERISTICS
Aperture delay 0.75 1.6 ns
Aperture delay matching between two channels on the same device ±70 ps
Aperture delay matching between two devices at the same temperature and supply voltage ±270 ps
Aperture jitter 135 fS rms
Wake-up time to valid data after coming out of global power-down 150 µs
Data latency(1): ADC sample to digital output 77 Input clock cycles
OVR latency: ADC sample to OVR bit 44 Input clock cycles
tPDI Clock propagation delay: input clock rising edge cross-over to output clock rising edge cross-over 4 ns
tSU_SYSREF Setup time for SYSREF, referenced to input clock rising edge 300 900 ps
tH_SYSREF Hold time for SYSREF, referenced to input clock rising edge 100 ps
JESD OUTPUT INTERFACE TIMING CHARACTERISTICS
Unit interval 100 400 ps
Serial output data rate 2.5 10 Gbps
Total jitter for BER of 1E-15 and lane rate = 10 Gbps 26 ps
Random jitter for BER of 1E-15 and lane rate = 10 Gbps 0.75 ps rms
Deterministic jitter for BER of 1E-15 and lane rate = 10 Gbps 12 ps, pk-pk
tR, tF Data rise time, data fall time: rise and fall times measured from 20% to 80%, differential output waveform, 2.5 Gbps ≤ bit rate ≤ 10 Gbps 35 ps
(1) Overall ADC latency = data latency + tPDI.
ADS54J66 elect_char_clk_bas717.gif Figure 1. Latency Timing Diagram

6.9 Typical Characteristics: General (DDC Mode-8)

typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = 85°C, ADC sampling frequency = 500 MSPS, 14-bit resolution, no decimation filter, 50% clock duty cycle, AVDD3V = 3 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, –1-dBFS differential input for IF ≤ 250 MHz, and –3-dBFS differential input for IF > 250 MHz (unless otherwise noted)
ADS54J66 D001_SBAS717.gif
fIN = 10 MHz , AIN = –1 dBFS,
SNR = 71 dBFS, SFDR = 89 dBc, SFDR = 89 dBc (non 23)
Figure 2. FFT for 10-MHz Input Signal
ADS54J66 D003_SBAS717.gif
fIN = 190 MHz , AIN = –1 dBFS,
SNR = 69.4 dBFS, SFDR = 88 dBc, SFDR = 96 dBc (non 23)
Figure 4. FFT for 190-MHz Input Signal
ADS54J66 D005_SBAS717.gif
fIN = 300 MHz , AIN = –3 dBFS,
SNR = 69.4 dBFS, SFDR = 80 dBc, SFDR = 95 dBc (non 23)
Figure 6. FFT for 300-MHz Input Signal
ADS54J66 D007_SBAS717.gif
fIN = 470 MHz , AIN = –3 dBFS,
SNR = 67.4 dBFS, SFDR = 73 dBc, SFDR = 80 dBc (non 23)
Figure 8. FFT for 470-MHz Input Signal
ADS54J66 D009_SBAS717.gif
fIN1 = 185 MHz, fIN2 = 190 MHz, IMD = 103 dBFS,
each tone at –36 dBFS
Figure 10. FFT for Two-Tone Input Signal
ADS54J66 D011_SBAS717.gif
fIN1 = 370 MHz, fIN2 = 365 MHz, IMD = 102 dBFS,
each tone at –36 dBFS
Figure 12. FFT for Two-Tone Input Signal
ADS54J66 D013_SBAS717.gif
fIN1 = 470 MHz, fIN2 = 465 MHz, IMD = 98.8 dBFS,
each tone at –36 dBFS
Figure 14. FFT for Two-Tone Input Signal
ADS54J66 D015_SBAS717.gif
fIN1 = 365 MHz, fIN2 = 370 MHz
Figure 16. Intermodulation Distortion vs Input Amplitude
ADS54J66 D017_SBAS717.gif
Figure 18. Spurious-Free Dynamic Range vs
Input Frequency
ADS54J66 D019_SBAS717.gif
Figure 20. Signal-to-Noise Ratio vs Input Frequency
ADS54J66 D021_SBAS717.gif
fIN = 190 MHz, AIN = –1 dBFS
Figure 22. Spurious-Free Dynamic Range vs
AVDD Supply and Temperature
ADS54J66 D023_SBAS717.gif
fIN = 370 MHz, AIN = –3 dBFS
Figure 24. Spurious-Free Dynamic Range vs
AVDD Supply and Temperature
ADS54J66 D025_SBAS717.gif
fIN = 190 MHz, AIN = –1 dBFS
Figure 26. Spurious-Free Dynamic Range vs
DVDD Supply and Temperature
ADS54J66 D027_SBAS717.gif
fIN = 370 MHz, AIN = –3 dBFS
Figure 28. Spurious-Free Dynamic Range vs
DVDD Supply and Temperature
ADS54J66 D029_SBAS717.gif
fIN = 190 MHz, AIN = –1 dBFS
Figure 30. Spurious-Free Dynamic Range vs
AVDD3V Supply and Temperature
ADS54J66 D031_SBAS717.gif
fIN = 370 MHz, AIN = –3 dBFS
Figure 32. Spurious-Free Dynamic Range vs
AVDD3V Supply and Temperature
ADS54J66 D033_SBAS717.gif
fIN = 370 MHz
Figure 34. Performance vs Amplitude
ADS54J66 D035_SBAS717.gif
fIN = 370 MHz, AIN = –3 dBFS
Figure 36. Performance vs Clock Amplitude
ADS54J66 D037_SBAS717.gif
fIN = 370 MHz, AIN = –3 dBFS
Figure 38. Performance vs Clock Duty Cycle
ADS54J66 D039_SBAS717.gif
fIN = 190 MHz, AIN = –1 dBFS
Figure 40. Power-Supply Rejection Ratio vs Supplies
ADS54J66 D041_SBAS717.gif
fIN = 190 MHz, AIN= –1 dBFS
50-mVPP test signal on input common-mode
Figure 42. Common-Mode Rejection Ratio
ADS54J66 D002_SBAS717.gif
fIN = 140 MHz , AIN = –1 dBFS,
SNR = 70 dBFS, SFDR = 88 dBc, SFDR = 91 dBc (non 23)
Figure 3. FFT for 140-MHz Input Signal
ADS54J66 D004_SBAS717.gif
fIN = 230 MHz , AIN = –1 dBFS,
SNR = 69.4 dBFS, SFDR = 85 dBc, SFDR = 96 dBc (non 23)
Figure 5. FFT for 230-MHz Input Signal
ADS54J66 D006_SBAS717.gif
fIN = 370 MHz , AIN = –3 dBFS,
SNR = 68.4 dBFS, SFDR = 84 dBc, SFDR = 86 dBc (non 23)
Figure 7. FFT for 370-MHz Input Signal
ADS54J66 D008_SBAS717.gif
fIN1 = 185 MHz, fIN2 = 190 MHz, IMD = 89 dBFS,
each tone at –7 dBFS
Figure 9. FFT for Two-Tone Input Signal
ADS54J66 D010_SBAS717.gif
fIN1 = 370 MHz, fIN2 = 365 MHz, IMD = 81.7 dBFS,
each tone at –7 dBFS
Figure 11. FFT for Two-Tone Input Signal
ADS54J66 D012_SBAS717.gif
fIN1 = 470 MHz, fIN2 = 465 MHz, IMD = 76.7 dBFS,
each tone at –7 dBFS
Figure 13. FFT for Two-Tone Input Signal
ADS54J66 D014_SBAS717.gif
fIN1 = 185 MHz, fIN2 = 190 MHz
Figure 15. Intermodulation Distortion vs Input Amplitude
ADS54J66 D016_SBAS717.gif
fIN1 = 465 MHz, fIN2 = 470 MHz
Figure 17. Intermodulation Distortion vs Input Amplitude
ADS54J66 D018_SBAS717.gif
Figure 19. IL Spur vs Input Frequency
ADS54J66 D020_SBAS717.gif
fIN = 190 MHz, AIN = –1 dBFS
Figure 21. Signal-to-Noise Ratio vs
AVDD Supply and Temperature
ADS54J66 D022_SBAS717.gif
fIN = 370 MHz, AIN = –3 dBFS
Figure 23. Signal-to-Noise Ratio vs
AVDD Supply and Temperature
ADS54J66 D024_SBAS717.gif
fIN = 190 MHz, AIN = –1 dBFS
Figure 25. Signal-to-Noise Ratio vs
DVDD Supply and Temperature
ADS54J66 D026_SBAS717.gif
fIN = 370 MHz, AIN = –3 dBFS
Figure 27. Signal-to-Noise Ratio vs
DVDD Supply and Temperature
ADS54J66 D028_SBAS717.gif
fIN = 190 MHz, AIN = –1 dBFS
Figure 29. Signal-to-Noise Ratio vs
AVDD3V Supply and Temperature
ADS54J66 D030_SBAS717.gif
fIN = 370 MHz, AIN = –3 dBFS
Figure 31. Signal-to-Noise Ratio vs
AVDD3V Supply and Temperature
ADS54J66 D032_SBAS717.gif
fIN = 190 MHz
Figure 33. Performance vs Amplitude
ADS54J66 D034_SBAS717.gif
fIN = 190 MHz, AIN = –1 dBFS
Figure 35. Performance vs Clock Amplitude
ADS54J66 D036_SBAS717.gif
fIN = 190 MHz, AIN = –1 dBFS
Figure 37. Performance vs Clock Duty Cycle
ADS54J66 D038_SBAS717.gif
fIN = 190 MHz , AIN = –1 dBFS
SFDR = 49 dBc, fPSRR = 5 MHz, APSRR = 50 mVPP
Figure 39. Power-Supply Rejection Ratio FFT for
Test Signal on AVDD Supply
ADS54J66 D040_SBAS717.gif
fIN = 190 MHz , AIN = –1 dBFS
SFDR = 81 , fCMRR = 5 MHz, ACMRR = 50 mVPP
Figure 41. Common-Mode Rejection Ratio FFT
ADS54J66 D042_SBAS717.gif
Figure 43. Power vs Chip Clock

6.10 Typical Characteristics: Mode 2

low-pass or high-pass decimation-by-2 filter selected as per input frequency; typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = 85°C, ADC sampling frequency = 500 MSPS, 14-bit resolution, no decimation filter, 50% clock duty cycle, AVDD3V = 3 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, –1-dBFS differential input for IF ≤ 250 MHz, and –3-dBFS differential input for IF > 250 MHz (unless otherwise noted)
ADS54J66 D043_SBAS717.gif
fIN = 100 MHz, AIN = –1 dBFS,
SNR = 74.1 dBFS, SFDR = 98 dBc, SFDR = 100 dBc (non 23)
Figure 44. FFT for 100-MHz Input Signal
ADS54J66 D045_SBAS717.gif
fIN = 185 MHz, AIN = – 1 dBFS,
SNR = 73.2 dBFS, SFDR = 98 dBc, SFDR = 98 dBc (non 23)
Figure 46. FFT for 185-MHz Input Signal
ADS54J66 D044_SBAS717.gif
fIN = 150 MHz, AIN = –1 dBFS,
SNR = 73.8 dBFS, SFDR = 99 dBc, SFDR = 99 dBc (non 23)
Figure 45. FFT for 150-MHz Input Signal
ADS54J66 D046_SBAS717.gif
fIN = 230 MHz, AIN = –1 dBFS,
SNR = 72.4 dBFS, SFDR = 91 dBc, SFDR = 98 dBc (non 23)
Figure 47. FFT for 230-MHz Input Signal

6.11 Typical Characteristics: Mode 0

low-pass decimation-by-2 filter selected, complex FFT plotted, mixer frequency 125 MHz; typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = 85°C, ADC sampling frequency = 500 MSPS, 14-bit resolution, no decimation filter, 50% clock duty cycle, AVDD3V = 3 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, –1-dBFS differential input for IF ≤ 250 MHz, and –3-dBFS differential input for IF > 250 MHz (unless otherwise noted)
ADS54J66 D047_SBAS717.gif
fIN = 270 MHz, AIN = –3 dBFS,
SNR = 69.5 dBFS, SFDR = 83 dBc, SFDR = 87 dBc (non 23)
Figure 48. FFT for 270-MHz Input Signal
ADS54J66 D049_SBAS717.gif
fIN = 470 MHz, AIN = –3 dBFS,
SNR = 66.3 dBFS, SFDR = 75 dBc, SFDR = 75 dBc (non 23)
Figure 50. FFT for 470-MHz Input Signal
ADS54J66 D048_SBAS717.gif
fIN = 370 MHz, AIN = –3 dBFS,
SNR = 68.1 dBFS, SFDR = 82 dBc, SFDR = 82 dBc (non 23)
Figure 49. FFT for 370-MHz Input Signal