SBAS811 January 2017 ADS7029-Q1
PRODUCTION DATA.
| MIN | MAX | UNIT | |
|---|---|---|---|
| AVDD to GND | –0.3 | 3.9 | V |
| DVDD to GND | –0.3 | 3.9 | V |
| AINP to GND | –0.3 | AVDD + 0.3 | V |
| AINM to GND | –0.3 | 0.3 | V |
| Digital input voltage to GND | –0.3 | DVDD + 0.3 | V |
| Storage temperature, Tstg | –60 | 150 | °C |
| VALUE | UNIT | |||
|---|---|---|---|---|
| V(ESD) | Electrostatic discharge | Human-body model (HBM), per AEC Q100-002(1) | ±2000 | V |
| Charged-device model (CDM), per AEC Q100-011 | ±1000 | |||
| MIN | NOM | MAX | UNIT | ||
|---|---|---|---|---|---|
| AVDD | Analog supply voltage range | 2.35 | 3.6 | V | |
| DVDD | Digital supply voltage range | 1.65 | 3.6 | V | |
| TA | Operating free-air temperature | –40 | 125 | °C | |
| THERMAL METRIC(1) | ADS7029-Q1 | UNIT | |
|---|---|---|---|
| DCU (VSSOP) | |||
| 8 PINS | |||
| RθJA | Junction-to-ambient thermal resistance | 181.8 | °C/W |
| RθJC(top) | Junction-to-case (top) thermal resistance | 50.8 | °C/W |
| RθJB | Junction-to-board thermal resistance | 73.9 | °C/W |
| ψJT | Junction-to-top characterization parameter | 1.0 | °C/W |
| ψJB | Junction-to-board characterization parameter | 73.9 | °C/W |
| RθJC(bot) | Junction-to-case (bottom) thermal resistance | N/A | °C/W |
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
|---|---|---|---|---|---|---|---|
| ANALOG INPUT | |||||||
| Full-scale input voltage span(1) | 0 | AVDD | V | ||||
| Absolute input voltage range | AINP to GND | –0.1 | AVDD + 0.1 | V | |||
| AINM to GND | –0.1 | 0.1 | |||||
| CS | Sampling capacitance | 15 | pF | ||||
| SYSTEM PERFORMANCE | |||||||
| Resolution | 8 | Bits | |||||
| NMC | No missing codes | 8 | Bits | ||||
| INL | Integral nonlinearity | AVDD = 3 V | –0.5 | ±0.25 | 0.5 | LSB(2) | |
| DNL | Differential nonlinearity | AVDD = 3 V | –0.4 | ±0.2 | 0.4 | LSB | |
| EO | Offset error | ±0.5 | LSB | ||||
| dVOS/dT | Offset error drift with temperature | ±25 | ppm/°C | ||||
| EG | Gain error | AVDD = 3 V | ±0.2 | %FS | |||
| Gain error drift with temperature | No calibration | ±25 | ppm/°C | ||||
| SAMPLING DYNAMICS | |||||||
| tACQ | Acquisition time | 120 | ns | ||||
| Maximum throughput rate | 32-MHz SCLK, AVDD = 2.35 V to 3.6 V | 2 | MHz | ||||
| DYNAMIC CHARACTERISTICS | |||||||
| SNR | Signal-to-noise ratio(4) | fIN = 2 kHz, AVDD = 3 V | 48.5 | 49 | dB | ||
| THD | Total harmonic distortion(4)(3) | fIN = 2 kHz, AVDD = 3 V | –70 | dB | |||
| SINAD | Signal-to-noise and distortion(4) | fIN = 2 kHz, AVDD = 3 V | 48.5 | 49 | dB | ||
| SFDR | Spurious-free dynamic range(4) | fIN = 2 kHz, AVDD = 3 V | 75 | dB | |||
| BW(fp) | Full-power bandwidth | At –3 dB, AVDD = 3 V | 25 | MHz | |||
| DIGITAL INPUT/OUTPUT (CMOS Logic Family) | |||||||
| VIH | High-level input voltage(5) | 0.65 × DVDD | DVDD + 0.3 | V | |||
| VIL | Low-level input voltage(5) | –0.3 | 0.35 × DVDD | V | |||
| VOH | High-level output voltage(5) | At Isource = 500 µA | 0.8 × DVDD | DVDD | V | ||
| At Isource = 2 mA | DVDD – 0.45 | DVDD | |||||
| VOL | Low-level output voltage(5) | At Isink = 500 µA | 0 | 0.2 × DVDD | V | ||
| At Isink = 2 mA | 0 | 0.45 | |||||
| POWER-SUPPLY REQUIREMENTS | |||||||
| AVDD | Analog supply voltage | 2.35 | 3 | 3.6 | V | ||
| DVDD | Digital I/O supply voltage | 1.65 | 3 | 3.6 | V | ||
| IAVDD | Analog supply current | At 2 MSPS with AVDD = 3 V | 335 | 370 | µA | ||
| IDVDD | Digital supply current | AVDD = 3 V, no load, no transitions | 10 | µA | |||
| PD | Power dissipation | At 2 MSPS with AVDD = 3 V | 1.005 | 1.11 | mW | ||
| MIN | TYP | MAX | UNIT | ||
|---|---|---|---|---|---|
| tACQ | Acquisition time | 120 | ns | ||
| fSCLK | SCLK frequency | 0.016 | 24 | MHz | |
| tSCLK | SCLK period | 41.67 | ns | ||
| tPH_CK | SCLK high time | 0.45 | 0.55 | tSCLK | |
| tPL_CK | SCLK low time | 0.45 | 0.55 | tSCLK | |
| tPH_CS | CS high time | 30 | ns | ||
| tSU_CSCK | Setup time: CS falling to SCLK falling | 12 | ns | ||
| tD_CKCS | Delay time: last SCLK falling to CS rising | 10 | ns | ||
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| fTHROUGHPUT | Throughput | 2 | MSPS | |||
| tCYCLE | Cycle time | 0.5 | µs | |||
| tCONV | Conversion time | 8.5 × tSCLK + tSU_CSCK | ns | |||
| tDV_CSDO | Delay time: CS falling to data enable | 10 | ns | |||
| tD_CKDO | Delay time: SCLK falling to (next) data valid on DOUT | AVDD = 2.35 V to 3.6 V | 25 | ns | ||
| tDZ_CSDO | Delay time: CS rising to DOUT going to tri-state | 5 | ns | |||
Figure 1. Timing Diagram
| SNR = 49.65 dB, THD = –73.26 dB, fIN = 2 kHz, AVDD = 3 V |
| fIN = 2 kHz, AVDD = 3 V |
| fIN = 2 kHz |
| fIN = 2 kHz, AVDD = 3 V |
| fIN = 2 kHz, AVDD = 3 V |
| AVDD = 2.35 V |
| AVDD = 3 V |
| AVDD = 3 V |
| AVDD = 3 V |
| AVDD = 3 V |
| fSample = 2 MSPS |
| AVDD = DVDD = 3.3 V |
| AVDD = DVDD = 3.3 V |
| SNR = 49.19 dB, THD = –71.25 dB, fIN = 250 kHz, AVDD = 3 V |
| AVDD = 3 V |
| fIN = 2 kHz, AVDD = 3 V |
| AVDD = 3 V |
| fIN = 2 kHz, AVDD = 3 V |
| Mean code = 127, sigma = 0, AVDD = 3 V |
| AVDD = 2.35 V |
| AVDD = 3 V |
| AVDD = 3 V |
| AVDD = DVDD = 3.3 V |
| AVDD = DVDD = 3.3 V |