SBAS523D October   2010  – September 2017 ADS7223 , ADS7263 , ADS8363

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics: General
    6. 7.6  Electrical Characteristics: ADS8363
    7. 7.7  Electrical Characteristics: ADS7263
    8. 7.8  Electrical Characteristics: ADS7223
    9. 7.9  Switching Characteristics
    10. 7.10 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog
        1. 8.3.1.1 Analog Inputs
        2. 8.3.1.2 Analog-to-Digital Converters (ADCs)
        3. 8.3.1.3 CONVST
        4. 8.3.1.4 CLOCK
        5. 8.3.1.5 RESET
        6. 8.3.1.6 REFIOx
      2. 8.3.2 Digital
        1. 8.3.2.1 Mode Selection Pin M0 and M1
        2. 8.3.2.2 Half-Clock Mode (Default Mode After Power-Up and Reset)
        3. 8.3.2.3 Full-Clock Mode (Allowing Conversion and Data Readout Within 1 µs, Supported In Dual Output Modes)
        4. 8.3.2.4 2-Bit Counter
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Down Modes and Reset
        1. 8.4.1.1 Power-Down Mode
        2. 8.4.1.2 Sleep Mode
        3. 8.4.1.3 Auto-Sleep Mode
        4. 8.4.1.4 Reset
    5. 8.5 Programming
      1. 8.5.1 Read Data Input (RD)
      2. 8.5.2 Serial Data Outputs (SDOx)
        1. 8.5.2.1 Mode I
        2. 8.5.2.2 Mode II (Half-Clock Mode Only)
        3. 8.5.2.3 Special Read Mode II (Half-Clock Mode Only)
        4. 8.5.2.4 Mode III
        5. 8.5.2.5 Fully-Differential Mode IV (Half-Clock Mode Only)
        6. 8.5.2.6 Special Mode IV (Half-Clock Mode Only)
      3. 8.5.3 Programming the Reference DAC
    6. 8.6 Register Maps
      1. 8.6.1 Configuration (Config) Register
      2. 8.6.2 REFDAC1 and REFDAC2 Registers
      3. 8.6.3 Sequencer/FIFO (SEQFIFO) Register
      4. 8.6.4 Reference and Common-Mode Selection (REFCM) Register
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 ADS8361 Compatibility
        1. 9.1.1.1 Pinout
        2. 9.1.1.2 SDI versus A0
        3. 9.1.1.3 Internal Reference
        4. 9.1.1.4 Timing
        5. 9.1.1.5 RD
        6. 9.1.1.6 CONVST
      2. 9.1.2 Minimum Configuration Example
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Grounding
      2. 11.1.2 Digital Interface
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Related Links
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

11 Layout

11.1 Layout Guidelines

For optimum performance, care must be taken with the physical layout of the ADS8363, ADS7263, and ADS7223 circuitry, particularly if the device is used at the maximum throughput rate. In this case, a fixed phase relationship is recommended between CLOCK and CONVST.

Additionally, the high-performance SAR architecture is sensitive to glitches or sudden changes on the power supply, reference, ground connections, and digital inputs that occur just before latching the output of the internal analog comparator. Therefore, during an operation of an n-bit SAR converter, there are n windows in which large external transient voltages (glitches) can affect the conversion result. Such glitches can originate from switching power supplies, nearby digital logic, or high-power devices. The degree of impact depends on the reference voltage, layout, and the actual timing of the external event.

With this possibility in mind, power to the device must be clean and well-bypassed. A 1-µF ceramic bypass capacitor must be placed at each supply pin (connected to the corresponding ground pin) as close to the device as possible.

If the reference voltage is external, the operational amplifier must be able to drive the 22-µF capacitor without oscillation. A series resistor between the driver output and the capacitor may be required. To minimize any code-dependent voltage drop on this path, a small value must be used for this resistor (10 Ω max). TI's REF50xx family is able to directly drive such a capacitive load.

11.1.1 Grounding

The AGND, RGND, and DGND pins must be connected to a clean ground reference. All connections must be kept as short as possible to minimize the inductance of these paths. Using vias connecting the pads directly to the ground plane is recommended. In designs without ground planes, the ground trace must be kept as wide as possible. Avoid connections that are close to the grounding point of a microcontroller or digital signal processor.

Depending on the circuit density of the board, placement of the analog and digital components, and the related current loops, a single solid ground plane for the entire printed circuit board (PCB) or a dedicated analog ground area can be used. In case of a separated analog ground area, ensure a low-impedance connection between the analog and digital ground of the ADC by placing a bridge underneath (or next) to the ADC (see Figure 49). Otherwise, even short undershoots on the digital interface with a value of less than –300 mV can lead to conduction of ESD diodes, causing current flow through the substrate and degrading the analog performance.

During the layout of the PCB, care must be taken to avoid any return currents crossing any sensitive analog areas or signals. No signal must exceed the limit of –300 mV with respect to the corresponding (AGND or DGND) ground plane.

11.1.2 Digital Interface

To further optimize performance of the device, a series resistor of between 10 Ω to 100 Ω can be used on each digital pin of the device. In this way, the slew rate of the input and output signals is reduced, limiting the noise injection from the digital interface.

11.2 Layout Example

ADS8363 ADS7263 ADS7223 ai_layout_bas523.gif Figure 49. Optimized Layout Recommendation