SBAS523D October   2010  – September 2017 ADS7223 , ADS7263 , ADS8363

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics: General
    6. 7.6  Electrical Characteristics: ADS8363
    7. 7.7  Electrical Characteristics: ADS7263
    8. 7.8  Electrical Characteristics: ADS7223
    9. 7.9  Switching Characteristics
    10. 7.10 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog
        1. 8.3.1.1 Analog Inputs
        2. 8.3.1.2 Analog-to-Digital Converters (ADCs)
        3. 8.3.1.3 CONVST
        4. 8.3.1.4 CLOCK
        5. 8.3.1.5 RESET
        6. 8.3.1.6 REFIOx
      2. 8.3.2 Digital
        1. 8.3.2.1 Mode Selection Pin M0 and M1
        2. 8.3.2.2 Half-Clock Mode (Default Mode After Power-Up and Reset)
        3. 8.3.2.3 Full-Clock Mode (Allowing Conversion and Data Readout Within 1 µs, Supported In Dual Output Modes)
        4. 8.3.2.4 2-Bit Counter
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Down Modes and Reset
        1. 8.4.1.1 Power-Down Mode
        2. 8.4.1.2 Sleep Mode
        3. 8.4.1.3 Auto-Sleep Mode
        4. 8.4.1.4 Reset
    5. 8.5 Programming
      1. 8.5.1 Read Data Input (RD)
      2. 8.5.2 Serial Data Outputs (SDOx)
        1. 8.5.2.1 Mode I
        2. 8.5.2.2 Mode II (Half-Clock Mode Only)
        3. 8.5.2.3 Special Read Mode II (Half-Clock Mode Only)
        4. 8.5.2.4 Mode III
        5. 8.5.2.5 Fully-Differential Mode IV (Half-Clock Mode Only)
        6. 8.5.2.6 Special Mode IV (Half-Clock Mode Only)
      3. 8.5.3 Programming the Reference DAC
    6. 8.6 Register Maps
      1. 8.6.1 Configuration (Config) Register
      2. 8.6.2 REFDAC1 and REFDAC2 Registers
      3. 8.6.3 Sequencer/FIFO (SEQFIFO) Register
      4. 8.6.4 Reference and Common-Mode Selection (REFCM) Register
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 ADS8361 Compatibility
        1. 9.1.1.1 Pinout
        2. 9.1.1.2 SDI versus A0
        3. 9.1.1.3 Internal Reference
        4. 9.1.1.4 Timing
        5. 9.1.1.5 RD
        6. 9.1.1.6 CONVST
      2. 9.1.2 Minimum Configuration Example
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Grounding
      2. 11.1.2 Digital Interface
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Related Links
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • Eight Pseudo- or Four Fully-Differential Inputs
  • Simultaneous Sampling of Two Channels
  • Excellent AC Performance:
    • SNR:
      93 dB (ADS8363)
      85 dB (ADS7263)
      73 dB (ADS7223)
    • THD:
      –98 dB (ADS8363)
      –92 dB (ADS7263)
      –86 dB (ADS7223)
  • Dual Programmable and Buffered 2.5-V Reference Allows:
    • Two Different Input Voltage Range Settings
    • Two-Level PGA Implementation
  • Programmable Auto-Sequencer
  • Integrated Data Storage (up to 4 per channel) for Oversampling Applications
  • 2-Bit Counter for Safety Applications
  • Fully Specified Over the Extended Industrial Temperature Range: –40°C to +125°C

2 Applications

  • Motor Control: Current and Position Measurement including Safety Applications
  • Power Quality Measurement
  • Three-Phase Power Control
  • Programmable Logic Controllers
  • Industrial Automation
  • Protection Relays

3 Description

The ADS8363 is a dual, 16-bit, 1-MSPS analog-to-digital converter (ADC) with eight pseudo- or four fully-differential input channels grouped into two pairs for simultaneous signal acquisition. The analog inputs are maintained differentially to the input of the ADC. The input multiplexer can be used in either pseudo-differential mode, supporting up to four channels per ADC (4x2), or in fully-differential mode that allows to convert up to two inputs per ADC (2x2). The ADS7263 is a 14-bit version and the ADS7223 is a 12-bit version of the ADS8363.

The ADS8363, ADS7263, and ADS7223 offer two programmable reference outputs, flexible supply voltage ranges, a programmable auto-sequencer, data storage of up to four conversion results per channel, and several power-down features.

All devices are offered in a 5-mm x 5-mm, 32-pin VQFN package.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
ADSxxx3 VQFN (32) 5.00 mm x 5.00 mm
  1. For all available packages, see the package option addendum at the end of the data sheet.

Functional Block Diagram

ADS8363 ADS7263 ADS7223 front_pg_fbd_bas523.gif

4 Revision History

Changes from C Revision (January 2017) to D Revision

  • Changed operating temperature from 85°C to 125°C in Recommended Operating Conditions tableGo

Changes from B Revision (January 2011) to C Revision

  • Added Device Information table, ESD Ratings table, Recommended Operating Conditions table, Feature Description section, Device Functional Modes section, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information sectionGo
  • Changed ADS8363/7263/7223 to ADS8363, ADS7263, and ADS7223 throughout documentGo
  • Changed Description section: changed last sentence of first paragraph and last paragraph Go
  • Changed Device Comparison Table titleGo
  • Changed Pin Configuration and Functions section titleGo
  • Changed footnote of Figure 1 and 1 for clarityGo
  • Changed second and third columns of Midscale – 1 LSB row in Output Data Format table: changed –VREF to –2VREF in column 2, changed last two voltage values in column 3Go
  • Changed footnote of Figure 31 Go
  • Changed footnote of Figure 32 Go
  • Changed footnote of Figure 33 Go
  • Changed footnote of Figure 34 Go
  • Changed footnote of Figure 35 Go
  • Changed footnote of Figure 36 Go
  • Changed footnote of Figure 38 Go
  • Changed footnote of Figure 40 Go
  • Changed 1FFh to 3FFh in bits 9-0 description of REFDAC1 Control Register and REFDAC2 Control RegisterGo

Changes from A Revision (December, 2010) to B Revision

Changes from * Revision (October, 2010) to A Revision