SBAS523D October 2010 – September 2017 ADS7223 , ADS7263 , ADS8363
PRODUCTION DATA.
| PIN | TYPE(1) | DESCRIPTION | |
|---|---|---|---|
| NAME | NO. | ||
| AGND | 12, 30 | P | Analog ground. Connect to analog ground plane. |
| AVDD | 13, 29 | P | Analog power supply, 2.7 V to 5.5 V. Decouple to AGND with a 1-μF ceramic capacitor. |
| BUSY | 23 | DO | Converter busy indicator. BUSY goes high when the inputs are in hold mode and returns to low after the conversion is complete. |
| CHA0N/CHA0 | 8 | AI | Fully-differential inverting analog input channel A1 or pseudo-differential input A0 |
| CHA0P/CHA1 | 7 | AI | Fully-differential noninverting analog input channel A1 or pseudo-differential input A1 |
| CHA1N/CHA2 | 6 | AI | Fully-differential inverting analog input channel A1 or pseudo-differential input A2 |
| CHA1P/CHA3 | 5 | AI | Fully-differential noninverting analog input channel A1 or pseudo-differential input A3 |
| CHB0N/CHB0 | 4 | AI | Fully-differential inverting analog input channel B0 or pseudo-differential input B0 |
| CHB0P/CHB1 | 3 | AI | Fully-differential noninverting analog input channel B0 or pseudo-differential input B1 |
| CHB1N/CHB2 | 2 | AI | Fully-differential inverting analog input channel B1 or pseudo-differential input B2 |
| CHB1P/CHB3 | 1 | AI | Fully-differential noninverting analog input channel B1 or pseudo-differential input B3 |
| CLOCK | 22 | DI | External clock input. The range is 0.5 MHz to 20 MHz in half-clock mode, or 1 MHz to 40 MHz in full-clock mode. |
| CMA | 31 | AI | Common-mode voltage input for channels Ax (in pseudo-differential mode only). |
| CMB | 32 | AI | Common-mode voltage input for channels Bx (in pseudo-differential mode only). |
| CONVST | 19 | DI | Conversion start. The ADC switches from sample into hold mode on the rising edge of CONVST. Thereafter, the conversion starts with the next rising edge of the CLOCK pin. |
| CS | 21 | DI | Chip select. When this pin is low, the SDOx, SDI, and RD pins are active; when this pin is high, the SDOx outputs are 3-stated, and the SDI and RD inputs are ignored. |
| DGND | 28 | P | Digital ground. Connect to digital ground plane. |
| DVDD | 27 | P | Digital supply, 2.3 V to 5.5 V. Decouple to DGND with a 1-μF ceramic capacitor. |
| M0 | 17 | DI | Mode pin 0. Selects analog input channel mode (see Table 5). |
| M1 | 16 | DI | Mode pin 1. Selects the digital output mode (see Table 5). |
| NC | 14, 15, 26 | NC | This pin is not internally connected. |
| RD | 20 | DI | Read data. Synchronization pulse for the SDOx outputs and SDI input. RD only triggers when CS is low. |
| REFIO1 | 9 | AIO | Reference voltage input/output 1. A ceramic capacitor of 22 µF connected to RGND is required. |
| REFIO2 | 10 | AIO | Reference voltage input/output 2. A ceramic capacitor of 22 µF connected to RGND is required. |
| RGND | 11 | P | Reference ground. Connect to analog ground plane with a dedicated via. |
| SDI | 18 | DI | Serial data input. This pin is used to set up of the internal registers, and can also be used in ADS8361-compatible manner. The data on SDI are ignored when CS is high. |
| SDOA | 25 | DO | Serial data output for converter A. 3-state when CS is high. |
| SDOB | 24 | DO | Serial data output for converter B. Active only if M1 is low. 3-state when CS is high. |