SBAS523D October   2010  – September 2017 ADS7223 , ADS7263 , ADS8363

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics: General
    6. 7.6  Electrical Characteristics: ADS8363
    7. 7.7  Electrical Characteristics: ADS7263
    8. 7.8  Electrical Characteristics: ADS7223
    9. 7.9  Switching Characteristics
    10. 7.10 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog
        1. 8.3.1.1 Analog Inputs
        2. 8.3.1.2 Analog-to-Digital Converters (ADCs)
        3. 8.3.1.3 CONVST
        4. 8.3.1.4 CLOCK
        5. 8.3.1.5 RESET
        6. 8.3.1.6 REFIOx
      2. 8.3.2 Digital
        1. 8.3.2.1 Mode Selection Pin M0 and M1
        2. 8.3.2.2 Half-Clock Mode (Default Mode After Power-Up and Reset)
        3. 8.3.2.3 Full-Clock Mode (Allowing Conversion and Data Readout Within 1 µs, Supported In Dual Output Modes)
        4. 8.3.2.4 2-Bit Counter
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Down Modes and Reset
        1. 8.4.1.1 Power-Down Mode
        2. 8.4.1.2 Sleep Mode
        3. 8.4.1.3 Auto-Sleep Mode
        4. 8.4.1.4 Reset
    5. 8.5 Programming
      1. 8.5.1 Read Data Input (RD)
      2. 8.5.2 Serial Data Outputs (SDOx)
        1. 8.5.2.1 Mode I
        2. 8.5.2.2 Mode II (Half-Clock Mode Only)
        3. 8.5.2.3 Special Read Mode II (Half-Clock Mode Only)
        4. 8.5.2.4 Mode III
        5. 8.5.2.5 Fully-Differential Mode IV (Half-Clock Mode Only)
        6. 8.5.2.6 Special Mode IV (Half-Clock Mode Only)
      3. 8.5.3 Programming the Reference DAC
    6. 8.6 Register Maps
      1. 8.6.1 Configuration (Config) Register
      2. 8.6.2 REFDAC1 and REFDAC2 Registers
      3. 8.6.3 Sequencer/FIFO (SEQFIFO) Register
      4. 8.6.4 Reference and Common-Mode Selection (REFCM) Register
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 ADS8361 Compatibility
        1. 9.1.1.1 Pinout
        2. 9.1.1.2 SDI versus A0
        3. 9.1.1.3 Internal Reference
        4. 9.1.1.4 Timing
        5. 9.1.1.5 RD
        6. 9.1.1.6 CONVST
      2. 9.1.2 Minimum Configuration Example
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Grounding
      2. 11.1.2 Digital Interface
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Related Links
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Supply voltage, AVDD to AGND or DVDD to DGND –0.3 6 V
Supply voltage, DVDD to AVDD 1.2 × AVDD(2) V
Analog and reference input voltage with respect to AGND AGND – 0.3 AVDD + 0.3 V
Digital input voltage with respect to DGND DGND – 0.3 DVDD + 0.3 V
Ground voltage difference |AGND-DGND| 0.3 V
Input current to any pin except supply pins –10 10 mA
Maximum virtual junction temperature, TJ 150 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Exceeding the specified limit causes an increase of the DVDD leakage current and leads to malfunction of the device.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
AVDD Analog supply voltage 5 V
DVDD Digital supply voltage 3.3 V
Operating temperature –40 125 °C

7.4 Thermal Information

THERMAL METRIC(1) ADS8363, ADS7263, ADS7223 UNIT
RHB (VQFN)
32 PINS
RθJA Junction-to-ambient thermal resistance 33.3 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 29.5 °C/W
RθJB Junction-to-board thermal resistance 7.3 °C/W
ψJT Junction-to-top characterization parameter 0.2 °C/W
ψJB Junction-to-board characterization parameter 7.4 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 0.9 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

7.5 Electrical Characteristics: General

All minimum and maximum specifications at TA = –40°C to +125°C, specified supply voltage range, VREF = 2.5 V (int), and tDATA = 1 MSPS (unless otherwise noted). Typical values are at TA = +25°C, AVDD = 5 V, and DVDD = 3.3 V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUT
FSR Full-scale input range (CHxxP – CHxxN) or CHxx to CMx –VREF +VREF V
VIN Absolute input voltage CHxxx to AGND –0.1 AVDD + 0.1 V
CIN Input capacitance CHxxx to AGND 45 pF
CID Differential input capacitance 22.5 pF
IIL Input leakage current –16 16 nA
PSRR Power-supply rejection ratio AVDD = 5.5 V 75 dB
SAMPLING DYNAMICS
tCONV Conversion time per ADC Half-clock mode 17.5 tCLK
Full-clock mode 35
tACQ Acquisition time Half-clock mode 2 tCLK
Full-clock Mode 4
fDATA Data rate 25 1000 kSPS
tA Aperture delay 6 ns
tA match ADC to ADC 50 ps
tAJIT Aperture jitter 50 ps
fCLK Clock frequency Half-clock mode 0.5 20 MHz
Full-clock mode 1 40
tCLK Clock period Half-clock mode 50 2000 ns
Full-clock mode 25 1000
INTERNAL VOLTAGE REFERENCE
Resolution Reference output DAC resolution 10 Bits
VREFOUT Reference output voltage Over 20% to 100% DAC range 0.2VREFOUT VREFOUT V
REFIO1, DAC = 3FFh 2.485 2.500 2.515
REFIO2, DAC = 3FFh 2.480 2.500 2.520
dVREFOUT/dT Reference voltage drift ±10 ppm/°C
DNLDAC DAC differential linearity error –4 ±1 4 LSB
INLDAC DAC integral linearity error –4 ±0.5 4 LSB
VOSDAC DAC offset error VREFOUT = 0.5 V –4 ±1 4 LSB
PSRR Power-supply rejection ratio 73 dB
IREFOUT Reference output dc current –2 +2 mA
IREFSC Reference output short-circuit current(1) 50 mA
tREFON Reference output settling time CREF = 22 μF 8 ms
VOLTAGE REFERENCE INPUT
VREF Reference input voltage range 0.5 2.5 2.525 V
IREF Reference input current 50 μA
CREF External ceramic reference capacitance 22 μF
DIGITAL INPUTS(2)
IIN Input current VIN = DVDD to DGND –50 +50 nA
CIN Input capacitance 5 pF
Logic family CMOS with Schmitt-Trigger
VIH High-level input voltage DVDD = 4.5 V to 5.5 V 0.7DVDD DVDD + 0.3 V
VIL Low-level input voltage DVDD = 4.5 V to 5.5 V –0.3 0.3DVDD V
Logic family LVCMOS
VIH High-level input voltage DVDD = 2.3 V to 3.6 V 2 DVDD + 0.3 V
VIL Low-level input voltage DVDD = 2.3 V to 3.6 V –0.3 0.8 V
DIGITAL OUTPUTS(2)
COUT Output capacitance 5 pF
CLOAD Load capacitance 30 pF
Logic family CMOS
VOH High-level output voltage DVDD = 4.5 V, IOH = –100 µA 4.44 V
VOL Low-level output voltage DVDD = 4.5 V, IOH = +100 µA 0.5 V
Logic family LVCMOS
VOH High-level output voltage DVDD = 2.3 V, IOH = –100 µA DVDD – 0.2 V
VOL Low-level output voltage DVDD = 2.3 V, IOH = +100 µA 0.2 V
POWER SUPPLY
AVDD Analog supply voltage AVDD to AGND, half-clock mode 2.7 5.0 5.5 V
AVDD to AGND, full-clock mode 4.5 5.0 5.5
DVDD Digital supply voltage 3-V and 3.3-V levels 2.3 2.5 3.6 V
5-V levels, half-clock mode only 4.5 5.0 5.5
AIDD Analog supply current AVDD = 3.6 V 12.0 16.0 mA
AVDD = 5.5 V 15.0 20.0
AVDD = 3.6 V, sleep and auto-sleep modes 0.8 1.2
AVDD = 5.5 V, sleep and auto-sleep modes 0.9 1.4
Power-down mode 0.005
DIDD Digital supply current DVDD = 3.6 V, CLOAD = 10 pF 1.1 2.5 mA
DVDD = 5.5 V, CLOAD = 10 pF 3 6
PD Power dissipation (normal operation) AVDD = DVDD = 3.6 V 47.2 66.6 mW
AVDD = 5.5 V, DVDD = 3.6 V 86.5 117.0
(1) Reference output current is not internally limited.
(2) Specified by design; not production tested.

7.6 Electrical Characteristics: ADS8363

All minimum and maximum specifications at TA = –40°C to +125°C, specified supply voltage range, VREF = 2.5 V (int), and tDATA = 1 MSPS (unless otherwise noted). Typical values are at TA = +25°C, AVDD = 5 V, and DVDD = 3.3 V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
RESOLUTION
Resolution 16 Bits
DC ACCURACY
INL Integral nonlinearity Half-clock mode –3 ±1.2 +3 LSB
Full-clock mode –4 ±1.5 +4
DNL Differential nonlinearity Half-clock mode –0.99 ±0.6 +2 LSB
Full-clock mode –1.5 ±0.8 +3
VOS Input offset error –2 ±0.2 +2 mV
VOS match ADC to ADC –1 ±0.1 +1 mV
dVOS/dT Input offset thermal drift 1 μV/°C
GERR Gain error Referenced to the voltage at REFIOx –0.1% ±0.01% +0.1%
GERR match ADC to ADC –0.1% ±0.005% +0.1%
GERR/dT Gain error thermal drift Referenced to the voltage at REFIOx 1 ppm/°C
CMRR Common-mode rejection ratio Both ADCs, dc to 100 kHz 92 dB
AC ACCURACY
SINAD Signal-to-noise + distortion VIN = 5 VPP at 10 kHz 89 92 dB
SNR Signal-to-noise ratio VIN = 5 VPP at 10 kHz 90 93 dB
THD Total harmonic distortion VIN = 5 VPP at 10 kHz –98 –90 dB
SFDR Spurious-free dynamic range VIN = 5 VPP at 10 kHz 90 100 dB

7.7 Electrical Characteristics: ADS7263

All minimum and maximum specifications at TA = –40°C to +125°C, specified supply voltage range, VREF = 2.5 V (int), and tDATA = 1 MSPS (unless otherwise noted). Typical values are at TA = +25°C, AVDD = 5 V, and DVDD = 3.3 V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
RESOLUTION
Resolution 14 Bits
DC ACCURACY
INL Integral nonlinearity –1 ±0.4 +1 LSB
DNL Differential nonlinearity –0.5 ±0.2 +1 LSB
VOS Input offset error –2 ±0.2 +2 mV
VOS match ADC to ADC –1 ±0.1 +1 mV
dVOS/dT Input offset thermal drift 1 μV/°C
GERR Gain error Referenced to the voltage at REFIOx –0.1% ±0.01% +0.1%
GERR match ADC to ADC –0.1% ±0.005% +0.1%
GERR/dT Gain error thermal drift Referenced to the voltage at REFIOx 1 ppm/°C
CMRR Common-mode rejection ratio Both ADCs, dc to 100 kHz 92 dB
AC ACCURACY
SINAD Signal-to-noise + distortion VIN = 5 VPP at 10 kHz 82 84 dB
SNR Signal-to-noise ratio VIN = 5 VPP at 10 kHz 84 85 dB
THD Total harmonic distortion VIN = 5 VPP at 10 kHz –92 –88 dB
SFDR Spurious-free dynamic range VIN = 5 VPP at 10 kHz 88 92 dB

7.8 Electrical Characteristics: ADS7223

All minimum and maximum specifications at TA = –40°C to +125°C, specified supply voltage range, VREF = 2.5 V (int), and tDATA = 1 MSPS (unless otherwise noted). Typical values are at TA = +25°C, AVDD = 5 V, and DVDD = 3.3 V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
RESOLUTION
Resolution 12 Bits
DC ACCURACY
INL Integral nonlinearity –0.5 ±0.2 +0.5 LSB
DNL Differential nonlinearity –0.5 ±0.1 +0.5 LSB
VOS Input offset error –2 ±0.2 +2 mV
VOS match ADC to ADC –1 ±0.1 +1 mV
dVOS/dT Input offset thermal drift 1 μV/°C
GERR Gain error Referenced to the voltage at REFIOx –0.1% ±0.01% +0.1%
GERR match ADC to ADC –0.1% ±0.005% +0.1%
GERR/dT Gain error thermal drift Referenced to the voltage at REFIOx 1 ppm/°C
CMRR Common-mode rejection ratio Both ADCs, dc to 100 kHz 92 dB
AC ACCURACY
SINAD Signal-to-noise + distortion VIN = 5 VPP at 10 kHz 71 72 dB
SNR Signal-to-noise ratio VIN = 5 VPP at 10 kHz 72 73 dB
THD Total harmonic distortion VIN = 5 VPP at 10 kHz –86 –84 dB
SFDR Spurious-free dynamic range VIN = 5 VPP at 10 kHz 84 86 dB

7.9 Switching Characteristics(1)

Over the recommended operating free-air temperature range of –40°C to +125°C, and DVDD = 2.3 V to 5.5 V (unless otherwise noted).
MIN MAX UNIT
tDATA Data throughput, fCLK = max 1 μs
tCONV Conversion time Half-clock mode 17.5 tCLK
Full-clock mode 35
tACQ Acquisition time 100 ns
fCLK CLOCK frequency Half-clock mode 0.5 20 MHz
Full-clock mode 1 40
tCLK CLOCK period Half-clock mode 50 2000 ns
Full-clock mode 25 1000
tCLKL CLOCK low time 11.25 ns
tCLKH CLOCK high time 11.25 ns
t1 CONVST rising edge to first CLOCK rising edge 12 ns
t2 CONVST high time 10 ns
Half-clock mode: timing modes II and IV only 1 tCLK
t3 RD high time, half-clock mode: timing modes II, IV, SII, and SIV only 1 tCLK
tS1 RD high to CLOCK falling edge setup time 5 ns
tH1 RD high to CLOCK falling edge hold time 5 ns
tS2 Input data to CLOCK falling edge setup time 5 ns
tH2 Input data to CLOCK falling edge hold time 4 ns
tD1 CONVST rising edge to BUSY high delay(2) 2.3 V < DVDD < 3.6 V 19 ns
4.5 V < DVDD < 5.5 V 16
tD2 CLOCK 18th falling edge (half-clock mode) or 24th rising edge (full-clock mode) to BUSY low delay 2.3 V < DVDD < 3.6 V 25 ns
4.5 V < DVDD < 5.5 V 20
tD3 CLOCK rising edge to next data valid delay Half-clock mode,
2.3 V < DVDD < 3.6 V		 14 ns
Half-clock mode,
4.5 V < DVDD < 5.5 V		 12
tH3 Output data to CLOCK rising edge hold time, half-clock mode 3 ns
tD4 CLOCK falling edge to next data valid delay, full-clock mode 19 ns
tH4 Output data to CLOCK falling edge hold time, full-clock mode 7 ns
tD5 RD falling edge to first data valid 2.3 V < DVDD < 3.6 V 16 ns
4.5 V < DVDD < 5.5 V 12
tD6 CS rising edge to SDOx 3-state 6 ns
(1) All input signals are specified with tR = tF = 1.5 ns (10% to 90% of DVDD) and timed from a voltage level of (VIL + VIH) / 2.
(2) Not applicable in auto-sleep power-down mode.
ADS8363 ADS7263 ADS7223 tim_half-clock_bas523.gif
1. The ADS7263 and ADS7223 output data with the MSB located as the ADS8363 and the last 2 or 4 bits are '0'.
Figure 1. Detailed Timing Diagram: Half-Clock Mode (ADS8361-Compatible)
ADS8363 ADS7263 ADS7223 tim_full-clock_bas523.gif
1. The ADS7263 and ADS7223 output data with the MSB located as the ADS8363 and the last 2 or 4 bits are '0'.
Figure 2. Detailed Timing Diagram: Full-Clock Mode

7.10 Typical Characteristics

at TA = +25°C, AVDD = 5 V, DVDD = 3.3 V, VREF = 2.5 V (internal), and fDATA = 1 MSPS (unless otherwise noted)
ADS8363 ADS7263 ADS7223 tc_inl-data_rate_bas523.gif
Figure 3. Integral Nonlinearity vs Data Rate
ADS8363 ADS7263 ADS7223 tc_inl-code_bas523.gif
Figure 5. Integral Nonlinearity vs Code
ADS8363 ADS7263 ADS7223 tc_inl-temp_bas523.gif
Figure 7. Integral Nonlinearity vs Temperature
ADS8363 ADS7263 ADS7223 tc_offset-avdd_bas523.gif
Figure 9. Offset Error and Offset Match vs
Analog Supply Voltage
ADS8363 ADS7263 ADS7223 tc_gain-avdd_bas523.gif
Figure 11. Gain Error and Gain Match vs
Analog Supply Voltage
ADS8363 ADS7263 ADS7223 tc_cmrr-avdd_bas523.gif
Figure 13. Common-Mode Rejection Ratio vs
Analog Supply Voltage
ADS8363 ADS7263 ADS7223 tc_freq_bas523.gif
Figure 15. Frequency Spectrum
(4096 Point FFT; fIN = 10 kHz)
ADS8363 ADS7263 ADS7223 tc_snr_sinad-fin_bas523.gif
Figure 17. Signal-to-Noise Ratio and Signal-to-Noise + Distortion vs Input Signal Frequency
ADS8363 ADS7263 ADS7223 tc_thd-fin_bas523.gif
Figure 19. Total Harmonic Distortion vs
Input Signal Frequency
ADS8363 ADS7263 ADS7223 tc_sfdr-fin_bas523.gif
Figure 21. Spurious-Free Dynamic Range vs
Input Signal Frequency
ADS8363 ADS7263 ADS7223 tc_iavdd-temp_bas523.gif
Figure 23. Analog Supply Current vs Temperature
ADS8363 ADS7263 ADS7223 tc_iavdd-fsample_bas523.gif
Figure 25. Analog Supply Current vs Data Rate
ADS8363 ADS7263 ADS7223 tc_dnl-data_rate_bas523.gif
Figure 4. Differential Nonlinearity vs Data Rate
ADS8363 ADS7263 ADS7223 tc_dnl-code_bas523.gif
Figure 6. Differential Nonlinearity vs Code
ADS8363 ADS7263 ADS7223 tc_dnl-temp_bas523.gif
Figure 8. Differential Nonlinearity vs Temperature
ADS8363 ADS7263 ADS7223 tc_offset-temp_bas523.gif
Figure 10. Offset Error and Offset Match vs Temperature
ADS8363 ADS7263 ADS7223 tc_gain-temp_bas523.gif
Figure 12. Gain Error and Gain Match vs Temperature
ADS8363 ADS7263 ADS7223 tc_cmrr-temp_bas523.gif
Figure 14. Common-Mode Rejection Ratio vs Temperature
ADS8363 ADS7263 ADS7223 tc_freq_05msps_bas523.gif
Figure 16. Frequency Spectrum
(4096 Point FFT; fIN = 10 kHz, fSAMPLE = 0.5 MSPS)
ADS8363 ADS7263 ADS7223 tc_snr_sinad-temp_bas523.gif
Figure 18. Signal-to-Noise Ratio and Signal-to-Noise + Distortion vs Temperature
ADS8363 ADS7263 ADS7223 tc_thd-temp_bas523.gif
Figure 20. Total Harmonic Distortion vs Temperature
ADS8363 ADS7263 ADS7223 tc_sfdr-temp_bas523.gif
Figure 22. Spurious-Free Dynamic Range vs Temperature
ADS8363 ADS7263 ADS7223 tc_idvdd-temp_bas523.gif
Figure 24. Digital Supply Current vs Temperature
ADS8363 ADS7263 ADS7223 tc_iavdd-fsample_auto_bas523.gif
Figure 26. Analog Supply Current vs Data Rate
(Auto-Sleep Mode)