SBAS779A December   2016  – October 2018 ADS8671 , ADS8675

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Block Diagram
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements: Conversion Cycle
    7. 6.7  Timing Requirements: Asynchronous Reset
    8. 6.8  Timing Requirements: SPI-Compatible Serial Interface
    9. 6.9  Timing Requirements: Source-Synchronous Serial Interface (External Clock)
    10. 6.10 Timing Requirements: Source-Synchronous Serial Interface (Internal Clock)
    11. 6.11 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Input Structure
      2. 7.3.2 Analog Input Impedance
      3. 7.3.3 Input Protection Circuit
      4. 7.3.4 Programmable Gain Amplifier (PGA)
      5. 7.3.5 Second-Order, Low-Pass Filter (LPF)
      6. 7.3.6 ADC Driver
      7. 7.3.7 Reference
        1. 7.3.7.1 Internal Reference
        2. 7.3.7.2 External Reference
      8. 7.3.8 ADC Transfer Function
      9. 7.3.9 Alarm Features
        1. 7.3.9.1 Input Alarm
        2. 7.3.9.2 AVDD Alarm
    4. 7.4 Device Functional Modes
      1. 7.4.1 Host-to-Device Connection Topologies
        1. 7.4.1.1 Single Device: All multiSPI Options
        2. 7.4.1.2 Single Device: Standard SPI Interface
        3. 7.4.1.3 Multiple Devices: Daisy-Chain Topology
      2. 7.4.2 Device Operational Modes
        1. 7.4.2.1 RESET State
        2. 7.4.2.2 ACQ State
        3. 7.4.2.3 CONV State
    5. 7.5 Programming
      1. 7.5.1 Data Transfer Frame
      2. 7.5.2 Input Command Word and Register Write Operation
      3. 7.5.3 Output Data Word
      4. 7.5.4 Data Transfer Protocols
        1. 7.5.4.1 Protocols for Configuring the Device
        2. 7.5.4.2 Protocols for Reading From the Device
          1. 7.5.4.2.1 Legacy, SPI-Compatible (SYS-xy-S) Protocols with a Single SDO-x
          2. 7.5.4.2.2 Legacy, SPI-Compatible (SYS-xy-S) Protocols with Dual SDO-x
          3. 7.5.4.2.3 Source-Synchronous (SRC) Protocols
            1. 7.5.4.2.3.1 Output Clock Source Options
            2. 7.5.4.2.3.2 Output Bus Width Options
    6. 7.6 Register Maps
      1. 7.6.1 Device Configuration and Register Maps
        1. 7.6.1.1 DEVICE_ID_REG Register (address = 00h)
          1. Table 11. DEVICE_ID_REG Register Field Descriptions
        2. 7.6.1.2 RST_PWRCTL_REG Register (address = 04h)
          1. Table 12. RST_PWRCTL_REG Register Field Descriptions
        3. 7.6.1.3 SDI_CTL_REG Register (address = 08h)
          1. Table 13. SDI_CTL_REG Register Field Descriptions
        4. 7.6.1.4 SDO_CTL_REG Register (address = 0Ch)
          1. Table 14. SDO_CTL_REG Register Field Descriptions
        5. 7.6.1.5 DATAOUT_CTL_REG Register (address = 10h)
          1. Table 15. DATAOUT_CTL_REG Register Field Descriptions
        6. 7.6.1.6 RANGE_SEL_REG Register (address = 14h)
          1. Table 16. RANGE_SEL_REG Register Field Descriptions
        7. 7.6.1.7 ALARM_REG Register (address = 20h)
          1. Table 17. ALARM_REG Register Field Descriptions
        8. 7.6.1.8 ALARM_H_TH_REG Register (address = 24h)
          1. Table 18. ALARM_H_TH_REG Register Field Descriptions
        9. 7.6.1.9 ALARM_L_TH_REG Register (address = 28h)
          1. Table 19. ALARM_L_TH_REG Register Field Descriptions
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
    1. 9.1 Power Supply Decoupling
    2. 9.2 Power Saving
      1. 9.2.1 NAP Mode
      2. 9.2.2 Power-Down (PD) Mode
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Related Links
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Features

  • 14-Bit ADC With Integrated Analog Front-End
  • High Speed:
    • ADS8671: 1 MSPS
    • ADS8675: 500 kSPS
  • Software Programmable Input Ranges:
    • Bipolar Ranges: ±12.288 V, ±10.24 V, ±6.144 V, ±5.12 V, and ±2.56 V
    • Unipolar Ranges: 0 V–12.288 V, 0 V–10.24 V, 0 V–6.144 V, and 0 V–5.12 V
  • 5-V Analog Supply: 1.65-V to 5-V I/O Supply
  • Constant Resistive Input Impedance ≥ 1 MΩ
  • Input Overvoltage Protection: Up to ±20 V
  • On-Chip, 4.096-V Reference With Low Drift
  • Excellent Performance:
    • DNL: ±0.25 LSB; INL: ±0.4 LSB
    • SNR: 84.5 dB; THD: –105 dB
  • ALARM → High, Low Threshold
  • multiSPI™ Interface With Daisy-Chain
  • Extended Industrial Temperature Range:
    –40°C to +125°C