SBASA74C January   2023  – April 2025 ADS9217 , ADS9218 , ADS9219

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Thermal Information
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements
    7. 6.7  Switching Characteristics
    8. 6.8  Timing Diagrams
    9. 6.9  Typical Characteristics: All Devices
    10. 6.10 Typical Characteristics: ADS9219
    11. 6.11 Typical Characteristics: ADS9218
    12. 6.12 Typical Characteristics: ADS9217
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Inputs
      2. 7.3.2 Analog Input Bandwidth
      3. 7.3.3 ADC Transfer Function
      4. 7.3.4 Reference Voltage
      5. 7.3.5 Temperature Sensor
      6. 7.3.6 Data Averaging
      7. 7.3.7 Digital Down Converter
      8. 7.3.8 Data Interface
        1. 7.3.8.1 Data Frame Width
        2. 7.3.8.2 ADC Output Data Randomizer
        3. 7.3.8.3 Synchronizing Multiple ADCs
        4. 7.3.8.4 Test Patterns for Data Interface
          1. 7.3.8.4.1 Fixed Pattern
          2. 7.3.8.4.2 Alternating Test Pattern
          3. 7.3.8.4.3 Digital Ramp
      9. 7.3.9 ADC Sampling Clock Input
    4. 7.4 Device Functional Modes
      1. 7.4.1 Reset
      2. 7.4.2 Power-Down Options
      3. 7.4.3 Normal Operation
      4. 7.4.4 Initialization Sequence
    5. 7.5 Programming
      1. 7.5.1 Register Write
      2. 7.5.2 Register Read
      3. 7.5.3 Multiple Devices: Daisy-Chain Topology for SPI Configuration
        1. 7.5.3.1 Register Write With Daisy-Chain
        2. 7.5.3.2 Register Read With Daisy-Chain
  9. 8 Register Map
    1. 8.1 Register Bank 0
    2. 8.2 Register Bank 1
    3. 8.3 Register Bank 2
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Data Acquisition (DAQ) Circuit for ≤20kHz Input Signal Bandwidth
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Data Acquisition (DAQ) Circuit for ≤100kHz Input Signal Bandwidth
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Application Curves
      3. 9.2.3 Data Acquisition (DAQ) Circuit for ≤1MHz Input Signal Bandwidth
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Mechanical Data

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.6 Data Averaging

The ADS921x features a built-in decimation filter that averages the conversion results from the ADC. The output data rate is reduced with higher data averaging. Table 7-3 compares the ADC output speed against SNR and OSR. The improvement in SNR with averaging in Table 7-4 shows the register settings corresponding to oversampling ratios.

Table 7-3 SNR vs OSR
OSR SNR (dBFS) ADC OUTPUT SPEED
1 95.5 fCYCLE
2 98.1 fCYCLE / 2
4 100.6 fCYCLE / 4
8 102.9 fCYCLE / 8
16 104.8 fCYCLE / 16
Table 7-4 Register Map Settings for OSR
DECIMATION REGISTER INTERFACE MODES(1)
2-LANE SDR AND DDR(2) 1-LANE SDR AND DDR(3)
OSR initialization CLK3 (0xC5[9]) 1 0 for OSR = 2
1 for OSR = 4, 8, and 16
OSR_INIT1 (0xC0[11:10]) 0 for DATA_LANES = 5 or 7
1 for DATA_LANES = 0 or 2
OSR_INIT2 (0xC4[5:4]) 2 0 for OSR = 2
2 for OSR = 4, 8, and 16
OSR_INIT3 (0xC4[1]) 1 0 for OSR = 2
1 for OSR = 4, 8, and 16
OSR_EN (0x0D[6]) 1 1
OSR_RD (0xC5[6:5]) 1 0 for OSR = 2
1 for OSR = 4, 8, and 16
2 OSR (0x0D[5:2]) 0 0
OSR_CLK (0xC0[9:7]) 0 0
4 OSR (0x0D[5:2]) 1 1
OSR_CLK (0xC0[9:7]) 4 0
8 OSR (0x0D[5:2]) 2 2
OSR_CLK (0xC0[9:7]) 5 4
16 OSR (0x0D[5:2]) 3 3
OSR_CLK (0xC0[9:7]) 6 5
(1) See Table 7-7 and Table 7-8 for DATA_LANES configuration.
(2) The ADS9217 functions with all data interface modes.
(3) Not applicable for the ADS9217.

As shown in Figure 7-4, a pulse on the SMPL_SYNC pin resets the decimation filter. A pulse on SMPL_SYNC synchronizes multiple ADS921x devices when using the decimation filter.

ADS9217 ADS9218 ADS9219 Data Output With Decimation Figure 7-4 Data Output With Decimation