SBASAK2B march   2022  – june 2023 AFE7903

PRODUCTION DATA  

  1.   1
  2. 1Features
  3. 2Applications
  4. 3Description
  5. 4Description (continued)
  6. 5Revision History
  7. 6Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Transmitter Electrical Characteristics
    6. 6.6  RF ADC Electrical Characteristics
    7. 6.7  PLL/VCO/Clock Electrical Characteristics
    8. 6.8  Digital Electrical Characteristics
    9. 6.9  Power Supply Electrical Characteristics
    10. 6.10 Timing Requirements
    11. 6.11 Switching Characteristics
    12. 6.12 Typical Characteristics
      1. 6.12.1  RX Typical Characteristics 30 MHz and 400 MHz
      2. 6.12.2  RX Typical Characteristics at 800 MHz
      3. 6.12.3  RX Typical Characteristics 1.75 GHz to 1.9 GHz
      4. 6.12.4  RX Typical Characteristics 2.6 GHz
      5. 6.12.5  RX Typical Characteristics 3.5 GHz
      6. 6.12.6  RX Typical Characteristics 4.9 GHz
      7. 6.12.7  RX Typical Characteristics 6.8 GHz
      8. 6.12.8  TX Typical Characteristics at 30 MHz and 600 MHz
      9. 6.12.9  TX Typical Characteristics at 800 MHz
      10. 6.12.10 TX Typical Characteristics at 1.8 GHz
      11. 6.12.11 TX Typical Characteristics at 2.6 GHz
      12. 6.12.12 TX Typical Characteristics at 3.5 GHz
      13. 6.12.13 TX Typical Characteristics at 4.9 GHz
      14. 6.12.14 TX Typical Characteristics at 7.1 GHz
      15. 6.12.15 PLL and Clock Typical Characteristics
  8. 7Device and Documentation Support
    1. 7.1 Receiving Notification of Documentation Updates
    2. 7.2 Support Resources
    3. 7.3 Trademarks
    4. 7.4 Electrostatic Discharge Caution
    5. 7.5 Glossary
  9. 9Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.11 Switching Characteristics

Typical values at TA = +25°C, full temperature range is TA,MIN = -40°C to TJ,MAX = +110°C; TX Input Rate = 491.52MSPS, fDAC = 8847.36MSPS; fADC = 2949.12MSPS; nominal power supplies; 1 tone at -1 dBFS; DSA Attenuation =0dB; SerDes rate = 24.33Gbps; unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
TX Channel Latency
SerDes Receiver Analog Delay Full rate 2.8 ns
tJESDTX JESD to TX output Latency LMFSHd=2-8-8-1, 368.64 MSPS input rate, 24x Interpolation, Serdes rate = 16.22Gbps (JESD204C) 152 interface clock cycles(1)
LMFSHd=8-16-4-1, 491.52 MSPS 24x Interpolation, Serdes rate = 16.22Gbps (JESD204C) 176
LMFSHd=4-16-8-1, 245.76 MSPS 48x Interpolation, Serdes rate = 16.22Gbps (JESD204C) 124
LMFSHd=2-16-16-1, 122.88 MSPS 96x Interpolation, Serdes rate = 16.22Gbps (JESD204C) 97
RX Channel Latency
tJESDRX RX input to JESD output Latency LMFS=2-16-16-1, 122.88 MSPS, 24x Decimation, Serdes rate = 16.22Gbps (JESD204C) 92 interface clock cycles(1)
LMFS=4-16-8-1, 245.76 MSPS, 12x Decimation, Serdes rate = 16.22Gbps (JESD204C) 108
LMFS=2-8-8-1, 368.64 MSPS, 8x Decimation, Serdes rate = 16.22Gbps (JESD204C) 118
LMFS=4-8-4-1, 491.52 MSPS, 6x Decimation, Serdes rate = 16.22Gbps (JESD204C) 153
SerDes Transmitter Analog Delay 3.6 ns
(1) Interface clock cycles is the period of the digital interface clock rate, e.g. 1GSPS = 1ns.