SBASA21B December   2021  – June 2025 AFE8030

PRODUCTION DATA  

  1.   1
  2. 1Features
  3. 2Applications
  4. 3Description
  5. 4 AFE8030 Functional Block Diagram
  6. 5Device and Documentation Support
    1. 5.1 Device Support
    2. 5.2 Receiving Notification of Documentation Updates
    3. 5.3 Support Resources
    4. 5.4 Trademarks
    5. 5.5 Electrostatic Discharge Caution
    6. 5.6 Glossary
  7. 6Revision History
  8. 7Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • Octal RF sampling 12GSPS transmit DACs
  • Octal RF sampling 3GSPS receive ADCs
  • Dual RF sampling 3GSPS feedback ADCs
  • Maximum RF signal bandwidth:
    • TX/FB: 800MHz
      • 1200MHz in 4-channel mode
    • RX: 600MHz
  • RF frequency range: up to 6GHz
  • Digital Step Attenuators (DSA):
    • TX: 40dB range, 1dB analog and 0.125dB digital steps
    • RX/FB: 31/25dB range, 1dB step
  • Single or dual-band DUC/DDCs
  • Dual NCOs per chain for fast frequency switching
  • Supports TDD operation with fast switching between TX and RX
  • Internal PLL/VCO to generate DAC/ADC clocks
  • Optional external CLK at DAC or ADC rate
  • SerDes data interface:
    • JESD204B and JESD204C
    • 8 SerDes transceivers up to 32.5Gbps
    • 8b/10b and 64b/66b Encoding
    • 12-bit, 16-bit, 24-bit and 32-bit resolution
    • Subclass one multi-device synchronization
  • Package:
    • 17mm × 17mm FCBGA, 0.8mm pitch