SLASF43 December   2023 AFE782H1 , AFE882H1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Timing Requirements
    7. 5.7  Timing Diagrams
    8. 5.8  Typical Characteristics: VOUT DAC
    9. 5.9  Typical Characteristics: ADC
    10. 5.10 Typical Characteristics: Reference
    11. 5.11 Typical Characteristics: HART Modem
    12. 5.12 Typical Characteristics: Power Supply
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Digital-to-Analog Converter (DAC) Overview
        1. 6.3.1.1 DAC Resistor String
        2. 6.3.1.2 DAC Buffer Amplifier
        3. 6.3.1.3 DAC Transfer Function
        4. 6.3.1.4 DAC Gain and Offset Calibration
        5. 6.3.1.5 Programmable Slew Rate
        6. 6.3.1.6 DAC Register Structure and CLEAR State
      2. 6.3.2  Analog-to-Digital Converter (ADC) Overview
        1. 6.3.2.1 ADC Operation
        2. 6.3.2.2 ADC Custom Channel Sequencer
        3. 6.3.2.3 ADC Synchronization
        4. 6.3.2.4 ADC Offset Calibration
        5. 6.3.2.5 External Monitoring Inputs
        6. 6.3.2.6 Temperature Sensor
        7. 6.3.2.7 Self-Diagnostic Multiplexer
        8. 6.3.2.8 ADC Bypass
      3. 6.3.3  Programmable Out-of-Range Alarms
        1. 6.3.3.1 Alarm-Based Interrupts
        2. 6.3.3.2 Alarm Action Configuration Register
        3. 6.3.3.3 Alarm Voltage Generator
        4. 6.3.3.4 Temperature Sensor Alarm Function
        5. 6.3.3.5 Internal Reference Alarm Function
        6. 6.3.3.6 ADC Alarm Function
        7. 6.3.3.7 Fault Detection
      4. 6.3.4  IRQ
      5. 6.3.5  HART Interface
        1. 6.3.5.1  FIFO Buffers
          1. 6.3.5.1.1 FIFO Buffer Access
          2. 6.3.5.1.2 FIFO Buffer Flags
        2. 6.3.5.2  HART Modulator
        3. 6.3.5.3  HART Demodulator
        4. 6.3.5.4  HART Modem Modes
          1. 6.3.5.4.1 Half-Duplex Mode
          2. 6.3.5.4.2 Full-Duplex Mode
        5. 6.3.5.5  HART Modulation and Demodulation Arbitration
          1. 6.3.5.5.1 HART Receive Mode
          2. 6.3.5.5.2 HART Transmit Mode
        6. 6.3.5.6  HART Modulator Timing and Preamble Requirements
        7. 6.3.5.7  HART Demodulator Timing and Preamble Requirements
        8. 6.3.5.8  IRQ Configuration for HART Communication
        9. 6.3.5.9  HART Communication Using the SPI
        10. 6.3.5.10 HART Communication Using UART
        11. 6.3.5.11 Memory Built-In Self-Test (MBIST)
      6. 6.3.6  Internal Reference
      7. 6.3.7  Integrated Precision Oscillator
      8. 6.3.8  Precision Oscillator Diagnostics
      9. 6.3.9  One-Time Programmable (OTP) Memory
      10. 6.3.10 GPIO
      11. 6.3.11 Timer
      12. 6.3.12 Unique Chip Identifier (ID)
      13. 6.3.13 Scratch Pad Register
    4. 6.4 Device Functional Modes
      1. 6.4.1 DAC Power-Down Mode
      2. 6.4.2 Register Built-In Self-Test (RBIST)
      3. 6.4.3 Reset
    5. 6.5 Programming
      1. 6.5.1 Communication Setup
        1. 6.5.1.1 SPI Mode
        2. 6.5.1.2 UART Mode
        3. 6.5.1.3 SPI Plus UART Mode
        4. 6.5.1.4 HART Functionality Setup Options
      2. 6.5.2 GPIO Programming
      3. 6.5.3 Serial Peripheral Interface (SPI)
        1. 6.5.3.1 SPI Frame Definition
        2. 6.5.3.2 SPI Read and Write
        3. 6.5.3.3 Frame Error Checking
        4. 6.5.3.4 Synchronization
      4. 6.5.4 UART Interface
        1. 6.5.4.1 UART Break Mode (UBM)
          1. 6.5.4.1.1 Interface With FIFO Buffers and Register Map
      5. 6.5.5 Status Bits
      6. 6.5.6 Watchdog Timer
  8. 7 Register Maps
    1. 7.1 AFEx82H1 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Multichannel Configuration
    2. 8.2 Typical Application
      1. 8.2.1 4-mA to 20-mA Current Transmitter
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Current Loop Control
          2. 8.2.1.2.2 HART Connections
          3. 8.2.1.2.3 Input Protection and Rectification
          4. 8.2.1.2.4 System Current Budget
        3. 8.2.1.3 Application Curves
    3. 8.3 Initialization Setup
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RRU|24
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.3.1.5 Programmable Slew Rate

The slew rate feature controls the rate at which the output voltage or current changes. This feature is disabled by default and is enabled by writing a logic 1 to the DAC_CFG.SR_EN bit. With the slew rate control feature disabled, the output changes smoothly at a rate limited by the output drive circuitry and the attached load.

With this feature enabled, the output does not slew directly between the two values. Instead, the output steps digitally at a rate defined by DAC_CFG.SR_STEP[2:0] and DAC_CFG.SR_CLK[2:0]. SR_CLK defines the rate at which the digital slew updates. SR_STEP defines the amount by which the output value changes at each update. The register descriptions show different settings for SR_STEP and SR_CLK.

The time required for the output to slew is expressed as Equation 6:

Equation 6. S l e w   T i m e   =   D e l t a   C o d e   C h a n g e S l e w   S t e p   ×   S l e w   C l o c k   R a t e

where

  • Slew Time is expressed in seconds
  • Slew Step is controlled by DAC_CFG.SR_STEP
  • Slew Clock Rate is controlled by DAC_CFG.SR_CLK

When the slew-rate control feature is enabled, the output changes at the programmed slew rate. This configuration results in a staircase formation at the output. If the clear code is asserted (see Section 6.3.1.6), the output slews to the DAC_CLR_CODE value at the programmed slew rate. When new DAC data are written, the output starts slewing to the new value at the slew rate determined by the current DAC code and the new DAC data.

Two slew-rate control modes are available: linear (default) and sinusoidal. Figure 6-3 and Figure 6-4 show the typical rising and falling DAC output waveforms, respectively.

GUID-20210704-CA0I-5KFW-BSSZ-BRMFB4B3JNS1-low.png
4 mA (0x0BA3) to 24 mA (0xF45D) measured on a 40-Ω shunt
Figure 6-3 Linear Slew Rate: Rising
GUID-20210704-CA0I-Q9Z3-LTW4-VPXXCZ9VN8ZR-low.png
24 mA (0xF45D) to 4 mA (0x0BA3) measured on 40-Ω shunt
Figure 6-4 Linear Slew Rate: Falling

Sinusoidal mode enables fast DAC settling while improving analog rate of change characteristics. Sinusoidal mode is selected by the DAC_CFG.SR_MODE bit. Figure 6-5 and Figure 6-6 show the typical rising and falling DAC output waveforms with sinusoidal slew-rate control, respectively.

GUID-20210704-CA0I-7GT3-HFFK-9GZP02DNXSTT-low.png
4 mA (0x0BA3) to 24 mA (0xF45D) measured on a 40-Ω shunt
Figure 6-5 Sinusoidal Slew Rate: Rising
GUID-20210704-CA0I-JR8N-BPGV-HR9C1G1ZLN7C-low.png
24 mA (0xF45D) to 4 mA (0x0BA3) measured on a 40-Ω shunt
Figure 6-6 Sinusoidal Slew Rate: Falling

If the slew-rate feature is disabled while the DAC is executing the slew-rate command, the slew-rate operation is aborted, and the DAC output goes to the target code.