SPRS695D September   2011  – January 2016 AM3871 , AM3874

PRODUCTION DATA.  

  1. 1High-Performance System-on-Chip (SoC)
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
    1. 2.1  Device Comparison
    2. 2.2  Device Characteristics
    3. 2.3  Device Compatibility
    4. 2.4  ARM Cortex-A8 Microprocessor Unit (MPU) Subsystem Overview
      1. 2.4.1 ARM Cortex-A8 RISC Processor
      2. 2.4.2 Embedded Trace Module (ETM)
      3. 2.4.3 ARM Cortex-A8 Interrupt Controller (AINTC)
      4. 2.4.4 ARM Cortex-A8 PLL (PLL_ARM)
      5. 2.4.5 ARM MPU Interconnect
    5. 2.5  Media Controller Overview
    6. 2.6  SGX530 Overview
    7. 2.7  Spinlock Module Overview
    8. 2.8  Mailbox Module Overview
    9. 2.9  Memory Map Summary
      1. 2.9.1 L3 Memory Map
      2. 2.9.2 L4 Memory Map
        1. 2.9.2.1 L4 Fast Peripheral Memory Map
        2. 2.9.2.2 L4 Slow Peripheral Memory Map
      3. 2.9.3 DDR DMM TILER Extended Addressing Map
    10. 2.10 Pin Maps
    11. 2.11 Terminal Functions
      1. 2.11.1  Boot Configuration
      2. 2.11.2  Camera Interface (I/F)
      3. 2.11.3  Controller Area Network (DCAN) Modules (DCAN0, DCAN1)
      4. 2.11.4  DDR2/DDR3 Memory Controller
      5. 2.11.5  EDMA
      6. 2.11.6  EMAC [(R)(G)MII Modes] and MDIO
      7. 2.11.7  General-Purpose Input/Outputs (GPIOs)
      8. 2.11.8  GPMC
      9. 2.11.9  HDMI
      10. 2.11.10 I2C
      11. 2.11.11 McASP
      12. 2.11.12 McBSP
      13. 2.11.13 PCI-Express (PCIe)
      14. 2.11.14 Reset, Interrupts, and JTAG Interface
      15. 2.11.15 Serial ATA (SATA) Signals
      16. 2.11.16 SD Signals (MMC/SD/SDIO)
      17. 2.11.17 SPI
      18. 2.11.18 Oscillator/PLL, Audio Reference Clocks, and Clock Generator
      19. 2.11.19 Timer
      20. 2.11.20 UART
      21. 2.11.21 USB
      22. 2.11.22 Video Input (Digital)
      23. 2.11.23 Video Output (Digital)
      24. 2.11.24 Video Output (Analog, TV)
      25. 2.11.25 Reserved Pins
      26. 2.11.26 Supply Voltages
      27. 2.11.27 Ground Pins (VSS)
  3. 3Device Configurations
    1. 3.1 Control Module Registers
    2. 3.2 Boot Modes
      1. 3.2.1 XIP (NOR) Boot Options
      2. 3.2.2 NAND Flash Boot
      3. 3.2.3 NAND I2C Boot (I2C EEPROM)
      4. 3.2.4 MMC/SD Cards Boot
      5. 3.2.5 SPI Boot
      6. 3.2.6 Ethernet PHY Mode Selection
      7. 3.2.7 PCIe Bootmode (PCIE_32 and PCIE_64)
      8. 3.2.8 UART Bootmode
    3. 3.3 Pin Multiplexing Control
    4. 3.4 Handling Unused Pins
    5. 3.5 DeBugging Considerations
      1. 3.5.1 Pullup/Pulldown Resistors
  4. 4 System Interconnect
  5. 5Device Operating Conditions
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Recommended Operating Conditions
    3. 5.3 Power-On Hours (POH)
    4. 5.4 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Temperature (Unless Otherwise Noted)
    5. 5.5 Thermal Resistance Characteristics (PBGA Package) [CYE-04] (Thinner Top Hat)
  6. 6Power, Reset, Clocking, and Interrupts
    1. 6.1 Power, Reset and Clock Management (PRCM) Module
    2. 6.2 Power
      1. 6.2.1 Voltage and Power Domains
        1. 6.2.1.1 Core Logic Voltage Domains
        2. 6.2.1.2 Memory Voltage Domains
        3. 6.2.1.3 Power Domains
      2. 6.2.2 SmartReflex [Not Supported]
        1. 6.2.2.1 Dynamic Voltage Frequency Scaling (DVFS)
        2. 6.2.2.2 Adaptive Voltage Scaling [Not Supported]
      3. 6.2.3 Memory Power Management
      4. 6.2.4 SERDES_CLKP and SERDES_CLKN LDO
      5. 6.2.5 Dual Voltage I/Os
      6. 6.2.6 I/O Power-Down Modes
      7. 6.2.7 Standby Mode
      8. 6.2.8 Supply Sequencing
        1. 6.2.8.1 Power-Up Sequence
        2. 6.2.8.2 Power-Down Sequence
      9. 6.2.9 Power-Supply Decoupling
        1. 6.2.9.1 Analog and PLL
        2. 6.2.9.2 Digital
    3. 6.3 Reset
      1. 6.3.1  System-Level Reset Sources
      2. 6.3.2  Power-on Reset (POR pin)
      3. 6.3.3  External Warm Reset (RESET pin)
      4. 6.3.4  Emulation Warm Reset
      5. 6.3.5  Watchdog Reset
      6. 6.3.6  Software Global Cold Reset
      7. 6.3.7  Software Global Warm Reset
      8. 6.3.8  Test Reset (TRST pin)
      9. 6.3.9  Local Reset
      10. 6.3.10 Reset Priority
      11. 6.3.11 Reset Status Register
      12. 6.3.12 PCIE Reset Isolation
      13. 6.3.13 EMAC Switch Reset Isolation
      14. 6.3.14 RSTOUT_WD_OUT Pin
      15. 6.3.15 Effect of Reset on Emulation and Trace
      16. 6.3.16 Reset During Power Domain Switching
      17. 6.3.17 Pin Behaviors at Reset
      18. 6.3.18 Reset Electrical Data/Timing
    4. 6.4 Clocking
      1. 6.4.1  Device (DEV) and Auxiliary (AUX) Clock Inputs
        1. 6.4.1.1 Using the Internal Oscillators
        2. 6.4.1.2 Using a 1.8V LVCMOS-Compatible Clock Input
      2. 6.4.2  SERDES_CLKN/P Input Clock
      3. 6.4.3  AUD_CLKINx Input Clocks
      4. 6.4.4  CLKIN32 Input Clock
      5. 6.4.5  External Input Clocks
      6. 6.4.6  Output Clocks Select Logic
      7. 6.4.7  Input/Output Clocks Electrical Data/Timing
      8. 6.4.8  PLLs
        1. 6.4.8.1 PLL Power Supply Filtering
        2. 6.4.8.2 PLL Multipliers and Dividers
        3. 6.4.8.3 PLL Frequency Limits
        4. 6.4.8.4 PLL Register Descriptions
      9. 6.4.9  SYSCLKs
      10. 6.4.10 Module Clocks
    5. 6.5 Interrupts
      1. 6.5.1 ARM Cortex-A8 Interrupts
  7. 7 Peripheral Information and Timings
    1. 7.1  Parameter Information
      1. 7.1.1 1.8-V and 3.3-V Signal Transition Levels
      2. 7.1.2 3.3-V Signal Transition Rates
      3. 7.1.3 Timing Parameters and Board Routing Analysis
    2. 7.2  Recommended Clock and Control Signal Transition Behavior
    3. 7.3  Controller Area Network Interface (DCAN)
      1. 7.3.1 DCAN Peripheral Register Descriptions
      2. 7.3.2 DCAN Electrical Data/Timing
    4. 7.4  EDMA
      1. 7.4.1 EDMA Channel Synchronization Events
      2. 7.4.2 EDMA Peripheral Register Descriptions
    5. 7.5  Emulation Features and Capability
      1. 7.5.1 Advanced Event Triggering (AET)
      2. 7.5.2 Trace
      3. 7.5.3 IEEE 1149.1 JTAG
        1. 7.5.3.1 JTAG ID (JTAGID) Register Description
        2. 7.5.3.2 JTAG Electrical Data/Timing
    6. 7.6  Ethernet MAC Switch (EMAC SW)
      1. 7.6.1 EMAC Peripheral Register Descriptions
      2. 7.6.2 EMAC Electrical Data/Timing
        1. 7.6.2.1 EMAC MII and GMII Electrical Data/Timing
        2. 7.6.2.2 EMAC RMII Electrical Data/Timing
        3. 7.6.2.3 EMAC RGMII Electrical Data/Timing
      3. 7.6.3 Management Data Input/Output (MDIO)
        1. 7.6.3.1 MDIO Peripheral Register Descriptions
        2. 7.6.3.2 MDIO Electrical Data/Timing
    7. 7.7  General-Purpose Input/Output (GPIO)
      1. 7.7.1 GPIO Peripheral Register Descriptions
      2. 7.7.2 GPIO Electrical Data/Timing
    8. 7.8  General-Purpose Memory Controller (GPMC) and Error Location Module (ELM)
      1. 7.8.1 GPMC and ELM Peripherals Register Descriptions
      2. 7.8.2 GPMC Electrical Data/Timing
        1. 7.8.2.1 GPMC/NOR Flash Interface Synchronous Mode Timing (Nonmultiplexed and Multiplexed Modes)
        2. 7.8.2.2 GPMC/NOR Flash Interface Asynchronous Mode Timing (Nonmultiplexed and Multiplexed Modes)
        3. 7.8.2.3 GPMC/NAND Flash and ELM Interface Timing
    9. 7.9  High-Definition Multimedia Interface (HDMI)
      1. 7.9.1 HDMI Design Guidelines
        1. 7.9.1.1 HDMI Interface Schematic
        2. 7.9.1.2 TMDS Routing
        3. 7.9.1.3 DDC Signals
        4. 7.9.1.4 HDMI ESD Protection Device (Required)
        5. 7.9.1.5 PCB Stackup Specifications
        6. 7.9.1.6 Grounding
    10. 7.10 High-Definition Video Processing Subsystem (HDVPSS)
      1. 7.10.1 HDVPSS Electrical Data/Timing
      2. 7.10.2 Video DAC Guidelines and Electrical Data/Timing
    11. 7.11 Inter-Integrated Circuit (I2C)
      1. 7.11.1 I2C Peripheral Register Descriptions
      2. 7.11.2 I2C Electrical Data/Timing
    12. 7.12 Imaging Subsystem (ISS)
      1. 7.12.1 ISSCAM Electrical Data/Timing
    13. 7.13 DDR2/DDR3 Memory Controller
      1. 7.13.1 DDR2/3 Memory Controller Register Descriptions
      2. 7.13.2 DDR2/DDR3 PHY Register Descriptions
      3. 7.13.3 DDR-Related Control Module Registers Description
      4. 7.13.4 DDR2/DDR3 Memory Controller Electrical Data/Timing
        1. 7.13.4.1 DDR2 Routing Specifications
          1. 7.13.4.1.1 DDR2 Interface
            1. 7.13.4.1.1.1  DDR2 Interface Schematic
            2. 7.13.4.1.1.2  Compatible JEDEC DDR2 Devices
            3. 7.13.4.1.1.3  PCB Stackup
            4. 7.13.4.1.1.4  Placement
            5. 7.13.4.1.1.5  DDR2 Keepout Region
            6. 7.13.4.1.1.6  Bulk Bypass Capacitors
            7. 7.13.4.1.1.7  High-Speed Bypass Capacitors
            8. 7.13.4.1.1.8  Net Classes
            9. 7.13.4.1.1.9  DDR2 Signal Termination
            10. 7.13.4.1.1.10 VREFSSTL_DDR Routing
          2. 7.13.4.1.2 DDR2 CK and ADDR_CTRL Routing
        2. 7.13.4.2 DDR3 Routing Specifications
          1. 7.13.4.2.1 DDR3 versus DDR2
          2. 7.13.4.2.2 DDR3 EMIFs
          3. 7.13.4.2.3 DDR3 Device Combinations
          4. 7.13.4.2.4 DDR3 Interface Schematic
            1. 7.13.4.2.4.1  Compatible JEDEC DDR3 Devices
            2. 7.13.4.2.4.2  PCB Stackup
            3. 7.13.4.2.4.3  Placement
            4. 7.13.4.2.4.4  DDR3 Keepout Region
            5. 7.13.4.2.4.5  Bulk Bypass Capacitors
            6. 7.13.4.2.4.6  High-Speed Bypass Capacitors
              1. 7.13.4.2.4.6.1 Return Current Bypass Capacitors and Vias
            7. 7.13.4.2.4.7  Net Classes
            8. 7.13.4.2.4.8  DDR3 Signal Termination
            9. 7.13.4.2.4.9  VREFSSTL_DDR Routing
            10. 7.13.4.2.4.10 VTT
            11. 7.13.4.2.4.11 CK and ADDR_CTRL Topologies and Routing Definition
              1. 7.13.4.2.4.11.1 Four DDR3 Devices
                1. 7.13.4.2.4.11.1.1 CK and ADDR_CTRL Topologies, Four DDR3 Devices
                2. 7.13.4.2.4.11.1.2 CK and ADDR_CTRL Routing, Four DDR3 Devices
              2. 7.13.4.2.4.11.2 Two DDR3 Devices
                1. 7.13.4.2.4.11.2.1 CK and ADDR_CTRL Topologies, Two DDR3 Devices
                2. 7.13.4.2.4.11.2.2 CK and ADDR_CTRL Routing, Two DDR3 Devices
              3. 7.13.4.2.4.11.3 One DDR3 Device
                1. 7.13.4.2.4.11.3.1 CK and ADDR_CTRL Topologies, One DDR3 Device
                2. 7.13.4.2.4.11.3.2 CK and ADDR/CTRL Routing, One DDR3 Device
            12. 7.13.4.2.4.12 Data Topologies and Routing Definition
              1. 7.13.4.2.4.12.1 DQS and DQ/DM Topologies, Any Number of Allowed DDR3 Devices
              2. 7.13.4.2.4.12.2 DQS and DQ/DM Routing, Any Number of Allowed DDR3 Devices
            13. 7.13.4.2.4.13 Routing Specification
              1. 7.13.4.2.4.13.1 CK and ADDR_CTRL Routing Specification
              2. 7.13.4.2.4.13.2 DQS and DQ Routing Specification
    14. 7.14 Multichannel Audio Serial Port (McASP)
      1. 7.14.1 McASP Device-Specific Information
      2. 7.14.2 McASP0, McASP1, McASP2, McASP3, McASP4, and McASP5 Peripheral Registers Descriptions
      3. 7.14.3 McASP (McASP[5:0]) Electrical Data/Timing
    15. 7.15 Multichannel Buffered Serial Port (McBSP)
      1. 7.15.1 McBSP Peripheral Register Descriptions
      2. 7.15.2 McBSP Electrical Data/Timing
    16. 7.16 MultiMedia Card/Secure Digital/Secure Digital Input Output (MMC/SD/SDIO)
      1. 7.16.1 MMC/SD/SDIO Peripheral Register Descriptions
      2. 7.16.2 MMC/SD/SDIO Electrical Data/Timing
    17. 7.17 Peripheral Component Interconnect Express (PCIe)
      1. 7.17.1 PCIe Peripheral Register Descriptions
      2. 7.17.2 PCIe Electrical Data/Timing
      3. 7.17.3 PCIe Design and Layout Guidelines
        1. 7.17.3.1 Clock Source
        2. 7.17.3.2 PCIe Connections and Interface Compliance
          1. 7.17.3.2.1 Coupling Capacitors
          2. 7.17.3.2.2 Polarity Inversion
        3. 7.17.3.3 Nonstandard PCIe Connections
          1. 7.17.3.3.1 PCB Stackup Specifications
          2. 7.17.3.3.2 Routing Specifications
    18. 7.18 Serial ATA Controller (SATA)
      1. 7.18.1 SATA Peripheral Register Descriptions
      2. 7.18.2 SATA Interface Design Guidelines
        1. 7.18.2.1 SATA Interface Schematic
        2. 7.18.2.2 Compatible SATA Components and Modes
        3. 7.18.2.3 PCB Stackup Specifications
        4. 7.18.2.4 Routing Specifications
        5. 7.18.2.5 Coupling Capacitors
    19. 7.19 Serial Peripheral Interface (SPI)
      1. 7.19.1 SPI Peripheral Register Descriptions
      2. 7.19.2 SPI Electrical Data/Timing
    20. 7.20 Timers
      1. 7.20.1 Timer Peripheral Register Descriptions
      2. 7.20.2 Timer Electrical/Data Timing
    21. 7.21 Universal Asynchronous Receiver/Transmitter (UART)
      1. 7.21.1 UART Peripheral Register Descriptions
      2. 7.21.2 UART Electrical/Data Timing
    22. 7.22 Universal Serial Bus (USB2.0)
      1. 7.22.1 USB2.0 Peripheral Register Descriptions
      2. 7.22.2 USB2.0 Electrical Data/Timing
  8. 8Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
      2. 8.1.2 Device and Development-Support Tool Nomenclature
    2. 8.2 Documentation Support
    3. 8.3 Related Links
    4. 8.4 Community Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Export Control Notice
    8. 8.8 Glossary
  9. 9Mechanical, Packaging, and Orderable Information
    1. 9.1 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • CYE|684
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Device Pins

2.10 Pin Maps

Figure 2-1 through Figure 2-8 show the bottom view of the package pin assignments in eight pin maps (A, B, C, D, E, F, G, and H).

AM3874 AM3871 A_CYE_prs647_cat.gif Figure 2-1 Pin Map A
AM3874 AM3871 B_CYE_prs695_f4.gif Figure 2-2 Pin Map B
AM3874 AM3871 C_CYE_prs647.gif Figure 2-3 Pin Map C
AM3874 AM3871 D_CYE_noCSI2_prs694.gif Figure 2-4 Pin Map D
AM3874 AM3871 E_CYE_prs647_cat.gif Figure 2-5 Pin Map E
AM3874 AM3871 F_CYE_prs647_master.gif Figure 2-6 Pin Map F
AM3874 AM3871 G_CYE_prs647_cat.gif Figure 2-7 Pin Map G
AM3874 AM3871 H_CYE_prs647_cat_woCSI2.gif Figure 2-8 Pin Map H

2.11 Terminal Functions

The terminal functions tables identify the external signal names and their pin multiplexing, the associated pin (ball) numbers along with the mechanical package designator, the pin type (for example, I, O, Z, S, A, or GND), whether the pin has any internal pullup or pulldown resistors (for example, IPU, IPD, or DIS), the supply voltage source, and describe the function or functions on the pin. The MUXED column in the tables also identifies all peripheral pin functions multiplexed on a pin, the pin control register (PINCNTLx) that controls which peripheral pin function is selected for that particular pin, and indicates the state driven on the peripheral input (logic 0, logic 1, or PIN level) when the peripheral pin function is not selected (that is, the deselected input state [DSIS]), and the Multi-Muxed [MM] option for that peripheral pin function). For more detailed information on device configuration, boot mode order, peripheral selection, and multiplexed/shared pin control, and so on, see Section 3, Device Configurations of this data manual.

2.11.1 Boot Configuration

Table 2-1 Boot Configuration Terminal Functions

SIGNAL TYPE(1) OTHER(2) (3) MUXED DESCRIPTION
NAME NO.
BOOT
GPMC_D[15]/
BTMODE[15]		 Y25 I DIS
DVDD_GPMC		 GPMC
PINCNTL104
DSIS: PIN		 GPMC CS0 default GPMC_Wait enable input. This pin is multiplexed between ARM Cortex-A8 boot mode and General-Purpose Memory Controller (GPMC) peripheral functions. At reset, BTMODE[15] is sampled to determine the GPMC CS0 Wait enable:

  • 0 = Wait disabled
  • 1 = Wait enabled


After reset, this pin functions as GPMC multiplexed data/address pin 15 (GPMC_D[15]).

GPMC_D[14]/
BTMODE[14]		 V24 I DIS
DVDD_GPMC		 GPMC
PINCNTL103
DSIS: PIN		 GPMC CS0 default Address/Data multiplexing mode input. These pins are multiplexed between ARM Cortex-A8 boot mode and General-Purpose Memory Controller (GPMC) peripheral functions. At reset, BTMODE[14:13] are sampled to determine the GPMC CS0 Address/Data multiplexing:

  • 00 = Not muxed
  • 01 = A/A/D muxed
  • 10 = A/D muxed
  • 11 = Reserved


After reset, this pin functions as GPMC multiplexed data/address pins 14 through 13 (GPMC_D[14:13]).

GPMC_D[13]/
BTMODE[13]		 U23 I DIS
DVDD_GPMC		 GPMC
PINCNTL102
DSIS: PIN
GPMC_D[12]/
BTMODE[12]		 U24 I DIS
DVDD_GPMC		 GPMC
PINCNTL101
DSIS: PIN		 GPMC CS0 default Data Bus Width input. This pin is multiplexed between ARM Cortex-A8 boot mode and General-Purpose Memory Controller (GPMC) peripheral functions. At reset, BTMODE[12] is sampled to determine the GPMC CS0 bus width:

  • 0 = 8-bit data bus
  • 1 = 16-bit data bus


After reset, this pin functions as GPMC multiplexed data/address pin 12 (GPMC_D[12]).

GPMC_D[11]/
BTMODE[11]		 AA27 I DIS
DVDD_GPMC		 GPMC
PINCNTL100
DSIS: PIN		 RSTOUT_WD_OUT Configuration. This pin is multiplexed between ARM Cortex-A8 boot mode and General-Purpose Memory Controller (GPMC) peripheral functions. At reset, BTMODE[11] is sampled to determine the function of the RSTOUT_WD_OUT pin:

  • 0 = RSTOUT is asserted when a Watchdog Timer reset, POR, RESET, or Emulation/Software-Global Cold/Warm reset occurs
  • 1 = RSTOUT_WD_OUT is asserted only when a Watchdog Timer reset occurs


After reset, this pin functions as GPMC multiplexed data/address pin 11 (GPMC_D[11]).

GPMC_D[10]/
BTMODE[10]		 Y26 I DIS
DVDD_GPMC		 GPMC
PINCNTL99
DSIS: PIN		 XIP (NOR) on GPMC Configuration. This pin is multiplexed between ARM Cortex-A8 boot mode and General-Purpose Memory Controller (GPMC) peripheral functions. At reset, when the XIP (MUX0), XIP (MUX1), XIP w/ WAiT (MUX0) or XIP w/ WAiT (MUX1) bootmode is selected (see Table 3-1), BTMODE[10] is sampled to select between GPMC pin muxing options A or B shown in Table 3-2, XIP (on GPMC) Boot Options [Muxed or Non-Muxed].

  • 0 = GPMC Option A
  • 1 = GPMC Option B


After reset, this pin functions as GPMC multiplexed data/address pin 10 (GPMC_D[10]).

GPMC_D[9]/
BTMODE[9]		 AB28 I DIS
DVDD_GPMC		 GPMC
PINCNTL98
DSIS: PIN		 Ethernet PHY Configuration. These pins are multiplexed between ARM Cortex-A8 boot mode and General-Purpose Memory Controller (GPMC) peripheral functions. At reset, when EMAC bootmode is selected (see Table 3-1), BTMODE[9:8] pins are sampled to determine the function of the Ethernet PHY Mode selection.

  • 00 = MII (GMII)
  • 01 = RMII
  • 10 = RGMII
  • 11 = Reserved


For more detailed information on the EMAC PHY boot modes and the EMAC pin functions selected, see Section 3.2.6, Ethernet PHY Mode Selection.

After reset, these pins function as GPMC multiplexed data/address pins 9 and 8 (GPMC_D[9] and GPMC_D[8]).
GPMC_D[8]/
BTMODE[8] 		Y27 I DIS
DVDD_GPMC		 GPMC
PINCNTL97
DSIS: PIN
GPMC_D[7]/
BTMODE[7] 		V25 I DIS
DVDD_GPMC		 GPMC
PINCNTL96
DSIS: PIN		 Reserved Boot Pins. These pins are multiplexed between ARM Cortex-A8 boot mode and General-Purpose Memory Controller (GPMC) peripheral functions.

For proper device operation at reset, these pins should be externally pulled low.

After reset, these pins function as GPMC multiplexed data/address pins 10 through 5 (GPMC_D[7:5]).
GPMC_D[6]/
BTMODE[6] 		U25 I DIS
DVDD_GPMC		 GPMC
PINCNTL95
DSIS: PIN
GPMC_D[5]/
BTMODE[5] 		AA28 I DIS
DVDD_GPMC		 GPMC
PINCNTL94
DSIS: PIN
GPMC_D[4]/
BTMODE[4] 		V26 I DIS
DVDD_GPMC		 GPMC
PINCNTL93
DSIS: PIN		 ARM Cortex-A8 Boot Mode Configuration Bits. These pins are multiplexed between ARM Cortex-A8 boot mode and the General-Purpose Memory Controller (GPMC) peripheral functions.

At reset, the boot mode inputs BTMODE[4:0] are sampled to determine the ARM boot configuration. For more details on the types of boot modes supported, see Section 3.2, Boot Modes, of this document, along with the AM387x ROM Code Memory and Peripheral Booting chapter of the AM387x Sitara™ ARM Processors Technical Reference Manual (Literature Number: SPRUGZ7).

After reset, these pins function as GPMC multiplexed data/address pins 4 through 0 (GPMC_D[4:0]).
GPMC_D[3]/
BTMODE[3] 		W27 I DIS
DVDD_GPMC		 GPMC
PINCNTL92
DSIS: PIN
GPMC_D[2]/
BTMODE[2] 		V27 I DIS
DVDD_GPMC		 GPMC
PINCNTL91
DSIS: PIN
GPMC_D[1]/
BTMODE[1] 		Y28 I DIS
DVDD_GPMC		 GPMC
PINCNTL90
DSIS: PIN
GPMC_D[0]/
BTMODE[0] 		U26 I DIS
DVDD_GPMC		 GPMC
PINCNTL89
DSIS: PIN
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS = De-selected Input State
(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the Internal Pull during and after Reset. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see Section 3.5.1, Pullup/Pulldown Resistors and Section 6.3.17, Pin Behaviors at Reset.
(3) Specifies the operating I/O supply voltage for each signal

2.11.2 Camera Interface (I/F)

Table 2-2 Camera I/F Terminal Functions

SIGNAL TYPE(1) OTHER(2) (3) MUXED DESCRIPTION
NAME NO.
CAMERA I/F
VOUT[0]_FLD/
CAM_PCLK/
GPMC_A[12]/
UART2_RTS/
GP2[2]		 AF18 I IPD
DVDD_C		 VOUT[0], GPMC, UART2, GP2
PINCNTL175
DSIS: 0		 Camera Pixel Clock.
VIN[0]A_D[23]/
CAM_D[15]/
EMAC[1]_RMTXEN/
SPI[3]_D[0]/
GP0[17]		 AC16 I IPD
DVDD_C		 VIN[0]A, EMAC[1], SPI[3], GP0
PINCNTL163
DSIS: PIN		 Camera data inputs
VIN[0]A_D[22]/
CAM_D[14]/
EMAC[1]_RMTXD[1]/
SPI[3]_D[1]/
GP0[16]		 AC21 I IPD
DVDD_C		 VIN[0]A, EMAC[1]_RM, SPI[3], GP0
PINCNTL162
DSIS: PIN
VIN[0]A_D[21]/
CAM_D[13]/
EMAC[1]_RMTXD[0]/
SPI[3]_SCLK/
GP0[15]		 AE18 I IPD
DVDD_C		 VIN[0]A, EMAC[1]_RM, SPI[3], GP0
PINCNTL161
DSIS: PIN
VIN[0]A_D[20]/
CAM_D[12]/
EMAC[1]_RMCRSDV/
SPI[3]_SCS[0]/
GP0[14]		 AC17 I IPD
DVDD_C		 VIN[0]A, EMAC[1]_RM, SPI[3], GP0
PINCNTL160
DSIS: PIN
VIN[0]A_D[19]/
CAM_D[11]/
EMAC[1]_RMRXD[0]/
I2C[3]_SDA/
GP0[13]		 AF21 I IPU
DVDD_C		 VIN[0]A, EMAC[1]_RM, I2C[3], GP0
PINCNTL159
DSIS: PIN
VIN[0]A_D[18]/
CAM_D[10]/
EMAC[1]_RMRXD[1]/
I2C[3]_SCL/
GP0[12]		 AF20 I IPU
DVDD_C		 VIN[0]A, EMAC[1]_RM, I2C[3], GP0
PINCNTL158
DSIS: PIN
VIN[0]A_D[17]/
CAM_D[9]/
EMAC[1]_RMRXER/
GP0[11]		 AB21 I IPD
DVDD_C		 VIN[0]A, EMAC[1]_RM, GP0
PINCNTL157
DSIS: PIN
VIN[0]A_D[16]/
CAM_D[8]/
I2C[2]_SCL/
GP0[10]		 AA21 I IPU
DVDD_C		 VIN[0]A, I2C[2], GP0
PINCNTL156
DSIS: PIN
VIN[0]A_DE/
CAM_D[7]/
GP0[18]		 AB17 I IPU
DVDD_C		 VIN[0]A, GP0
PINCNTL164
DSIS: PIN		 Camera data inputs
VIN[0]B_DE/
CAM_D[6]/
GP0[19]		 AC15 I IPU
DVDD_C		 VIN[0]A, GP0
PINCNTL165
DSIS: PIN
VIN[0]A_FLD/
CAM_D[5]/
GP0[20]		 AC22 I IPU
DVDD_C		 VIN[0]A, GP0
PINCNTL166
DSIS: PIN
VIN[0]B_FLD/
CAM_D[4]/
GP0[21]		 AD17 I IPU
DVDD_C		 VIN[0]B, GP0
PINCNTL167
DSIS: PIN
VOUT[1]_G_Y_YC[1]/
CAM_D[3]/
GPMC_A[5]/
UART4_RXD/
GP0[22]		 AD18 I IPU
DVDD_C		 VOUT[1], GPMC, UART4, GP0
PINCNTL168
DSIS: PIN
VOUT[1]_G_Y_YC[0]/
CAM_D[2]/
GPMC_A[6]/
UART4_TXD/
GP0[23]		 AC18 I IPD
DVDD_C		 VOUT[1], GPMC, UART4, GP0
PINCNTL169
DSIS: PIN
VOUT[1]_R_CR[1]/
CAM_D[1]/
GPMC_A[7]/
UART4_CTS/
GP0[24]		 AC19 I IPD
DVDD_C		 VOUT[1], GPMC, UART4, GP0
PINCNTL170
DSIS: PIN
VOUT[1]_R_CR[0]/
CAM_D[0]/
GPMC_A[8]/
UART4_RTS/
GP0[25]		 AA22 I IPD
DVDD_C		 VOUT[1], GPMC, UART4, GP0
PINCNTL171
DSIS: PIN
VOUT[1]_B_CB_C[1]/
CAM_HS/
GPMC_A[9]/
UART2_RXD/
GP0[26]		 AE23 I/O IPD
DVDD_C		 VOUT[1], GPMC, UART2, GP0
PINCNTL172
DSIS: 0		 Camera Horizontal Synchronization
VOUT[1]_B_CB_C[0]/
CAM_VS/
GPMC_A[10]/
UART2_TXD/
GP0[27]		 AD23 I/O IPU
DVDD_C		 VOUT[1], GPMC, UART2, GP0
PINCNTL173
DSIS: 0		 Camera Vertical Synchronization
VIN[0]A_D[13]_BD[5]/
CAM_RESET/
GP2[18]		 AF17 I/O IPD
DVDD		 VIN[0]AB, GP2
PINCNTL153
DSIS: 0		 Camera Reset. Used for Strobe Synchronization
VIN[0]A_D[11]_BD[3]/
CAM_WE/
GP2[16]		 AH17 I IPD
DVDD		 VIN[0]AB. GP2
PINCNTL151
DSIS: 0
MM: MUX1		 Camera Write Enable
VOUT[1]_FLD/
CAM_FLD/
CAM_WE/
GPMC_A[11]/
UART2_CTS/
GP0[28]		 AB23 I IPD
DVDD_C		 VOUT[1], CAMERA_I/F, GPMC, UART2, GP0
PINCNTL174
DSIS: 0
MM: MUX0
VOUT[1]_FLD/
CAM_FLD/
CAM_WE/
GPMC_A[11]/
UART2_CTS/
GP0[28]		 AB23 I/O IPD
DVDD_C		 VOUT[1], CAMERA_I/F, GPMC, UART2, GP0
PINCNTL174
DSIS: 0		 Camera Field Identification input
VIN[0]A_D[14]_BD[6]/
CAM_STROBE/
GP2[19]		 AC12 O IPD
DVDD		 VIN[0]AB, GP2
PINCNTL154
DSIS: N/A		 Camera Flash Strobe Control Signal
VIN[0]A_D[15]_BD[7]/
CAM_SHUTTER/
GP2[20]		 AC14 O IPD
DVDD		 VIN[0]AB, GP2
PINCNTL155
DSIS: N/A		 Camera Mechanical Shutter Control Signal
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS = De-selected Input State
(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the Internal Pull after Reset. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see Section 3.5.1, Pullup/Pulldown Resistors and Section 6.3.17, Pin Behaviors at Reset.
(3) Specifies the operating I/O supply voltage for each signal

2.11.3 Controller Area Network (DCAN) Modules (DCAN0, DCAN1)

Table 2-3 DCAN Terminal Functions

SIGNAL TYPE(1) OTHER(2)(3) MUXED DESCRIPTION
NAME NO.
DCAN0
DCAN0_RX/
UART2_RXD/
I2C[3]_SCL/
GP1[1]		 AG6 I/O IPU
DVDD		 UART2, I2C[3], GP1
PINCNTL69
DSIS: 1		 DCAN0 receive data pin.
DCAN0_TX/
UART2_TXD/
I2C[3]_SDA/
GP1[0]		 AH6 I/O IPU
DVDD		 UART2, I2C[3], GP1
PINCNTL68
DSIS: 1		 DCAN0 transmit data pin.
DCAN1
UART0_RTS/
UART4_TXD/
DCAN1_RX/
SPI[1]_SCS[2]/
SD2_SDCD		 AF5 I/O IPU
DVDD		 UART0, UART4, SPI[1], SD2
PINCNTL73
DSIS: 1		 DCAN1 receive data pin.
UART0_CTS/
UART4_RXD/
DCAN1_TX/
SPI[1]_SCS[3]/
SD0_SDCD		 AE6 I/O IPU
DVDD		 UART0, UART4, SPI[1], SD0
PINCNTL72
DSIS: 1		 DCAN1 transmit data pin.
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS = De-selected Input State
(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the Internal Pull after Reset. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see Section 3.5.1, Pullup/Pulldown Resistors and Section 6.3.17, Pin Behaviors at Reset.
(3) Specifies the operating I/O supply voltage for each signal

2.11.4 DDR2/DDR3 Memory Controller

Table 2-4 DDR2/DDR3 Memory Controller 0 Terminal Functions

SIGNAL TYPE(1) OTHER(2) (3) DESCRIPTION
NAME NO.
DDR2/DDR3 Memory Controller 0 (DDR[0])
DDR[0]_CLK B16 O IPD/DIS
DVDD_DDR[0]		 DDR[0] Clock
The internal pulldown (IPD) is enabled for this pin when the device is in reset and the IPD is disabled (DIS) when reset is released.
DDR[0]_CLK A16 O IPU/DIS
DVDD_DDR[0]		 DDR[0] Negative Clock
The internal pullup (IPU) is enabled for this pin when the device is in reset and the IPU is disabled (DIS) when reset is released.
DDR[0]_CKE H18 O IPD
DVDD_DDR[0]		 DDR[0] Clock Enable
DDR[0]_WE C17 O IPU/DIS
DVDD_DDR[0]		 DDR[0] Write Enable
The internal pullup (IPU) is enabled for this pin when the device is in reset and the IPU is disabled (DIS) when reset is released.
DDR[0]_CS[0] F18 O IPU/DIS
DVDD_DDR[0]		 DDR[0] Chip Select 0
The internal pullup (IPU) is enabled for this pin when the device is in reset and the IPU is disabled (DIS) when reset is released.
DDR[0]_CS[1] G17 O IPU/DIS
DVDD_DDR[0]		 DDR[0] Chip Select 1
The internal pullup (IPU) is enabled for this pin when the device is in reset and the IPU is disabled (DIS) when reset is released.
DDR[0]_RAS B18 O IPU/DIS
DVDD_DDR[0]		 DDR[0] Row Address Strobe output
The internal pullup (IPU) is enabled for this pin when the device is in reset and the IPU is disabled (DIS) when reset is released.
DDR[0]_CAS C18 O IPU/DIS
DVDD_DDR[0]		 DDR[0] Column Address Strobe output
The internal pullup (IPU) is enabled for this pin when the device is in reset and the IPU is disabled (DIS) when reset is released.
DDR[0]_DQM[3] F20 O IPU/IPD
DVDD_DDR[0]		 DDR[0] Data Mask outputs
DDR[0]_DQM[3]: For upper byte data bus DDR[0]_D[31:24]
DDR[0]_DQM[2]: For DDR[0]_D[23:16]
DDR[0]_DQM[1]: For DDR[0]_D[15:8]
DDR[0]_DQM[0]: For lower byte data bus DDR[0]_D[7:0]

The internal pullup (IPU) is enabled for these pins when the device is in reset and switches to an IPD enabled when reset is released.
DDR[0]_DQM[2] C24 O IPU/IPD
DVDD_DDR[0]
DDR[0]_DQM[1] B28 O IPU/IPD
DVDD_DDR[0]
DDR[0]_DQM[0] E28 O IPU/IPD
DVDD_DDR[0]
DDR[0]_DQS[3] B21 I/O IPD
DVDD_DDR[0]		 Data strobe input/outputs for each byte of the 32-bit data bus. They are outputs to the DDR[0] memory when writing and inputs when reading. They are used to synchronize the data transfers.
DDR[0]_DQS[3]: For upper byte data bus DDR[0]_D[31:24]
DDR[0]_DQS[2]: For DDR[0]_D[23:16]
DDR[0]_DQS[1]: For DDR[0]_D[15:8]
DDR[0]_DQS[0]: For lower byte data bus DDR[0]_D[7:0]

DDR[0]_DQS[2] B23 I/O IPD
DVDD_DDR[0]
DDR[0]_DQS[1] B26 I/O IPD
DVDD_DDR[0]
DDR[0]_DQS[0] D28 I/O IPD
DVDD_DDR[0]
DDR[0]_DQS[3] A21 I/O IPU
DVDD_DDR[0]		 Complementary data strobe input/outputs for each byte of the 32-bit data bus. They are outputs to the DDR[0] memory when writing and inputs when reading. They are used to synchronize the data transfers.
DDR[0]_DQS[3]: For upper byte data bus DDR[0]_D[31:24]
DDR[0]_DQS[2]: For DDR[0]_D[23:16]
DDR[0]_DQS[1]: For DDR[0]_D[15:8]
DDR[0]_DQS[0]: For lower byte data bus DDR[0]_D[7:0]

DDR[0]_DQS[2] A23 I/O IPU
DVDD_DDR[0]
DDR[0]_DQS[1] A26 I/O IPU
DVDD_DDR[0]
DDR[0]_DQS[0] D27 I/O IPU
DVDD_DDR[0]
DDR[0]_ODT[0] G18 O IPD/DIS
DVDD_DDR[0]		 DDR[0] On-Die Termination for Chip Select 0.
The internal pulldown (IPD) is enabled for this pin when the device is in reset and the IPD is disabled (DIS) when reset is released.
DDR[0]_ODT[1] H19 O IPD/DIS
DVDD_DDR[0]		 DDR[0] On-Die Termination for Chip Select 1.
The internal pulldown (IPD) is enabled for this pin when the device is in reset and the IPD is disabled (DIS) when reset is released.
DDR[0]_RST G19 O IPD/DIS
DVDD_DDR[0]		 DDR[0] Reset output

The internal pulldown (IPD) is enabled for this pin when the device is in reset and the IPD is disabled (DIS) when reset is released.
DDR[0]_BA[2] A18 O IPU/DIS
DVDD_DDR[0]		 DDR[0] Bank Address outputs

The internal pullup (IPU) is enabled for these pins when the device is in reset and the IPU is disabled (DIS) when reset is released.
DDR[0]_BA[1] A20 O IPU/DIS
DVDD_DDR[0]
DDR[0]_BA[0] F15 O IPU/DIS
DVDD_DDR[0]
DDR[0]_A[14] F16 O IPU/DIS
DVDD_DDR[0]		 DDR[0] Address Bus

The internal pullup (IPU) is enabled for these pins when the device is in reset and the IPU is disabled (DIS) when reset is released.
DDR[0]_A[13] F17 O IPU/DIS
DVDD_DDR[0]
DDR[0]_A[12] E17 O IPU/DIS
DVDD_DDR[0]
DDR[0]_A[11] D17 O IPU/DIS
DVDD_DDR[0]
DDR[0]_A[10] A19 O IPU/DIS
DVDD_DDR[0]
DDR[0]_A[9] C15 O IPU/DIS
DVDD_DDR[0]
DDR[0]_A[8] B15 O IPU/DIS
DVDD_DDR[0]
DDR[0]_A[7] E18 O IPU/DIS
DVDD_DDR[0]
DDR[0]_A[6] A15 O IPU/DIS
DVDD_DDR[0]
DDR[0]_A[5] B17 O IPU/DIS
DVDD_DDR[0]
DDR[0]_A[4] D15 O IPU/DIS
DVDD_DDR[0]
DDR[0]_A[3] E15 O IPU/DIS
DVDD_DDR[0]
DDR[0]_A[2] D18 O IPU/DIS
DVDD_DDR[0]
DDR[0]_A[1] F19 O IPU/DIS
DVDD_DDR[0]
DDR[0]_A[0] B19 O IPU/DIS
DVDD_DDR[0]
DDR[0]_D[31] B20 I/O IPD
DVDD_DDR[0]		 DDR[0] Data Bus
DDR[0]_D[30] D21 I/O IPD
DVDD_DDR[0]
DDR[0]_D[29] C21 I/O IPD
DVDD_DDR[0]
DDR[0]_D[28] C20 I/O IPD
DVDD_DDR[0]
DDR[0]_D[27] A22 I/O IPD
DVDD_DDR[0]
DDR[0]_D[26] G20 I/O IPD
DVDD_DDR[0]
DDR[0]_D[25] F21 I/O IPD
DVDD_DDR[0]
DDR[0]_D[24] H20 I/O IPD
DVDD_DDR[0]
DDR[0]_D[23] B22 I/O IPD
DVDD_DDR[0]
DDR[0]_D[22] C23 I/O IPD
DVDD_DDR[0]
DDR[0]_D[21] E23 I/O IPD
DVDD_DDR[0]
DDR[0]_D[20] D23 I/O IPD
DVDD_DDR[0]
DDR[0]_D[19] G21 I/O IPD
DVDD_DDR[0]
DDR[0]_D[18] H21 I/O IPD
DVDD_DDR[0]
DDR[0]_D[17] F22 I/O IPD
DVDD_DDR[0]
DDR[0]_D[16] B24 I/O IPD
DVDD_DDR[0]
DDR[0]_D[15] A24 I/O IPD
DVDD_DDR[0]		 DDR[0] Data Bus
DDR[0]_D[14] A25 I/O IPD
DVDD_DDR[0]
DDR[0]_D[13] D24 I/O IPD
DVDD_DDR[0]
DDR[0]_D[12] B25 I/O IPD
DVDD_DDR[0]
DDR[0]_D[11] A27 I/O IPD
DVDD_DDR[0]
DDR[0]_D[10] C26 I/O IPD
DVDD_DDR[0]
DDR[0]_D[9] C25 I/O IPD
DVDD_DDR[0]
DDR[0]_D[8] C27 I/O IPD
DVDD_DDR[0]
DDR[0]_D[7] C28 I/O IPD
DVDD_DDR[0]
DDR[0]_D[6] D26 I/O IPD
DVDD_DDR[0]
DDR[0]_D[5] E25 I/O IPD
DVDD_DDR[0]
DDR[0]_D[4] F24 I/O IPD
DVDD_DDR[0]
DDR[0]_D[3] F25 I/O IPD
DVDD_DDR[0]
DDR[0]_D[2] E26 I/O IPD
DVDD_DDR[0]
DDR[0]_D[1] F26 I/O IPD
DVDD_DDR[0]
DDR[0]_D[0] E27 I/O IPD
DVDD_DDR[0]
DDR[0]_VTP B27 I –
DVDD_DDR[0]		 DDR VTP Compensation Resistor Connection
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS = De-selected Input State
(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the Internal Pull during and after Reset. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see Section 3.5.1, Pullup/Pulldown Resistors and Section 6.3.17, Pin Behaviors at Reset.
(3) Specifies the operating I/O supply voltage for each signal

Table 2-5 DDR2/DDR3 Memory Controller 1 Terminal Functions

SIGNAL TYPE(1) OTHER(2) (3) DESCRIPTION
NAME NO.
DDR2/DDR3 Memory Controller 1 (DDR[1])
DDR[1]_CLK B13 O IPD/DIS
DVDD_DDR[1]		 DDR[1] Clock
The internal pulldown (IPD) is enabled for this pin when the device is in reset and the IPD is disabled (DIS) when reset is released.
DDR[1]_CLK A13 O IPU/DIS
DVDD_DDR[1]		 DDR[1] Negative Clock
The internal pullup (IPU) is enabled for this pin when the device is in reset and the IPU is disabled (DIS) when reset is released.
DDR[1]_CKE H11 O IPD
DVDD_DDR[1]		 DDR[1] Clock Enable
DDR[1]_WE E12 O IPU/DIS
DVDD_DDR[1]		 DDR[1] Write Enable
The internal pullup (IPU) is enabled for this pin when the device is in reset and the IPU is disabled (DIS) when reset is released.
DDR[1]_CS[0] G12 O IPU/DIS
DVDD_DDR[1]		 DDR[1] Chip Select 0
The internal pullup (IPU) is enabled for this pin when the device is in reset and the IPU is disabled (DIS) when reset is released.
DDR[1]_CS[1] G11 O IPU/DIS
DVDD_DDR[1]		 DDR[1] Chip Select 1
The internal pullup (IPU) is enabled for this pin when the device is in reset and the IPU is disabled (DIS) when reset is released.
DDR[1]_RAS C12 O IPU/DIS
DVDD_DDR[1]		 DDR[1] Row Address Strobe output
The internal pullup (IPU) is enabled for this pin when the device is in reset and the IPU is disabled (DIS) when reset is released.
DDR[1]_CAS F13 O IPU/DIS
DVDD_DDR[1]		 DDR[1] Column Address Strobe output
The internal pullup (IPU) is enabled for this pin when the device is in reset and the IPU is disabled (DIS) when reset is released.
DDR[1]_DQM[3] G9 O IPU/IPD
DVDD_DDR[1]		 DDR[1] Data Mask outputs
DDR[1]_DQM[3]: For upper byte data bus DDR[1]_D[31:24]
DDR[1]_DQM[2]: For DDR[1]_D[23:16]
DDR[1]_DQM[1]: For DDR[1]_D[15:8]
DDR[1]_DQM[0]: For lower byte data bus DDR[1]_D[7:0]

The internal pullup (IPU) is enabled for these pins when the device is in reset and switches to an IPD enabled when reset is released.
DDR[1]_DQM[2] G8 O IPU/IPD
DVDD_DDR[1]
DDR[1]_DQM[1] B2 O IPU/IPD
DVDD_DDR[1]
DDR[1]_DQM[0] F4 O IPU/IPD
DVDD_DDR[1]
DDR[1]_DQS[3] B8 I/O IPD
DVDD_DDR[1]		 Data strobe input/outputs for each byte of the 32-bit data bus. They are outputs to the DDR[1] memory when writing and inputs when reading. They are used to synchronize the data transfers.
DDR[1]_DQS[3]: For upper byte data bus DDR[1]_D[31:24]
DDR[1]_DQS[2]: For DDR[1]_D[23:16]
DDR[1]_DQS[1]: For DDR[1]_D[15:8]
DDR[1]_DQS[0]: For lower byte data bus DDR[1]_D[7:0]
DDR[1]_DQS[2] A6 I/O IPD
DVDD_DDR[1]
DDR[1]_DQS[1] B3 I/O IPD
DVDD_DDR[1]
DDR[1]_DQS[0] D1 I/O IPD
DVDD_DDR[1]
DDR[1]_DQS[3] A8 I/O IPU
DVDD_DDR[1]		 Complementary data strobe input/outputs for each byte of the 32-bit data bus. They are outputs to the DDR[1] memory when writing and inputs when reading. They are used to synchronize the data transfers.
DDR[1]_DQS[3]: For upper byte data bus DDR[1]_D[31:24]
DDR[1]_DQS[2]: For DDR[1]_D[23:16]
DDR[1]_DQS[1]: For DDR[1]_D[15:8]
DDR[1]_DQS[0]: For lower byte data bus DDR[1]_D[7:0]

DDR[1]_DQS[2] B6 I/O IPU
DVDD_DDR[1]
DDR[1]_DQS[1] A3 I/O IPU
DVDD_DDR[1]
DDR[1]_DQS[0] D2 I/O IPU
DVDD_DDR[1]
DDR[1]_ODT[0] H10 O IPD/DIS
DVDD_DDR[1]		 DDR[1] On-Die Termination for Chip Select 0.
The internal pulldown (IPD) is enabled for this pin when the device is in reset and the IPD is disabled (DIS) when reset is released.
DDR[1]_ODT[1] F11 O IPD/DIS
DVDD_DDR[1]		 DDR[1] On-Die Termination for Chip Select 1.
The internal pulldown (IPD) is enabled for this pin when the device is in reset and the IPD is disabled (DIS) when reset is released.
DDR[1]_RST G10 O IPD/DIS
DVDD_DDR[1]		 DDR[1] Reset output.
The internal pulldown (IPD) is enabled for this pin when the device is in reset and the IPD is disabled (DIS) when reset is released.
DDR[1]_BA[2] D12 O IPU/DIS
DVDD_DDR[1]		 DDR[1] Bank Address outputs

The internal pullup (IPU) is enabled for these pins when the device is in reset and the IPU is disabled (DIS) when reset is released.
DDR[1]_BA[1] A10 O IPU/DIS
DVDD_DDR[1]
DDR[1]_BA[0] F14 O IPU/DIS
DVDD_DDR[1]
DDR[1]_A[14] D11 O IPU/DIS
DVDD_DDR[1]		 DDR[1] Address Bus

The internal pullup (IPU) is enabled for these pins when the device is in reset and the IPU is disabled (DIS) when reset is released.
DDR[1]_A[13] E11 O IPU/DIS
DVDD_DDR[1]
DDR[1]_A[12] B10 O IPU/DIS
DVDD_DDR[1]
DDR[1]_A[11] A11 O IPU/DIS
DVDD_DDR[1]
DDR[1]_A[10] F12 O IPU/DIS
DVDD_DDR[1]
DDR[1]_A[9] C14 O IPU/DIS
DVDD_DDR[1]
DDR[1]_A[8] E14 O IPU/DIS
DVDD_DDR[1]
DDR[1]_A[7] A9 O IPU/DIS
DVDD_DDR[1]
DDR[1]_A[6] D14 O IPU/DIS
DVDD_DDR[1]
DDR[1]_A[5] B12 O IPU/DIS
DVDD_DDR[1]
DDR[1]_A[4] B14 O IPU/DIS
DVDD_DDR[1]
DDR[1]_A[3] A14 O IPU/DIS
DVDD_DDR[1]
DDR[1]_A[2] C11 O IPU/DIS
DVDD_DDR[1]
DDR[1]_A[1] F10 O IPU/DIS
DVDD_DDR[1]
DDR[1]_A[0] B11 O IPU/DIS
DVDD_DDR[1]
DDR[1]_D[31] B9 I/O IPD
DVDD_DDR[1]		 DDR[1] Data Bus
DDR[1]_D[30] C8 I/O IPD
DVDD_DDR[1]
DDR[1]_D[29] D8 I/O IPD
DVDD_DDR[1]
DDR[1]_D[28] C9 I/O IPD
DVDD_DDR[1]
DDR[1]_D[27] A7 I/O IPD
DVDD_DDR[1]
DDR[1]_D[26] F8 I/O IPD
DVDD_DDR[1]
DDR[1]_D[25] H9 I/O IPD
DVDD_DDR[1]
DDR[1]_D[24] F9 I/O IPD
DVDD_DDR[1]
DDR[1]_D[23] B7 I/O IPD
DVDD_DDR[1]
DDR[1]_D[22] D6 I/O IPD
DVDD_DDR[1]
DDR[1]_D[21] E6 I/O IPD
DVDD_DDR[1]
DDR[1]_D[20] C6 I/O IPD
DVDD_DDR[1]
DDR[1]_D[19] B5 I/O IPD
DVDD_DDR[1]
DDR[1]_D[18] C5 I/O IPD
DVDD_DDR[1]
DDR[1]_D[17] F7 I/O IPD
DVDD_DDR[1]
DDR[1]_D[16] H8 I/O IPD
DVDD_DDR[1]
DDR[1]_D[15] A5 I/O IPD
DVDD_DDR[1]		 DDR[1] Data Bus
DDR[1]_D[14] A4 I/O IPD
DVDD_DDR[1]
DDR[1]_D[13] C4 I/O IPD
DVDD_DDR[1]
DDR[1]_D[12] B4 I/O IPD
DVDD_DDR[1]
DDR[1]_D[11] A2 I/O IPD
DVDD_DDR[1]
DDR[1]_D[10] C3 I/O IPD
DVDD_DDR[1]
DDR[1]_D[9] D5 I/O IPD
DVDD_DDR[1]
DDR[1]_D[8] C2 I/O IPD
DVDD_DDR[1]
DDR[1]_D[7] C1 I/O IPD
DVDD_DDR[1]
DDR[1]_D[6] D3 I/O IPD
DVDD_DDR[1]
DDR[1]_D[5] E4 I/O IPD
DVDD_DDR[1]
DDR[1]_D[4] F5 I/O IPD
DVDD_DDR[1]
DDR[1]_D[3] E1 I/O IPD
DVDD_DDR[1]
DDR[1]_D[2] E2 I/O IPD
DVDD_DDR[1]
DDR[1]_D[1] F3 I/O IPD
DVDD_DDR[1]
DDR[1]_D[0] E3 I/O IPD
DVDD_DDR[1]
DDR[1]_VTP B1 I –
DVDD_DDR[1]		 DDR[1] VTP Compensation Resistor Connection
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS = De-selected Input State
(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the Internal Pull during and after Reset. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see Section 3.5.1, Pullup/Pulldown Resistors and Section 6.3.17, Pin Behaviors at Reset.
(3) Specifies the operating I/O supply voltage for each signal

2.11.5 EDMA

Table 2-6 EDMA Terminal Functions

SIGNAL TYPE(1) OTHER(2) (3) MUXED DESCRIPTION
NAME NO.
EDMA
AUD_CLKIN1/
MCA[0]_AXR[8]/
MCA[1]_AHCLKX/
MCA[4]_AHCLKX/
EDMA_EVT3/
TIM2_IO/
GP0[8]		 R5 I IPD
DVDD		 AUD_CLKIN1, MCA[0], MCA[1], MCA[4], TIMER2, GP0
PINCNTL15
DSIS: PIN
MM: MUX1		 External EDMA Event 3
GPMC_CLK/
GPMC_CS[5]/
GPMC_WAIT[1]/
CLKOUT1/
EDMA_EVT3/
TIM4_IO/
GP1[27]		 R26 I IPU
DVDD_GPMC		 GPMC, CLKOUT1, TIMER4, GP1
PINCNTL127
DSIS: PIN
MM: MUX0
AUD_CLKIN2/
MCA[0]_AXR[9]/
MCA[2]_AHCLKX/
MCA[5]_AHCLKX/
EDMA_EVT2/
TIM3_IO/
GP0[9]		 H1 I IPD
DVDD		 AUD_CLKIN2, MCA[0], MCA[2]. MCA[5], TIMER3, GP0
PINCNTL16
DSIS: PIN
MM: MUX1		 External EDMA Event 2
GPMC_BE[0]_CLE/
GPMC_A[25]/
EDMA_EVT2/
TIM6_IO/
GP1[29]		 U27 I IPD
DVDD_GPMC		 GPMC, TIMER6, GP1
PINCNTL131
DSIS: PIN
MM: MUX0
SPI[0]_SCS[1]/
SD1_SDCD/
SATA_ACT0_LED/
EDMA_EVT1/
TIM4_IO/
GP1[6]		 AE5 I IPU
DVDD		 SPI[0], SD1, SATA, TIMER4, GP1
PINCNTL80
DSIS: PIN
MM: MUX1		 External EDMA Event 1
GPMC_BE[1]/
GPMC_A[24]/
EDMA_EVT1/
TIM7_IO/
GP1[30]		 V28 I IPD
DVDD_GPMC		 GPMC, TIMER7, GP1
PINCNTL132
DSIS: PIN
MM: MUX0
SD2_DAT[4]/
GPMC_A[27]/
GPMC_A[23]/
GPMC_CS[7]/
EDMA_EVT0/
TIM7_IO/
GP1[22]		 R24 I IPU
DVDD_GPMC		 SD2, GPMC, TIMER7, GP1
PINCNTL116
DSIS: PIN
MM: MUX1		 External EDMA Event 0
GPMC_WAIT[0]/
GPMC_A[26]/
EDMA_EVT0/
GP1[31]		 W28 I IPU
DVDD_GPMC		 GPMC, GP1
PINCNTL133
DSIS: PIN
MM: MUX0
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS = De-selected Input State
(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the Internal Pull after Reset. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see Section 3.5.1, Pullup/Pulldown Resistors and the Section 6.3.17, Pin Behaviors at Reset.
(3) Specifies the operating I/O supply voltage for each signal

2.11.6 EMAC [(R)(G)MII Modes] and MDIO

Table 2-7 EMAC[0] Terminal Functions [(R)(G)MII]

SIGNAL TYPE(1) OTHER(2) (3) MUXED DESCRIPTION
NAME NO.
EMAC[0] (G)MII Mode
An EMAC bootmode must be selected via the BTMODE[4:0] pins. Once the EMAC bootmode is selected, the BTMODE[9:8] pins determine the Ethernet PHY Mode Selection (for example, 00b is MII mode). For more detailed information on EMAC bootmodes and Ethernet PHY Mode selection, see Section 3.2.6, Ethernet PHY Mode Selection.
These pin functions are available only when GMII or MII modes are selected.
EMAC[0]_MCOL/
EMAC[0]_RGRXCTL/
VIN[1]B_D[1]/
EMAC[0]_RMRXD[0]/
GP3[24]		 L23 I IPD
DVDD_GPMC		 EMAC[0], VIN[1]B, GP3
PINCNTL236
DSIS: 0		 [G]MII Collision Detect (Sense) input
EMAC[0]_MCRS/
EMAC[0]_RGRXD[2]/
VIN[1]B_D[2]/
EMAC[0]_RMRXD[1]/
GP3[25]		 R25 I IPD
DVDD_GPMC		 EMAC[0], VIN[1]B, GP3
PINCNTL237
DSIS: 0		 [G]MII Carrier Sense input
EMAC[0]_GMTCLK/
EMAC[1]_RGRXC/
GPMC_A[6]/
SPI[2]_D[1]		 K23 O IPD
DVDD_GPMC		 EMAC[1], GPMC, SPI[2]
PINCNTL249
DSIS: N/A		 GMII Source Synchronous Transmit Clock
EMAC[0]_MRCLK/
EMAC[0]_RGTXC/
VIN[1]B_D[4]/
EMAC[0]_RMCRSDV/
SPI[3]_SCS[2]/
GP3[27]		 H27 I IPD
DVDD_GPMC		 EMAC[0], VIN[1]B, SPI[3], GP3
PINCNTL239
DSIS: 0		 [G]MII Receive Clock
EMAC[0]_MRXD[7]/
EMAC[0]_RGTXD[1]/
GPMC_A[4]/
SPI[2]_SCS[3]		 G27 I IPD
DVDD_GPMC		 EMAC[0], GPMC, SPI[2]
PINCNTL247
DSIS: PIN		 [G]MII Receive Data [7:0]. For 1000 EMAC GMII operation, EMAC[0]_RXD[7:0] are used. For 10/100 EMAC MII operation, only EMAC[0]_RXD[3:0] are used.
EMAC[0]_MRXD[6]/
EMAC[0]_RGTXD[2]/
GPMC_A[3]/
UART5_RTS		 F28 EMAC[0], GPMC, UART5
PINCNTL246
DSIS: PIN
EMAC[0]_MRXD[5]/
EMAC[0]_RGTXD[3]/
GPMC_A[2]/
UART5_CTS		 H26 EMAC[0], GPMC, UART5
PINCNTL245
DSIS: PIN
EMAC[0]_MRXD[4]/
EMAC[0]_RGRXD[3]/
GPMC_A[1]/
UART5_TXD		 T23 EMAC[0], GPMC, UART5
PINCNTL244
DSIS: PIN
EMAC[0]_MRXD[3]/
EMAC[1]_RGRXCTL/
GPMC_A[27]/
GPMC_A[26]/
GPMC_A[0]/
UART5_RXD 		J25 EMAC[1], GPMC, UART5
PINCNTL243
DSIS: PIN
EMAC[0]_MRXD[2]/
EMAC[0]_RGRXD[1]/
VIN[1]B_D[7]/
EMAC[0]_RMTXEN/
GP3[30]		 R23 EMAC[0], VIN[1]B, GP3
PINCNTL242
DSIS: PIN
EMAC[0]_MRXD[1]/
EMAC[0]_RGRXD[0]/
VIN[1]B_D[6]/
EMAC[0]_RMTXD[1]/
GP3[29]		 P23 EMAC[0], VIN[1]B, GP3
PINCNTL241
DSIS: PIN
EMAC[0]_MRXD[0]/
EMAC[0]_RGTXD[0]/
VIN[1]B_D[5]/
EMAC[0]_RMTXD[0]/
GP3[28]		 G28 EMAC[0], VIN[1]B, GP3
PINCNTL240
DSIS: PIN
EMAC[0]_MRXDV/
EMAC[1]_RGRXD[1]/
GPMC_A[5]/
SPI[2]_SCLK		 K22 I IPD
DVDD_GPMC		 EMAC[1], GPMC, SPI[2]
PINCNTL248
DSIS: 0		 [G]MII Receive Data Valid input
EMAC[0]_MRXER/
EMAC[0]_RGTXCTL/
VIN[1]B_D[3]/
EMAC[0]_RMRXER/
GP3[26]		 J26 I IPD
DVDD_GPMC		 EMAC[0], VIN[1]B, GP3
PINCNTL238
DSIS: 0		 [G]MII Receive Data Error input
EMAC[0]_MTCLK/
EMAC[0]_RGRXC/
VIN[1]B_D[0]/
SPI[3]_SCS[3]/
I2C[2]_SDA/
GP3[23]		 L24 I IPD
DVDD_GPMC		 EMAC[0], VIN[1]B, SPI[3], I2C[2], GP3
PINCNTL235
DSIS: 0		 [G]MII Transmit Clock input
EMAC[0]_MTXD[7]/
EMAC[1]_RGTXD[3]/
EMAC[1]_RMTXD[1]/
GPMC_A[14]/
UART1_CTS		 H24 O IPD
DVDD_GPMC		 EMAC[1], GPMC, UART1
PINCNTL257
DSIS: N/A		 [G]MII Transmit Data [7:0]. For 1000 EMAC GMII operation, EMAC[0]_TXD[7:0] are used. For 10/100 EMAC MII operation, only EMAC[0]_TXD[3:0] are used.
EMAC[0]_MTXD[6]/
EMAC[1]_RGRXD[0]/
EMAC[1]_RMTXD[0]/
GPMC_A[13]/
UART1_TXD		 J22 EMAC[1], GPMC, UART1
PINCNTL256
DSIS: N/A
EMAC[0]_MTXD[5]/
EMAC[1]_RGTXC/
EMAC[1]_RMCRSDV/
GPMC_A[12]/
UART1_RXD		 F27 EMAC[1], GPMC, UART1
PINCNTL255
DSIS: N/A
EMAC[0]_MTXD[4]/
EMAC[1]_RGTXD[2]/
EMAC[1]_RMRXER/
GPMC_A[11]/
UART4_RTS		 G23 EMAC[1], GPMC, UART4
PINCNTL254
DSIS: N/A
EMAC[0]_MTXD[3]/
EMAC[1]_RGTXD[0]/
EMAC[1]_RMRXD[1]/
GPMC_A[10]/
UART4_CTS		 H23 EMAC[1], GPMC, UART4
PINCNTL253
DSIS: N/A
EMAC[0]_MTXD[2]/
EMAC[1]_RGTXCTL/
EMAC[1]_RMRXD[0]/
GPMC_A[9]/
UART4_TXD		 H22 EMAC[1], GPMC, UART4
PINCNTL252
DSIS: N/A
EMAC[0]_MTXD[1]/
EMAC[1]_RGTXD[1]/
GPMC_A[8]/
UART4_RXD		 H25 EMAC[1], GPMC, UART4
PINCNTL251
DSIS: N/A
EMAC[0]_MTXD[0]/
EMAC[1]_RGRXD[3]/
GPMC_A[7]/
SPI[2]_D[0]		 J24 EMAC[1], GPMC, UART4
PINCNTL250
DSIS: N/A
EMAC[0]_MTXEN/
EMAC[1]_RGRXD[2]/
EMAC[1]_RMTXEN/
GPMC_A[15]/
UART1_RTS		 J23 O IPD
DVDD_GPMC		 EMAC[1], GPMC, UART4
PINCNTL258
DSIS: N/A		 [G]MII Transmit Data Enable output
EMAC[0] RMII Mode
An EMAC bootmode must be selected via the BTMODE[4:0] pins. Once the EMAC bootmode is selected, the BTMODE[9:8] pins determine the Ethernet PHY Mode Selection (for example, 01b is RMII mode). For more detailed information on EMAC bootmodes and Ethernet PHY Mode selection, see Section 3.2.6, Ethernet PHY Mode Selection.
These pin functions are available only when RMII mode is selected.
EMAC_RMREFCLK/
TIM2_IO/
GP1[10]		 J27 I/O IPD
DVDD_GPMC		 TIMER2, GP1
PINCNTL232
DSIS: PIN		 RMII Reference Clock (EMAC[0] and EMAC[1] RMII mode)
Regardless of EMAC[0] RMII Mode, the GMII_EN bit in the MACCONTROL register, of the Control Module, configures the RMREFCLK pin function as an INPUT or OUTPUT clock reference. During RMII ROM Boot, the RMREFCLK pin function is configured as an OUTPUT clock reference (driving 50 MHz).
EMAC[0]_MRCLK/
EMAC[0]_RGTXC/
VIN[1]B_D[4]/
EMAC[0]_RMCRSDV/
SPI[3]_SCS[2]/
GP3[27]		 H27 I IPD
DVDD_GPMC		 EMAC[0], VIN[1]B, SPI[3], GP3
PINCNTL239
DSIS: 0		 RMII Carrier Sense input
EMAC[0]_MCRS/
EMAC[0]_RGRXD[2]/
VIN[1]B_D[2]/
EMAC[0]_RMRXD[1]/
GP3[25]		 R25 I IPD
DVDD_GPMC		 EMAC[0], VIN[1]B, SPI[3], GPI3
PINCNTL237
DSIS: PIN		 RMII Receive Data [1:0]. For 10/100 EMAC RMII operation, EMAC[0]_RMRXD[1:0] are used.
EMAC[0]_MCOL/
EMAC[0]_RGRXCTL/
VIN[1]B_D[1]/
EMAC[0]_RMRXD[0]/
GP3[24]		 L23 I IPD
DVDD_GPMC		 EMAC[0], VIN[1]B, GP3
PINCNTL236
DSIS: PIN
EMAC[0]_MRXER/
EMAC[0]_RGTXCTL/
VIN[1]B_D[3]/
EMAC[0]_RMRXER/
GP3[26]		 J26 I IPD
DVDD_GPMC		 EMAC[0], VIN[1]B, GP3
PINCNTL238
DSIS: 0		 RMII Receive Data Error input
EMAC[0]_MRXD[1]/
EMAC[0]_RGRXD[0]/
VIN[1]B_D[6]/
EMAC[0]_RMTXD[1]/
GP3[29]		 P23 O IPD
DVDD_GPMC		 EMAC[0], VIN[1]B, GP3
PINCNTL241
DSIS: N/A		 RMII Transmit Data [7:0]. For 10/100 EMAC RMII operation, EMAC[0]_RMTXD[1:0] are used.
EMAC[0]_MRXD[0]/
EMAC[0]_RGTXD[0]/
VIN[1]B_D[5]/
EMAC[0]_RMTXD[0]/
GP3[28]		 G28 O IPD
DVDD_GPMC		 EMAC[0], VIN[1]B, GP3
PINCNTL240
DSIS: N/A
EMAC[0]_MRXD[2]/
EMAC[0]_RGRXD[1]/
VIN[1]B_D[7]/
EMAC[0]_RMTXEN/
GP3[30]		 R23 O IPD
DVDD_GPMC		 EMAC[0], VIN[1]B, GP3
PINCNTL242
DSIS: N/A		 RMII Transmit Data Enable output
EMAC[0] RGMII Mode
An EMAC bootmode must be selected via the BTMODE[4:0] pins. Once the EMAC bootmode is selected, the BTMODE[9:8] pins determine the Ethernet PHY Mode Selection (for example, 10b is RGMII mode). For more detailed information on EMAC bootmodes and Ethernet PHY Mode selection, see Section 3.2.6, Ethernet PHY Mode Selection
These pin functions are available only when RGMII mode is selected.
EMAC[0]_MTCLK/
EMAC[0]_RGRXC/
VIN[1]B_D[0]/
SPI[3]_SCS[3]/
I2C[2]_SDA/
GP3[23]		 L24 I IPD
DVDD_GPMC		 EMAC[0], VIN[1]B, SPI[3], I2C[2], GP3
PINCNTL235
DSIS: PIN		 RGMII Receive Clock
EMAC[0]_MCOL/
EMAC[0]_RGRXCTL/
VIN[1]B_D[1]/
EMAC[0]_RMRXD[0]/
GP3[24]		 L23 I IPD
DVDD_GPMC		 EMAC[0], VIN[1]B, GP3
PINCNTL236
DSIS: PIN		 RGMII Receive Control
EMAC[0]_MRXD[4]/
EMAC[0]_RGRXD[3]/
GPMC_A[1]/
UART5_TXD		 T23 I IPD
DVDD_GPMC		 EMAC[0], GPMC, UART5
PINCNTL244
DSIS: PIN		 RGMII Receive Data [3:0]
EMAC[0]_MCRS/
EMAC[0]_RGRXD[2]/
VIN[1]B_D[2]/
EMAC[0]_RMRXD[1]/
GP3[25]		 R25 I IPD
DVDD_GPMC		 EMAC[0], VIN[1]B, GP3
PINCNTL237
DSIS: PIN
EMAC[0]_MRXD[2]/
EMAC[0]_RGRXD[1]/
VIN[1]B_D[7]/
EMAC[0]_RMTXEN/
GP3[30]		 R23 I IPD
DVDD_GPMC		 EMAC[0], VIN[1]B, GP3
PINCNTL242
DSIS: PIN
EMAC[0]_MRXD[1]/
EMAC[0]_RGRXD[0]/
VIN[1]B_D[6]/
EMAC[0]_RMTXD[1]/
GP3[29]		 P23 I IPD
DVDD_GPMC		 EMAC[0], VIN[1]B, GP3
PINCNTL241
DSIS: PIN
EMAC[0]_MRCLK/
EMAC[0]_RGTXC/
VIN[1]B_D[4]/
EMAC[0]_RMCRSDV/
SPI[3]_SCS[2]/
GP3[27]		 H27 O IPD
DVDD_GPMC		 EMAC[0], VIN[1]B, SPI[3], GP3
PINCNTL239
DSIS: N/A		 RGMII Transmit Clock
EMAC[0]_MRXER/
EMAC[0]_RGTXCTL/
VIN[1]B_D[3]/
EMAC[0]_RMRXER/
GP3[26]		 J26 O IPD
DVDD_GPMC		 EMAC[0], VIN[1]B, GP3
PINCNTL238
DSIS: N/A		 RGMII Transmit Enable
EMAC[0]_MRXD[5]/
EMAC[0]_RGTXD[3]/
GPMC_A[2]/
UART5_CTS		 H26 O IPD
DVDD_GPMC		 EMAC[0], GPMC, UART5
PINCNTL245
DSIS: N/A		 RGMII Transmit Data [3:0]
EMAC[0]_MRXD[6]/
EMAC[0]_RGTXD[2]/
GPMC_A[3]/
UART5_RTS		 F28 O IPD
DVDD_GPMC		 EMAC[0], GPMC, UART5
PINCNTL246
DSIS: N/A
EMAC[0]_MRXD[7]/
EMAC[0]_RGTXD[1]/
GPMC_A[4]/
SPI[2]_SCS[3]		 G27 O IPD
DVDD_GPMC		 EMAC[0], GPMC, SPI[2]
PINCNTL247
DSIS: N/A
EMAC[0]_MRXD[0]/
EMAC[0]_RGTXD[0]/
VIN[1]B_D[5]/
EMAC[0]_RMTXD[0]/
GP3[28]		 G28 O IPD
DVDD_GPMC		 EMAC[0], VIN[1]B, GP3
PINCNTL240
DSIS: N/A
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS = De-selected Input State
(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the Internal Pull after Reset. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see Section 3.5.1, Pullup/Pulldown Resistors and Section 6.3.17, Pin Behaviors at Reset.
(3) Specifies the operating I/O supply voltage for each signal

Table 2-8 EMAC[1] Terminal Functions [(R)(G)MII]

SIGNAL TYPE(1) OTHER(2) (3) MUXED DESCRIPTION
NAME NO.
EMAC[1] (G)MII Mode
An EMAC bootmode must be selected via the BTMODE[4:0] pins. Once the EMAC bootmode is selected, the BTMODE[9:8] pins determine the Ethernet PHY Mode Selection (for example, 00b is MII mode). For more detailed information on EMAC bootmodes and Ethernet PHY Mode selection, see Section 3.2.6, Ethernet PHY Mode Selection.

These pin functions are available only when GMII and MII modes are selected.
VOUT[1]_HSYNC/
EMAC[1]_MCOL/
VIN[1]A_VSYNC/
SPI[3]_D[1]/
UART3_RTS/
GP2[29]		 AC24 I IPD
DVDD		 VOUT[1], VIN[1]A, SPI[3], UART3, GP2
PINCNTL205
DSIS: 0		 [G]MII Collision Detect (Sense) input
VOUT[1]_VSYNC/
EMAC[1]_MCRS/
VIN[1]A_FLD/
VIN[1]A_DE/
SPI[3]_D[0]/
UART3_CTS/
GP2[30]		 AA23 I IPD
DVDD		 VOUT[1], VIN[1]A, SPI[3], UART3, GP2
PINCNTL206
DSIS: 0		 [G]MII Carrier Sense input
VOUT[1]_G_Y_YC[6]/
EMAC[1]_GMTCLK/
VIN[1]A_D[11]/
GP3[10]		 AH27 O IPD
DVDD		 VOUT[1], VIN[1]A, GP3
PINCNTL218
DSIS: N/A		 GMII Source Synchronous Transmit Clock
VOUT[1]_B_CB_C[3]/
EMAC[1]_MRCLK/
VIN[1]A_D[0]/
UART4_CTS/
GP3[0]		 AH25 I IPD
DVDD		 VOUT[1], VIN[1]A, UART4, GP3
PINCNTL208
DSIS: 0		 [G]MII Receive Clock
VOUT[1]_G_Y_YC[4]/
EMAC[1]_MRXD[7]/
VIN[1]A_D[9]/
GP3[8]		 W22 I IPD
DVDD		 VOUT[1], VIN[1]A, GP3
PINCNTL216
DSIS: PIN		 [G]MII Receive Data [7:0]. For 1000 EMAC GMII operation, EMAC[0]_RXD[7:0] are used. For 10/100 EMAC MII operation, only EMAC[0]_RXD[3:0] are used.
VOUT[1]_G_Y_YC[3]/
EMAC[1]_MRXD[6]/
VIN[1]A_D[8]/
GP3[7]		 Y23 VOUT[1], VIN[1]A, GP3
PINCNTL215
DSIS: PIN
VOUT[1]_B_CB_C[9]/
EMAC[1]_MRXD[5]/
VIN[1]A_D[6]/
I2C[3]_SDA/
GP3[6]		 AA24 VOUT[1], VIN[1]A, I2C[3], GP3
PINCNTL214
DSIS: PIN
VOUT[1]_B_CB_C[8]/
EMAC[1]_MRXD[4]/
VIN[1]A_D[5]/
I2C[3]_SCL/
GP3[5]		 AH26 VOUT[1], VIN[1]A, I2C[3], GP3
PINCNTL213
DSIS: PIN
VOUT[1]_B_CB_C[7]/
EMAC[1]_MRXD[3]/
VIN[1]A_D[4]/
UART3_TXD/
GP3[4]		 AC25 VOUT[1], VIN[1]A, UART3, GP3
PINCNTL212
DSIS: PIN
VOUT[1]_B_CB_C[6]/
EMAC[1]_MRXD[2]/
VIN[1]A_D[3]/
UART3_RXD/
GP3[3]		 AD25 VOUT[1], VIN[1]A, UART3, GP3
PINCNTL211
DSIS: PIN
VOUT[1]_B_CB_C[5]/
EMAC[1]_MRXD[1]/
VIN[1]A_D[2]/
UART4_TXD/
GP3[2]		 AF25 VOUT[1], VIN[1]A, UART4, GP3
PINCNTL210
DSIS: PIN
VOUT[1]_B_CB_C[4]/
EMAC[1]_MRXD[0]/
VIN[1]A_D[1]/
UART4_RXD/
GP3[1]		 AG25 VOUT[1], VIN[1]A, UART4, GP3
PINCNTL209
DSIS: PIN
VOUT[1]_G_Y_YC[5]/
EMAC[1]_MRXDV/
VIN[1]A_D[10]/
GP3[9]		 AG26 I IPD
DVDD		 VOUT[1], VIN[1]A, GP3
PINCNTL217
DSIS: 0		 [G]MII Receive Data Valid input
VOUT[1]_AVID/
EMAC[1]_MRXER/
VIN[1]A_CLK/
UART4_RTS/
TIM6_IO/
GP2[31]		 Y22 I IPD
DVDD		 VOUT[1], VIN[1]A, UART4, TIMER 6, GP2
PINCNTL207
DSIS: 0		 [G]MII Receive Data Error input
VOUT[1]_CLK/
EMAC[1]_MTCLK/
VIN[1]A_HSYNC/
GP2[28]		 AE24 I IPD
DVDD		 VOUT[1], VIN[1]A, GP2
PINCNTL204
DSIS: 0		 [G]MII Transmit Clock input
VOUT[1]_R_CR[8]/
EMAC[1]_MTXD[7]/
VIN[1]A_D[19]/
UART5_RXD/
GP3[18]		 W23 O IPD
DVDD		 VOUT[1], VIN[1]A, UART5, GP3
PINCNTL226
DSIS: N/A		 [G]MII Transmit Data [7:0]. For 1000 EMAC GMII operation, EMAC[0]_TXD[7:0] are used. For 10/100 EMAC MII operation, only EMAC[0]_TXD[3:0] are used.
VOUT[1]_R_CR[7]/
EMAC[1]_MTXD[6]/
VIN[1]A_D[18]/
SPI[3]_D[0]/
GP3[17]		 V22 VOUT[1], VIN[1]A, SPI[3], GP3
PINCNTL225
DSIS: N/A
VOUT[1]_R_CR[6]/
EMAC[1]_MTXD[5]/
VIN[1]A_D[17]/
SPI[3]_D[1]/
GP3[16]		 AA25 VOUT[1], VIN[1]A, SPI[3], GP3
PINCNTL224
DSIS: N/A
VOUT[1]_R_CR[5]/
EMAC[1]_MTXD[4]/
VIN[1]A_D[16]/
SPI[3]_SCLK/
GP3[15]		 AC26 VOUT[1], VIN[1]A, SPI[3], GP3
PINCNTL223
DSIS: N/A
VOUT[1]_R_CR[4]/
EMAC]1]_MTXD[3]/
VIN]1]A_D[15]/
SPI[3]_SCS[1]/
GP3[14]		 AG27 VOUT[1], VIN[1]A, SPI[3], GP3
PINCNTL222
DSIS: N/A
VOUT[1]_G_Y_YC[9]/
EMAC[1]_MTXD[2]/
VIN[1]A_D[14]/
GP3[13]		 AD26 VOUT[1], VIN[1]A, GP3
PINCNTL221
DSIS: N/A
VOUT[1]_G_Y_YC[8]/
EMAC[1]_MTXD[1]/
VIN[1]A_D[13]/
GP3[12]		 AE26 VOUT[1], VIN[1]A, GP3
PINCNTL220
DSIS: N/A
VOUT[1]_G_Y_YC[7]/
EMAC[1]_MTXD[0]/
VIN[1]A_D[12]/
GP3[11]		 AF26 VOUT[1], VIN[1]A, GP3
PINCNTL219
DSIS: N/A
VOUT[1]_R_CR[9]/
EMAC[1]_MTXEN/
VIN[1]A_D[20]/
UART5_TXD/
GP3[19]		 Y24 O IPD
DVDD		 VOUT[1], VIN[1]A, UART5, GP3
PINCNTL227
DSIS: N/A		 [G]MII Transmit Data Enable output
EMAC[1] RMII Mode
An EMAC bootmode must be selected via the BTMODE[4:0] pins. Once the EMAC bootmode is selected, the BTMODE[9:8] pins determine the Ethernet PHY Mode Selection (for example, 01b is RMII mode). For more detailed information on EMAC bootmodes and Ethernet PHY Mode selection, see Section 3.2.6, Ethernet PHY Mode Selection.

These pin functions are available only when RMII mode is selected.
EMAC_RMREFCLK/
TIM2_IO/
GP1[10]		 J27 I/O IPD
DVDD_GPMC		 TIMER2, GP1
PINCNTL232
DSIS: PIN		 RMII Reference Clock (EMAC[0] and EMAC[1] RMII mode)
VIN[0]A_D[20]/
CAM_D[12]/
EMAC[1]_RMCRSDV/
SPI[3]_SCS[0]/
GP0[14]		 AC17 I IPD
DVDD_C		 VIN[0]A, CAMERA_I/F, SPI[3], GP0
PINCNTL160
DSIS: 0
MM: MUX1		 RMII Carrier Sense input
EMAC[0]_MTXD[5]/
EMAC[1]_RGTXC/
EMAC[1]_RMCRSDV/
GPMC_A[12]/
UART1_RXD 		F27 I IPD
DVDD_GPMC		 EMAC[0], EMAC[1], GPMC, UART1
PINCNTL255
DSIS: 0
MM: MUX0
VIN[0]A_D[18]/
CAM_D[10]/
EMAC[1]_RMRXD[1]/
I2C[3]_SCL/
GP0[12]		 AF20 I IPU
DVDD_C		 VIN[0]A, CAMERA_I/F, I2C[3], GP0
PINCNTL158
DSIS: PIN
MM: MUX1		 RMII Receive Data [1:0].
EMAC[0]_MTXD[3]/
EMAC[1]_RGTXD[0]/
EMAC[1]_RMRXD[1]/
GPMC_A[10]/
UART4_CTS		 H23 I IPD
DVDD_GPMC		 EMAC[0], EMAC[1], GPMC, UART4
PINCNTL253
DSIS: PIN
MM: MUX0
VIN[0]A_D[19]/
CAM_D[11]/
EMAC[1]_RMRXD[0]/
I2C[3]_SDA/
GP0[13]		 AF21 I IPU
DVDD_C		 VIN[0]A, CAMERA_I/F, I2C[3], GP0
PINCNTL159
DSIS: PIN
MM: MUX1
EMAC[0]_MTXD[2]/
EMAC[1]_RGTXCTL/
EMAC[1]_RMRXD[0]/
GPMC_A[9]/
UART4_TXD 		H22 I IPD
DVDD_GPMC		 EMAC[0], EMAC[1], GPMC, UART4
PINCNTL252
DSIS: PIN
MM: MUX0
VIN[0]A_D[17]/
CAM_D[9]/
EMAC[1]_RMRXER/
GP0[11]		 AB21 I IPD
DVDD_C		 VIN[0]A, CAMERA_I/F, SPI[3], GP0
PINCNTL157
DSIS: 0
MM: MUX1		 RMII Receive Data Error input
EMAC[0]_MTXD[4]/
EMAC[1]_RGTXD[2]/
EMAC[1]_RMRXER/
GPMC_A[11]/
UART4_RTS		 G23 I IPD
DVDD_GPMC		 EMAC[0], EMAC[1], GPMC, UART1
PINCNTL254
DSIS: 0
MM: MUX0
VIN[0]A_D[22]/
CAM_D[14]/
EMAC[1]_RMTXD[1]/
SPI[3]_D[1]/
GP0[16]		 AC21 O IPD
DVDD_C		 VIN[0]A, CAMERA_I/F, SPI[3], GP0
PINCNTL162
DSIS: N/A
MM: MUX1		 RMII Transmit Data [1:0].
EMAC[0]_MTXD[7]/
EMAC[1]_RGTXD[3]/
EMAC[1]_RMTXD[1]/
GPMC_A[14]/
UART1_CTS		 H24 O IPD
DVDD_GPMC		 EMAC[0], GPMC, UART1
PINCNTL257
DSIS: N/A
MM: MUX0
VIN[0]A_D[21]/
CAM_D[13]/
EMAC[1]_RMTXD[0]/
SPI[3]_SCLK/
GP0[15]		 AE18 O IPD
DVDD_C		 VIN[0]A CAMERA_I/F, SPI[3], GP0
PINCNTL161
DSIS: N/A
MM: MUX1
EMAC[0]_MTXD[6]/
EMAC[1]_RGRXD[0]/
EMAC[1]_RMTXD[0]/
GPMC_A[13]/
UART1_TXD 		J22 O IPD
DVDD_GPMC		 EMAC[0], EMAC[1], GPMC, UART1
PINCNTL256
DSIS: N/A
MM: MUX0
VIN[0]A_D[23]/
CAM_D[15]/
EMAC[1]_RMTXEN/
SPI[3]_D[0]/
GP0[17]		 AC16 O IPD
DVDD_C		 VIN[0]A, CAMERA_I/F, SPI[3], GP0
PINCNTL163
DSIS: N/A
MM: MUX1		 RMII Transmit Data Enable output
EMAC[0]_MTXEN/
EMAC[1]_RGRXD[2]/
EMAC[1]_RMTXEN/
GPMC_A[15]/
UART1_RTS		 J23 O IPD
DVDD_GPMC		 EMAC[0], EMAC[1], GPMC, UART1
PINCNTL258
DSIS: N/A
MM: MUX0
EMAC[1] RGMII MODE
An EMAC bootmode must be selected via the BTMODE[4:0] pins. Once the EMAC bootmode is selected, the BTMODE[9:8] pins determine the Ethernet PHY Mode Selection (for example, 10b is RGMII mode). For more detailed information on EMAC bootmodes and Ethernet PHY Mode selection, see Section 3.2.6, Ethernet PHY Mode Selection

These pin functions are available only when RGMII mode is selected.
EMAC[0]_GMTCLK/
EMAC[1]_RGRXC/
GPMC_A[6]/
SPI[2]_D[1]		 K23 I IPD
DVDD_GPMC		 EMAC[0], GPMC, SPI[2]
PINCNTL249
DSIS: PIN		 RGMII Receive Clock
EMAC[0]_MRXD[3]/
EMAC[1]_RGRXCTL/
GPMC_A[27]/
GPMC_A[26]/
GPMC_A[0]/
UART5_RXD 		J25 I IPD
DVDD_GPMC		 EMAC[0], GPMC, UART5
PINCNTL243
DSIS: PIN		 RGMII Receive Control
EMAC[0]_MTXD[0]/
EMAC[1]_RGRXD[3]/
GPMC_A[7]/
SPI[2]_D[0]		 J24 I IPD
DVDD_GPMC		 EMAC[0], GPMC, UART4
PINCNTL250
DSIS: PIN		 RGMII Receive Data [3:0]
EMAC[0]_MTXEN/
EMAC[1]_RGRXD[2]/
EMAC[1]_RMTXEN/
GPMC_A[15]/
UART1_RTS		 J23 I IPD
DVDD_GPMC		 EMAC[0], GPMC, UART4
PINCNTL258
DSIS: PIN
EMAC[0]_MRXDV/
EMAC[1]_RGRXD[1]/
GPMC_A[5]/
SPI[2]_SCLK		 K22 I IPD
DVDD_GPMC		 EMAC[0], GPMC, SPI[2]
PINCNTL248
DSIS: PIN
EMAC[0]_MTXD[6]/
EMAC[1]_RGRXD[0]/
EMAC[1]_RMTXD[0]/
GPMC_A[13]/
UART1_TXD		 J22 I IPD
DVDD_GPMC		 EMAC[0], GPMC, UART1
PINCNTL256
DSIS: PIN
EMAC[0]_MTXD[5]/
EMAC[1]_RGTXC/
EMAC[1]_RMCRSDV/
GPMC_A[12]/
UART1_RXD		 F27 O IPD
DVDD_GPMC		 EMAC[0], GPMC, UART1
PINCNTL255
DSIS: N/A		 RGMII Transmit Clock
EMAC[0]_MTXD[2]/
EMAC[1]_RGTXCTL/
EMAC[1]_RMRXD[0]/
GPMC_A[9]/
UART4_TXD		 H22 O IPD
DVDD_GPMC		 EMAC[0], GPMC, UART4
PINCNTL252
DSIS: N/A		 RGMII Transmit Enable
EMAC[0]_MTXD[7]/
EMAC[1]_RGTXD[3]/
EMAC[1]_RMTXD[1]/
GPMC_A[14]/
UART1_CTS		 H24 O IPD
DVDD_GPMC		 EMAC[0], GPMC, UART1
PINCNTL257
DSIS: N/A		 RGMII Transmit Data [3:0]
EMAC[0]_MTXD[4]/
EMAC[1]_RGTXD[2]/
EMAC[1]_RMRXER/
GPMC_A[11]/
UART4_RTS		 G23 O IPD
DVDD_GPMC		 EMAC[0], GPMC, UART4
PINCNTL254
DSIS: N/A
EMAC[0]_MTXD[1]/
EMAC[1]_RGTXD[1]/
GPMC_A[8]/
UART4_RXD		 H25 O IPD
DVDD_GPMC		 EMAC[0], GPMC, UART4
PINCNTL251
DSIS: N/A
EMAC[0]_MTXD[3]/
EMAC[1]_RGTXD[0]/
EMAC[1]_RMRXD[1]/
GPMC_A[10]/
UART4_CTS		 H23 O IPD
DVDD_GPMC		 EMAC[0], EMAC[1], GPMC, UART4
PINCNTL253
DSIS: N/A
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS = De-selected Input State
(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the Internal Pull after Reset. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see Section 3.5.1, Pullup/Pulldown Resistors and the Section 6.3.17, Pin Behaviors at Reset.
(3) Specifies the operating I/O supply voltage for each signal

Table 2-9 MDIO Terminal Functions

SIGNAL TYPE(1) OTHER(2) (3) MUXED DESCRIPTION
NAME NO.
MDIO
MDCLK/
GP1[11]		 H28 O IPU
DVDD_GPMC		 GP1
PINCNTL233
DSIS: N/A		 Management Data Serial Clock output
MDIO/
GP1[12]		 P24 I/O IPU
DVDD_GPMC		 GP1
PINCNTL234
DSIS: 1		 Management Data I/O
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS = De-selected Input State
(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the Internal Pull after Reset. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see Section 3.5.1, Pullup/Pulldown Resistors and Section 6.3.17, Pin Behaviors at Reset.
(3) Specifies the operating I/O supply voltage for each signal

2.11.7 General-Purpose Input/Outputs (GPIOs)

Table 2-10 GP0 Terminal Functions

SIGNAL TYPE(1) OTHER(2) (3) MUXED DESCRIPTION
NAME NO.
GPIO0
Note: General-Purpose Input/Output (I/O) pins can also serve as external interrupt inputs.
UART2_TXD/
GP0[31]		 U3 I/O IPD
DVDD		 UART2
PINCNTL61
DSIS: PIN		 General-Purpose Input/Output (I/O) 0 [GP0] pin 31
TCLKIN/
GP0[30]		 T2 I/O IPD
DVDD		 TCLKIN
PINCNTL60
DSIS: PIN		 General-Purpose Input/Output (I/O) 0 [GP0] pin 30
UART2_RXD/
GP0[29]		 U4 I/O IPD
DVDD		 UART2
PINCNTL59
DSIS: PIN		 General-Purpose Input/Output (I/O) 0 [GP0] pin 29
MCA[5]_AXR[1]/
MCA[4]_AXR[3]/
TIM7_IO/
GP0[28]		 L6 I/O IPD
DVDD		 MCA[5], MCA[4], TIMER7
PINCNTL58
DSIS: PIN
MM: MUX1		 General-Purpose Input/Output (I/O) 0 [GP0] pin 28
VOUT[1]_FLD/
CAM_FLD/
CAM_WE/
GPMC_A[11]/
UART2_CTS/
GP0[28]		 AB23 I/O IPD
DVDD_C		 VOUT[1], CAMERA_I/F, GPMC, UART2
PINCNTL174
DSIS: PIN
MM: MUX0
MCA[5]_AXR[0]/
MCA[4]_AXR[2]/
GP0[27]		 L7 I/O IPD
DVDD		 MCA[5], MCA[4]
PINCNTL57
DSIS: PIN
MM: MUX1		 General-Purpose Input/Output (I/O) 0 [GP0] pin 27
VOUT[1]_B_CB_C[0]/
CAM_VS/
GPMC_A[10]/
UART2_TXD/
GP0[27]		 AD23 I/O IPU
DVDD_C		 VOUT[1], CAMERA_I/F, GPMC, UART2
PINCNTL173
DSIS: PIN
MM: MUX0
MCA[5]_AFSX/
GP0[26]		 H5 I/O IPD
DVDD		 MCA[5]
PINCNTL56
DSIS: PIN
MM: MUX1		 General-Purpose Input/Output (I/O) 0 [GP0] pin 26
VOUT[1]_B_CB_C[1]/
CAM_HS/
GPMC_A[9]/
UART2_RXD/
GP0[26]		 AE23 I/O IPD
DVDD_C		 VOUT[1], CAMERA_I/F, GPMC, UART2
PINCNTL172
DSIS: PIN
MM: MUX0
MCA[5]_ACLKX/
GP0[25]		 J3 I/O IPD
DVDD		 MCA[5]
PINCNTL55
DSIS: PIN
MM: MUX1		 General-Purpose Input/Output (I/O) 0 [GP0] pin 25
VOUT[1]_R_CR[0]/
CAM_D[0]/
GPMC_A[8]/
UART4_RTS/
GP0[25]		 AA22 I/O IPD
DVDD_C		 VOUT[1], CAMERA_I/F, GPMC, UART4
PINCNTL171
DSIS: PIN
MM: MUX0
MCA[4]_AXR[1]/
TIM6_IO/
GP0[24]		 J4 I/O IPD
DVDD		 MCA[4], TIMER6
PINCNTL54
DSIS: PIN
MM: MUX1		 General-Purpose Input/Output (I/O) 0 [GP0] pin 24
VOUT[1]_R_CR[1]/
CAM_D[1]/
GPMC_A[7]/
UART4_CTS/
GP0[24]		 AC19 I/O IPD
DVDD_C		 VOUT[1], CAMERA_I/F, GPMC, UART4
PINCNTL170
DSIS: PIN
MM: MUX0
MCA[4]_AXR[0]/
GP0[23]		 H6 I/O IPD
DVDD		 MCA[4]
PINCNTL53
DSIS: PIN
MM: MUX1		 General-Purpose Input/Output (I/O) 0 [GP0] pin 23
VOUT[1]_G_Y_YC[0]/
CAM_D[2]/
GPMC_A[6]/
UART4_TXD/
GP0[23]		 AC18 I/O IPD
DVDD_C		 VOUT[1], CAMERA_I/F, GPMC, UART4
PINCNTL169
DSIS: PIN
MM: MUX0
MCA[4]_AFSX/
GP0[22]		 H3 I/O IPD
DVDD		 MCA[4]
PINCNTL52
DSIS: PIN
MM: MUX1		 General-Purpose Input/Output (I/O) 0 [GP0] pin 22
VOUT[1]_G_Y_YC[1]/
CAM_D[3]/
GPMC_A[5]/
UART4_RXD/
GP0[22]		 AD18 I/O IPU
DVDD_C		 VOUT[1], CAMERA_I/F, GPMC, UART4
PINCNTL168
DSIS: PIN
MM: MUX0
MCA[4]_ACLKX/
GP0[21]		 K7 I/O IPD
DVDD		 MCA[4]
PINCNTL51
DSIS: PIN
MM: MUX1		 General-Purpose Input/Output (I/O) 0 [GP0] pin 21
VIN[0]B_FLD/
CAM_D[4]/
GP0[21]		 AD17 I/O IPU
DVDD_C		 VIN[0]B, CAMERA_I/F
PINCNTL167
DSIS: PIN
MM: MUX0
MCA[3]_AXR[2]/
MCA[1]_AXR[8]/
GP0[20]		 F2 I/O IPD
DVDD		 MCA[3], MCA[1]
PINCNTL49
DSIS: PIN
MM: MUX1		 General-Purpose Input/Output (I/O) 0 [GP0] pin 20
VIN[0]A_FLD/
CAM_D[5]/
GP0[20]		 AC22 I/O IPU
DVDD_C		 VIN[0]A, CAMERA_I/F
PINCNTL166
DSIS: PIN
MM: MUX0
MCA[3]_AXR[1]/
TIM5_IO/
GP0[19]		 G2 I/O IPD
DVDD		 MCA[3], TIMER5
PINCNTL48
DSIS: PIN
MM: MUX1		 General-Purpose Input/Output (I/O) 0 [GP0] pin 19
VIN[0]B_DE/
CAM_D[6]/
GP0[19]		 AC15 I/O IPU
DVDD_C		 VIN[0]B, CAMERA_I/F
PINCNTL165
DSIS: PIN
MM: MUX0
MCA[3]_AXR[0]/
TIM4_IO/
GP0[18]		 G1 I/O IPD
DVDD		 MCA[3], TIMER4
PINCNTL47
DSIS: PIN
MM: MUX1		 General-Purpose Input/Output (I/O) 0 [GP0] pin 18
VIN[0]A_DE/
CAM_D[7]/
GP0[18]		 AB17 I/O IPU
DVDD_C		 VIN[0]A, CAMERA_I/F
PINCNTL164
DSIS: PIN
MM: MUX0
MCA[3]_AFSX/
GP0[17]		 H4 I/O IPD
DVDD		 MCA[3]
PINCNTL46
DSIS: PIN
MM: MUX1		 General-Purpose Input/Output (I/O) 0 [GP0] pin 17
VIN[0]A_D[23]/
CAM_D[15]/
EMAC[1]_RMTXEN/
SPI[3]_D[0]/
GP0[17]		 AC16 I/O IPD
DVDD_C		 VIN[0]A, CAMERA_I/F, EMAC[1]_RM, SPI[3]
PINCNTL163
DSIS: PIN
MM: MUX0
MCA[3]_ACLKX/
GP0[16]		 G6 I/O IPD
DVDD		 MCA[3]
PINCNTL45
DSIS: PIN
MM: MUX1		 General-Purpose Input/Output (I/O) 0 [GP0] pin 16
VIN[0]A_D[22]/
CAM_D[14]/
EMAC[1]_RMTXD[1]/
SPI[3]_D[1]/
GP0[16]		 AC21 I/O IPD
DVDD_C		 VIN[0]A, CAMERA_I/F, EMAC[1]_RM, SPI[3]
PINCNTL162
DSIS: PIN
MM: MUX0
MCA[2]_AXR[3]/
MCA[1]_AXR[7]/
TIM3_IO/
GP0[15]		 H2 I/O IPD
DVDD		 MCA[2], MCA[1], TIMER3
PINCNTL44
DSIS: PIN
MM: MUX1		 General-Purpose Input/Output (I/O) 0 [GP0] pin 15
VIN[0]A_D[21]/
CAM_D[13]/
EMAC[1]_RMTXD[0]/
SPI[3]_SCLK/
GP0[15]		 AE18 I/O IPD
DVDD_C		 VIN[0]A, CAMERA_I/F, EMAC[1]_RM, SPI[3]
PINCNTL161
DSIS: PIN
MM: MUX0
MCA[2]_AXR[2]/
MCA[1]_AXR[6]/
TIM2_IO/
GP0[14]		 V5 I/O IPD
DVDD		 MCA[2], MCA[1], TIMER2
PINCNTL43
DSIS: PIN
MM: MUX1		 General-Purpose Input/Output (I/O) 0 [GP0] pin 14
VIN[0]A_D[20]/
CAM_D[12]/
EMAC[1]_RMCRSDV/
SPI[3]_SCS[0]/
GP0[14]		 AC17 I/O IPD
DVDD_C		 VIN[0]A, CAMERA_I/F, EMAC[1]_RM, SPI[3]
PINCNTL160
DSIS: PIN
MM: MUX0
MCA[2]_AXR[1]/
SD0_DAT[7]/
UART5_TXD/
GP0[13]		 V6 I/O IPU
DVDD		 MCA[2], SD0, UART5
PINCNTL42
DSIS: PIN
MM: MUX1		 General-Purpose Input/Output (I/O) 0 [GP0] pin 13
VIN[0]A_D[19]/
CAM_D[11]/
EMAC[1]_RMRXD[0]/
I2C[3]_SDA/
GP0[13]		 AF21 I/O IPU
DVDD_C		 VIN[0]A, CAMERA_I/F, EMAC[1]_RM, I2C[3]
PINCNTL159
DSIS: PIN
MM: MUX0
MCA[2]_AXR[0]/
SD0_DAT[6]/
UART5_RXD/
GP0[12]		 N2 I/O IPU
DVDD		 MCA[2], SD0, UART5
PINCNTL41
DSIS: PIN
MM: MUX1		 General-Purpose Input/Output (I/O) 0 [GP0] pin 12
VIN[0]A_D[18]/
CAM_D[10]/
EMAC[1]_RMRXD[1]/
I2C[3]_SCL/
GP0[12]		 AF20 I/O IPU
DVDD_C		 VIN[0]A, CAMERA_I/F, EMAC[1]_RM, I2C[3]
PINCNTL158
DSIS: PIN
MM: MUX0
MCA[2]_AFSX/
GP0[11]		 AA5 I/O IPU
DVDD		 MCA[2]
PINCNTL40
DSIS: PIN
MM: MUX1		 General-Purpose Input/Output (I/O) 0 [GP0] pin 11
VIN[0]A_D[17]/
CAM_D[9]/
EMAC[1]_RMRXER/
GP0[11]		 AB21 I/O IPD
DVDD_C		 VIN[0]A, CAMERA_I/F, EMAC[1]_RM
PINCNTL157
DSIS: PIN
MM: MUX0
MCA[2]_ACLKX/
GP0[10]		 U6 I/O IPU
DVDD		 MCA[2]
PINCNTL39
DSIS: PIN
MM: MUX1		 General-Purpose Input/Output (I/O) 0 [GP0] pin 10
VIN[0]A_D[16]/
CAM_D[8]/
I2C[2]_SCL/
GP0[10]		 AA21 I/O IPU
DVDD_C		 VIN[0]A, CAMERA_I/F, I2C[2]
PINCNTL156
DSIS: PIN
MM: MUX0
AUD_CLKIN2/
MCA[0]_AXR[9]/
MCA[2]_AHCLKX/
MCA[5]_AHCLKX/
EDMA_EVT2/
TIM3_IO/
GP0[9]		 H1 I/O IPD
DVDD		 AUD_CLKIN2, MCA[0], MCA[2], MCA[5], EDMA, TIMER3
PINCNTL16
DSIS: PIN		 General-Purpose Input/Output (I/O) 0 [GP0] pin 9
AUD_CLKIN1/
MCA[0]_AXR[8]/
MCA[1]_AHCLKX/
MCA[4]_AHCLKX/
EDMA_EVT3/
TIM2_IO/
GP0[8] 		R5 I/O IPD
DVDD		 AUD_CLKIN1, MCA[0], MCA[1], MCA[4], EDMA, TIMER2
PINCNTL15
DSIS: PIN		 General-Purpose Input/Output (I/O) 0 [GP0] pin 8
USB0_DRVVBUS/
GP0[7]		 AF11 I/O IPD
DVDD		 USB0
PINCNTL270
DSIS: PIN		 General-Purpose Input/Output (I/O) 0 [GP0] pin 7
SD0_DAT[3]/
SD1_DAT[7]/
GP0[6]		 Y4 I/O IPU
DVDD_SD		 SD0, SD1
PINCNTL13
DSIS: PIN		 General-Purpose Input/Output (I/O) 0 [GP0] pin 6
SD0_DAT[2]_SDRW/
SD1_DAT[6]/
GP0[5]		 Y3 I/O IPU
DVDD_SD		 SD0, SD1
PINCNTL12
DSIS: PIN		 General-Purpose Input/Output (I/O) 0 [GP0] pin 5
SD0_DAT[1]_SDIRQ/
SD1_DAT[5]/
GP0[4]		 Y5 I/O IPU
DVDD_SD		 SD0, SD1
PINCNTL11
DSIS: PIN		 General-Purpose Input/Output (I/O) 0 [GP0] pin 4
SD0_DAT[0]/
SD1_DAT[4]/
GP0[3]		 R7 I/O IPU
DVDD_SD		 SD0, SD1
PINCNTL10
DSIS: PIN		 General-Purpose Input/Output (I/O) 0 [GP0] pin 3
SD0_CMD/
SD1_CMD/
GP0[2]		 N1 I/O IPU
DVDD_SD		 SD0, SD1
PINCNTL9
DSIS: PIN		 General-Purpose Input/Output (I/O) 0 [GP0] pin 2
SD0_CLK/
GP0[1]		 Y6 I/O IPU
DVDD_SD		 SD0
PINCNTL8
DSIS: PIN		 General-Purpose Input/Output (I/O) 0 [GP0] pin 1
SD1_CMD/
GP0[0]		 P2 I/O IPU
DVDD_SD		 SD1
PINCNTL2
DSIS: PIN		 General-Purpose Input/Output (I/O) 0 [GP0] pin 0
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS = De-selected Input State
(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the Internal Pull after Reset. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see Section 3.5.1, Pullup/Pulldown Resistors and Section 6.3.17, Pin Behaviors at Reset.
(3) Specifies the operating I/O supply voltage for each signal

Table 2-11 GP1 Terminal Functions

SIGNAL TYPE(1) OTHER(2) (3) MUXED DESCRIPTION
NAME NO.
GPIO1
Note: General-Purpose Input/Output (I/O) pins can also serve as external interrupt inputs.
GPMC_WAIT[0]/
GPMC_A[26]/
EDMA_EVT0/
GP1[31]		 W28 I/O IPU
DVDD_GPMC		 GPMC, EDMA
PINCNTL133
DSIS: PIN		 General-Purpose Input/Output (I/O) 1 [GP1] pin 31
GPMC_BE[1]/
GPMC_A[24]/
EDMA_EVT1/
TIM7_IO/
GP1[30]		 V28 I/O IPD
DVDD_GPMC		 GPMC, EDMA, TIMER7
PINCNTL132
DSIS: PIN		 General-Purpose Input/Output (I/O) 1 [GP1] pin 30
GPMC_BE[0]_CLE/
GPMC_A[25]/
EDMA_EVT2/
TIM6_IO/
GP1[29]		 U27 I/O IPD
DVDD_GPMC		 GPMC, EDMA, TIMER6
PINCNTL131
DSIS: PIN		 General-Purpose Input/Output (I/O) 1 [GP1] pin 29
GPMC_ADV_ALE/
GPMC_CS[6]/
TIM5_IO/
GP1[28]		 M26 I/O IPU
DVDD_GPMC		 GPMC, TIMER5
PINCNTL128
DSIS: PIN		 General-Purpose Input/Output (I/O) 1 [GP1] pin 28
GPMC_CLK/
GPMC_CS[5]/
GPMC_WAIT[1]/
CLKOUT1/
EDMA_EVT3/
TIM4_IO/
GP1[27]		 R26 I/O IPU
DVDD_GPMC		 GPMC, CLKOUT1, EDMA, TIMER4
PINCNTL127
DSIS: PIN		 General-Purpose Input/Output (I/O) 1 [GP1] pin 27
SPI[1]_D[0]/
GP1[26]		 AA6 I/O IPU
DVDD		 SPI[1]
PINCNTL88
DSIS: PIN
MM: MUX1		 General-Purpose Input/Output (I/O) 1 [GP1] pin 26
GPMC_CS[3]/
VIN[1]B_CLK/
SPI[2]_SCS[0]/
GP1[26]		 P26 I/O IPU
DVDD_GPMC		 GPMC, VIN[1]B, SPI[2]
PINCNTL125
DSIS: PIN
MM: MUX0
GPMC_CS[2]/
GPMC_A[24]/
GP1[25]		 M25 I/O IPU
DVDD_GPMC		 GPMC
PINCNTL124
DSIS: PIN		 General-Purpose Input/Output (I/O) 1 [GP1] pin 25
GPMC_CS[1]/
GPMC_A[25]/
GP1[24]		 K28 I/O IPU
DVDD_GPMC		 GPMC
PINCNTL123
DSIS: PIN		 General-Purpose Input/Output (I/O) 1 [GP1] pin 24
GPMC_CS[0]/
GP1[23]		 T28 I/O IPU
DVDD_GPMC		 GPMC
PINCNTL122
DSIS: PIN		 General-Purpose Input/Output (I/O) 1 [GP1] pin 23
SD2_DAT[4]/
GPMC_A[27]/
GPMC_A[23]/
GPMC_CS[7]/
EDMA_EVT0/
TIM7_IO/
GP1[22]		 R24 I/O IPU
DVDD_GPMC		 SD2, GPMC, EDMA, TIMER7
PINCNTL116
DSIS: PIN		 General-Purpose Input/Output (I/O) 1 [GP1] pin 22
SD2_DAT[5]/
GPMC_A[26]/
GPMC_A[22]/
TIM6_IO/
GP1[21]		 P22 I/O IPU
DVDD_GPMC		 SD2, GPMC, TIMER6
PINCNTL115
DSIS: PIN		 General-Purpose Input/Output (I/O) 1 [GP1] pin 21
SD2_DAT[6]/
GPMC_A[25]/
GPMC_A[21]/
UART2_TXD/
GP1[20]		 N23 I/O IPU
DVDD_GPMC		 SD2, GPMC, UART2
PINCNTL114
DSIS: PIN		 General-Purpose Input/Output (I/O) 1 [GP1] pin 20
SD2_DAT[7]/
GPMC_A[24]/
GPMC_A[20]/
UART2_RXD/
GP1[19]		 L25 I/O IPU
DVDD_GPMC		 SD2, GPMC, UART2
PINCNTL113
DSIS: PIN		 General-Purpose Input/Output (I/O) 1 [GP1] pin 19
SPI[1]_D[1]/
GP1[18]		 AA3 I/O IPU
DVDD		 SPI[1]
PINCNTL87
DSIS: PIN
MM: MUX1		 General-Purpose Input/Output (I/O) 1 [GP1] pin 18
GPMC_A[23]/
SPI[2]_SCLK/
HDMI_HPDET/
TIM5_IO/
GP1[18]		 AA26 I/O IPD
DVDD_GPMC		 GPMC, SPI[2], HDMI, TIMER5
PINCNTL112
DSIS: PIN
MM: MUX0
SPI[1]_SCLK/
GP1[17]		 AC3 I/O IPU
DVDD		 SPI[1]
PINCNTL86
DSIS: PIN
MM: MUX1		 General-Purpose Input/Output (I/O) 1 [GP1] pin 17
GPMC_A[22]/
SPI[2]_D[1]/
HDMI_CEC/
TIM4_IO/
GP1[17]		 AB27 I/O IPU
DVDD_GPMC		 GPMC, SPI[2], HDMI, TIMER4
PINCNTL111
DSIS: PIN
MM: MUX0
SPI[1]_SCS[0]/
GP1[16]		 AD3 I/O IPU
DVDD		 SPI[1]
PINCNTL85
DSIS: PIN
MM: MUX1		 General-Purpose Input/Output (I/O) 1 [GP1] pin 16
GPMC_A[21]/
SPI[2]_D[0]/
GP1[16]		 AC28 I/O IPD
DVDD_GPMC		 GPMC, SPI[2]
PINCNTL110
DSIS: PIN
MM: MUX0
SD2_CLK/
GP1[15]		 M23 I/O IPU
DVDD_GPMC		 SD2
PINCNTL121
DSIS: PIN
MM: MUX1		 General-Purpose Input/Output (I/O) 1 [GP1] pin 15
GPMC_A[20]/
SPI[2]_SCS[1]/
GP1[15]		 AD28 I/O IPU
DVDD_GPMC		 GPMC, SPI[2]
PINCNTL109
DSIS: PIN
MM: MUX0
SD2_DAT[0]/
GPMC_A[4]/
GP1[14]		 L26 I/O IPU
DVDD_GPMC		 SD2, GPMC
PINCNTL120
DSIS: PIN
MM: MUX1		 General-Purpose Input/Output (I/O) 1 [GP1] pin 14
GPMC_A[19]/
TIM3_IO/
GP1[14]		 AC27 I/O IPD
DVDD_GPMC		 GPMC, TIMER3
PINCNTL108
DSIS: PIN
MM: MUX0
SD2_DAT[1]_SDIRQ/
GPMC_A[3]/
GP1[13]		 M24 I/O IPU
DVDD_GPMC		 SD2, GPMC
PINCNTL119
DSIS: PIN
MM: MUX1		 General-Purpose Input/Output (I/O) 1 [GP1] pin 13
GPMC_A[18]/
TIM2_IO/
GP1[13]		 AE28 I/O IPD
DVDD_GPMC		 GPMC, TIMER2
PINCNTL107
DSIS: PIN
MM: MUX0
VIN[0]A_D[1]/
GP1[12]		 AB11 I/O IPD
DVDD		 VIN[0]A
PINCNTL141
DSIS: PIN
MM: MUX1		 General-Purpose Input/Output (I/O) 1 [GP1] pin 12
MDIO/
GP1[12]		 P24 I/O IPU
DVDD_GPMC		 MDIO
PINCNTL234
DSIS: PIN
MM: MUX0
VIN[0]A_D[0]/
GP1[11]		 AF9 I/O IPD
DVDD		 VIN[0]A
PINCNTL140
DSIS: PIN
MM: MUX1		 General-Purpose Input/Output (I/O) 1 [GP1] pin 11
MDCLK/
GP1[11]		 H28 I/O IPU
DVDD_GPMC		 MDIO
PINCNTL233
DSIS: PIN
MM: MUX0
GP1[10] V2 I/O IPU
DVDD_M		 PINCNTL65
DSIS: PIN
MM: MUX1		 General-Purpose Input/Output (I/O) 1 [GP1] pin 10

The ENLVCMOS bit in the MLBP_DAT_IO_CTRL register should be set to 1 to enable GPIO LVCMOS mode. The ENN bit in the MLBP_DAT_IO_CTRL register should also be set to 1 to enable the GPIO LVCMOS receiver. The internal Pullup/Pulldown is always disabled, regardless of the state of the PULLUDEN bit in the PINCNTL65 register. An external Pullup/Pulldown can be used to control the floating state of this pin.
EMAC_RMREFCLK/
TIM2_IO/
GP1[10]		 J27 I/O IPD
DVDD_GPMC		 EMAC, TIMER2
PINCNTL232
DSIS: PIN
MM: MUX0		 General-Purpose Input/Output (I/O) 1 [GP1] pin 10
GP1[9] V1 I/O IPD
DVDD_M		 PINCNTL64
DSIS: PIN
MM: MUX1		 General-Purpose Input/Output (I/O) 1 [GP1] pin 9

The ENLVCMOS bit in the MLBP_DAT_IO_CTRL register should be set to 1 to enable GPIO LVCMOS mode. The ENP bit in the MLBP_DAT_IO_CTRL register should also be set to 1 to enable the GPIO LVCMOS receiver. The internal Pullup/Pulldown is always disabled, regardless of the state of the PULLUDEN bit in the PINCNTL64 register. An external Pullup/Pulldown can be used to control the floating state of this pin.
VIN[0]B_CLK/
CLKOUT0/
GP1[9]		 AE17 I/O IPD
DVDD		 VIN[0]B, CLKOUT0
PINCNTL134
DSIS: PIN
MM: MUX0		 General-Purpose Input/Output (I/O) 1 [GP1] pin 9
GP1[8] W2 I/O IPU
DVDD_M		 PINCNTL63
DSIS: PIN
MM: MUX1		 General-Purpose Input/Output (I/O) 1 [GP1] pin 8

The ENLVCMOS bit in the MLBP_DAT_IO_CTRL register should be set to 1 to enable GPIO LVCMOS mode. The ENN bit in the MLBP_DAT_IO_CTRL register should also be set to 1 to enable the GPIO LVCMOS receiver. The internal Pullup/Pulldown is always disabled, regardless of the state of the PULLUDEN bit in the PINCNTL63 register. An external Pullup/Pulldown can be used to control the floating state of this pin.
GPMC_CS[4]/
SD2_CMD/
GP1[8]		 P25 I/O IPU
DVDD_GPMC		 GPMC, SD2
PINCNTL126
DSIS: PIN
MM: MUX0		 General-Purpose Input/Output (I/O) 1 [GP1] pin 8
GP1[7] W1 I/O IPD
DVDD_M		 PINCNTL62
DSIS: PIN
MM: MUX1		 General-Purpose Input/Output (I/O) 1 [GP1] pin 7

The ENLVCMOS bit in the MLBP_DAT_IO_CTRL register should be set to 1 to enable GPIO LVCMOS mode. The ENP bit in the MLBP_DAT_IO_CTRL register should also be set to 1 to enable the GPIO LVCMOS receiver. The internal Pullup/Pulldown is always disabled, regardless of the state of the PULLUDEN bit in the PINCNTL62 register. An external Pullup/Pulldown can be used to control the floating state of this pin.
DEVOSC_WAKE/
SPI[1]_SCS[1]/
TIM5_IO/
GP1[7]		 W6 I/O IPU
DVDD_SD		 DEVOSC, SPI[1], TIMER5
PINCNTL7
DSIS: PIN
MM: MUX0		 General-Purpose Input/Output (I/O) 1 [GP1] pin 7
SPI[0]_SCS[1]/
SD1_SDCD/
SATA_ACT0_LED/
EDMA_EVT1/
TIM4_IO/
GP1[6]		 AE5 I/O IPU
DVDD		 SPI[0], SD1, SATA, EDMA, TIMER4
PINCNTL80
DSIS: PIN		 General-Purpose Input/Output (I/O) 1 [GP1] pin 6
UART0_RIN/
UART3_RTS/
UART1_RXD/
GP1[5]		 AF4 I/O IPU
DVDD		 UART0, UART3, UART1
PINCNTL77
DSIS: PIN		 General-Purpose Input/Output (I/O) 1 [GP1] pin 5
UART0_DTR/
UART3_CTS/
UART1_TXD/
GP1[4]		 AG2 I/O IPU
DVDD		 UART0, UART3, UART1
PINCNTL76
DSIS: PIN		 General-Purpose Input/Output (I/O) 1 [GP1] pin 4
UART0_DSR/
UART3_TXD/
SPI[0]_SCS[2]/
I2C[2]_SDA/
SD1_SDWP/
GP1[3]		 AG4 I/O IPU
DVDD		 UART0, UART3, SPI[0], I2C[2], SD1
PINCNTL75
DSIS: PIN		 General-Purpose Input/Output (I/O) 1 [GP1] pin 3
UART0_DCD/
UART3_RXD/
SPI[0]_SCS[3]/
I2C[2]_SCL/
SD1_POW/
GP1[2]		 AH4 I/O IPU
DVDD		 UART0, UART3, SPI[0], I2C[2], SD1
PINCNTL74
DSIS: PIN		 General-Purpose Input/Output (I/O) 1 [GP1] pin 2
DCAN0_RX/
UART2_RXD/
I2C[3]_SCL/
GP1[1]		 AG6 I/O IPU
DVDD		 DCAN0, UART2, I2C[3]
PINCNTL69
DSIS: PIN		 General-Purpose Input/Output (I/O) 1 [GP1] pin 1
DCAN0_TX/
UART2_TXD/
I2C[3]_SDA/
GP1[0]		 AH6 I/O IPU
DVDD		 DCAN0, UART2, I2C[3]
PINCNTL68
DSIS: PIN		 General-Purpose Input/Output (I/O) 1 [GP1] pin 0
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS = De-selected Input State
(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the Internal Pull after Reset. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see Section 3.5.1, Pullup/Pulldown Resistors and Section 6.3.17, Pin Behaviors at Reset.
(3) Specifies the operating I/O supply voltage for each signal

Table 2-12 GP2 Terminal Functions

SIGNAL TYPE(1) OTHER(2) (3) MUXED DESCRIPTION
NAME NO.
GPIO2
Note: General-Purpose Input/Output (I/O) pins can also serve as external interrupt inputs.
VOUT[1]_AVID/
EMAC[1]_MRXER/
VIN[1]A_CLK/
UART4_RTS/
TIM6_IO/
GP2[31]		 Y22 I/O IPD
DVDD		 VOUT[1], EMAC[1], VIN[1]A, UART4, TIMER6
PINCNTL207
DSIS: PIN		 General-Purpose Input/Output (I/O) 2 [GP2] pin 31
VOUT[1]_VSYNC/
EMAC[1]_MCRS/
VIN[1]A_FLD/
VIN[1]A_DE/
SPI[3]_D[0]/
UART3_CTS/
GP2[30]		 AA23 I/O IPD
DVDD		 VOUT[1], EMAC[1], VIN[1]A, SPI[3], UART3
PINCNTL206
DSIS: PIN		 General-Purpose Input/Output (I/O) 2 [GP2] pin 30
VOUT[1]_HSYNC/
EMAC[1]_MCOL/
VIN[1]A_VSYNC/
SPI[3]_D[1]/
UART3_RTS/
GP2[29]		 AC24 I/O IPD
DVDD		 VOUT[1], EMAC[1], VIN[1]A, SPI[3], UART3
PINCNTL205
DSIS: PIN		 General-Purpose Input/Output (I/O) 2 [GP2] pin 29
VOUT[1]_CLK/
EMAC[1]_MTCLK/
VIN[1]A_HSYNC/
GP2[28]		 AE24 I/O IPD
DVDD		 VOUT[1], EMAC[1], VIN[1]A
PINCNTL204
DSIS: PIN		 General-Purpose Input/Output (I/O) 2 [GP2] pin 28
VOUT[0]_R_CR[3]/
GP2[27]		 AB9 I/O IPD
DVDD		 VOUT[0]
PINCNTL197
DSIS: PIN		 General-Purpose Input/Output (I/O) 2 [GP2] pin 27
VOUT[0]_R_CR[2]/
EMU4/
GP2[26]		 AD9 I/O IPD
DVDD		 VOUT[0], EMU
PINCNTL196
DSIS: PIN		 General-Purpose Input/Output (I/O) 2 [GP2] pin 26
VOUT[0]_G_Y_YC[3]/
GP2[25]		 AH15 I/O IPD
DVDD		 VOUT[0]
PINCNTL189
DSIS: PIN		 General-Purpose Input/Output (I/O) 2 [GP2] pin 25
VOUT[0]_G_Y_YC[2]/
EMU3/
GP2[24]		 AH7 I/O IPD
DVDD		 VOUT[0], EMU
PINCNTL188
DSIS: PIN		 General-Purpose Input/Output (I/O) 2 [GP2] pin 24
VOUT[0]_B_CB_C[3]/
GP2[23]		 AE15 I/O IPD
DVDD		 VOUT[0]
PINCNTL181
DSIS: PIN		 General-Purpose Input/Output (I/O) 2 [GP2] pin 23
VOUT[0]_B_CB_C[2]/
EMU2/
GP2[22]		 AG7 I/O IPD
DVDD		 VOUT[0], EMU
PINCNTL180
DSIS: PIN		 General-Purpose Input/Output (I/O) 2 [GP2] pin 22
VOUT[0]_AVID/
VOUT[0]_FLD/
SPI[3]_SCLK/
TIM7_IO/
GP2[21]		 AA10 I/O IPD
DVDD		 VOUT[0], SPI[3], TIMER7
PINCNTL179
DSIS: PIN		 General-Purpose Input/Output (I/O) 2 [GP2] pin 21
VIN[0]A_D[15]_BD[7]/
CAM_SHUTTER/
GP2[20]		 AC14 I/O DIS
DVDD		 VIN[0]AB, CAMERA_I/F
PINCNTL155
DSIS: PIN		 General-Purpose Input/Output (I/O) 2 [GP2] pin 20
VIN[0]A_D[14]_BD[6]/
CAM_STROBE/
GP2[19]		 AC12 I/O IPD
DVDD		 VIN[0]AB, CAMERA_I/F
PINCNTL154
DSIS: PIN		 General-Purpose Input/Output (I/O) 2 [GP2] pin 19
VIN[0]A_D[13]_BD[5]/
CAM_RESET/
GP2[18]		 AF17 I/O IPD
DVDD		 VIN[0]AB, CAMERA_I/F
PINCNTL153
DSIS: PIN		 General-Purpose Input/Output (I/O) 2 [GP2] pin 18
VIN[0]A_D[12]_BD[4]/
CLKOUT1/
GP2[17]		 AG17 I/O IPD
DVDD		 VIN[0]AB, CLKOUT1
PINCNTL152
DSIS: PIN		 General-Purpose Input/Output (I/O) 2 [GP2] pin 17
VIN[0]A_D[11]_BD[3]/
CAM_WE/
GP2[16]		 AH17 I/O IPD
DVDD		 VIN[0]AB, CAMERA_I/F
PINCNTL151
DSIS: PIN		 General-Purpose Input/Output (I/O) 2 [GP2] pin 16
VIN[0]A_D[10]_BD[2]/
GP2[15]		 AH9 I/O IPD
DVDD		 VIN[0]AB
PINCNTL150
DSIS: PIN		 General-Purpose Input/Output (I/O) 2 [GP2] pin 15
VIN[0]A_D[9]_BD[1]/
GP2[14]		 AG9 I/O IPD
DVDD		 VIN[0]AB
PINCNTL149
DSIS: PIN		 General-Purpose Input/Output (I/O) 2 [GP2] pin 14
VIN[0]A_D[8]_BD[0]/
GP2[13]		 AB15 I/O IPD
DVDD		 VIN[0]AB
PINCNTL148
DSIS: PIN		 General-Purpose Input/Output (I/O) 2 [GP2] pin 13
VIN[0]A_D[7]/
GP2[12]		 AA11 I/O IPD
DVDD		 VIN[0]A
PINCNTL147
DSIS: PIN		 General-Purpose Input/Output (I/O) 2 [GP2] pin 12
VIN[0]A_D[6]/
GP2[11]		 AH16 I/O IPD
DVDD		 VIN[0]A
PINCNTL146
DSIS: PIN		 General-Purpose Input/Output (I/O) 2 [GP2] pin 11
VIN[0]A_D[5]/
GP2[10]		 AG16 I/O IPD
DVDD		 VIN[0]A
PINCNTL145
DSIS: PIN		 General-Purpose Input/Output (I/O) 2 [GP2] pin 10
VIN[0]A_D[4]/
GP2[9]		 AH8 I/O IPD
DVDD		 VIN[0]A
PINCNTL144
DSIS: PIN		 General-Purpose Input/Output (I/O) 2 [GP2] pin 9
VIN[0]A_D[3]/
GP2[8]		 AE12 I/O IPD
DVDD		 VIN[0]A
PINCNTL143
DSIS: PIN		 General-Purpose Input/Output (I/O) 2 [GP2] pin 8
VIN[0]A_D[2]/
GP2[7]		 AC9 I/O IPD
DVDD		 VIN[0]A
PINCNTL142
DSIS: PIN		 General-Purpose Input/Output (I/O) 2 [GP2] pin 7
SD2_DAT[2]_SDRW/
GPMC_A[2]/
GP2[6]		 K27 I/O IPU
DVDD_GPMC		 SD2, GPMC
PINCNTL118
DSIS: PIN
MM: MUX1		 General-Purpose Input/Output (I/O) 2 [GP2] pin 6
GPMC_A[17]/
GP2[6]		 V23 I/O IPD
DVDD_GPMC		 GPMC
PINCNTL106
DSIS: PIN
MM: MUX0
SD2_DAT[3]/
GPMC_A[1]/
GP2[5]		 J28 I/O IPU
DVDD_GPMC		 SD2, GPMC
PINCNTL117
DSIS: PIN
MM: MUX1		 General-Purpose Input/Output (I/O) 2 [GP2] pin 5
GPMC_A[16]/
GP2[5]		 AD27 I/O IPD
DVDD_GPMC		 GPMC
PINCNTL105
DSIS: PIN
MM: MUX0
VIN[0]A_VSYNC/
UART5_CTS/
GP2[4]		 AD20 I/O IPU
DVDD		 VIN[0]A, UART5
PINCNTL139
DSIS: PIN		 General-Purpose Input/Output (I/O) 2 [GP2] pin 4
VIN[0]A_HSYNC/
UART5_RTS/
GP2[3]		 AC20 I/O IPU
DVDD		 VIN[0]A, UART5
PINCNTL138
DSIS: PIN		 General-Purpose Input/Output (I/O) 2 [GP2] pin 3
VIN[0]A_CLK/
GP2[2]		 AB20 I/O IPD
DVDD		 VIN[0]A
PINCNTL137
DSIS: PIN
MM: MUX1		 General-Purpose Input/Output (I/O) 2 [GP2] pin 2
VOUT[0]_FLD/
CAM_PCLK/
GPMC_A[12]/
UART2_RTS/
GP2[2]		 AF18 I/O IPD
DVDD_C		 VOUT[0], CAMERA_I/F, GPMC, UART2
PINCNTL175
DSIS: PIN
MM: MUX0
VIN[0]A_FLD/
VIN[0]B_VSYNC/
UART5_RXD/
I2C[2]_SCL/
GP2[1]		 AA20 I/O IPU
DVDD		 VIN[0]A, VIN[0]B, UART5, I2C[2]
PINCNTL136
DSIS: PIN		 General-Purpose Input/Output (I/O) 2 [GP2] pin 1
VIN[0]A_DE/
VIN[0]B_HSYNC/
UART5_TXD/
I2C[2]_SDA/
GP2[0]		 AE21 I/O IPU
DVDD		 VIN[0]A, VIN[0]B, UART5, I2C[2]
PINCNTL135
DSIS: PIN		 General-Purpose Input/Output (I/O) 2 [GP2] pin 0
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS = De-selected Input State
(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the Internal Pull after Reset. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see Section 3.5.1, Pullup/Pulldown Resistors and Section 6.3.17, Pin Behaviors at Reset.
(3) Specifies the operating I/O supply voltage for each signal

Table 2-13 GP3 Terminal Functions

SIGNAL TYPE(1) OTHER(2) (3) MUXED DESCRIPTION
NAME NO.
GPIO3
Note: General-Purpose Input/Output (I/O) pins can also serve as external interrupt inputs.
CLKIN32/
CLKOUT0/
TIM3_IO/
GP3[31]		 J7 I/O IPD
DVDD		 CLKIN32, CLKOUT0, TIMER3
PINCNTL259
DSIS: PIN		 General-Purpose Input/Output (I/O) 3 [GP3] pin 31.
VOUT[1]_B_CB_C[2]/
GPMC_A[0]/
VIN[1]A_D[7]/
HDMI_CEC/
SPI[2]_D[0]/
GP3[30]		 AF28 I/O IPU
DVDD		 VOUT[1], GPMC, VIN[1]A, HDMI, SPI[2]
PINCNTL231
DSIS: PIN
MM: MUX1		 General-Purpose Input/Output (I/O) 3 [GP3] pin 30.
EMAC[0]_MRXD[2]/
EMAC[0]_RGRXD[1]/
VIN[1]B_D[7]/
EMAC[0]_RMTXEN/
GP3[30]		 R23 I/O IPD
DVDD_GPMC		 EMAC[0], VIN[1]B
PINCNTL242
DSIS: PIN
MM: MUX0
EMAC[0]_MRXD[1]/
EMAC[0]_RGRXD[0]/
VIN[1]B_D[6]/
EMAC[0]_RMTXD[1]/
GP3[29]		 P23 I/O IPD
DVDD_GPMC		 EMAC[0], VIN[1]B
PINCNTL241
DSIS: PIN		 General-Purpose Input/Output (I/O) 3 [GP3] pin 29.
EMAC[0]_MRXD[0]/
EMAC[0]_RGTXD[0]/
VIN[1]B_D[5]/
EMAC[0]_RMTXD[0]/
GP3[28]		 G28 I/O IPD
DVDD_GPMC		 EMAC[0], VIN[1]B
PINCNTL240
DSIS: PIN		 General-Purpose Input/Output (I/O) 3 [GP3] pin 28.
EMAC[0]_MRCLK/
EMAC[0]_RGTXC/
VIN[1]B_D[4]/
EMAC[0]_RMCRSDV/
SPI[3]_SCS[2]/
GP3[27]		 H27 I/O IPD
DVDD_GPMC		 EMAC[0], VIN[1]B, SPI[3]
PINCNTL239
DSIS: PIN		 General-Purpose Input/Output (I/O) 3 [GP3] pin 27.
EMAC[0]_MRXER/
EMAC[0]_RGTXCTL/
VIN[1]B_D[3]/
EMAC[0]_RMRXER/
GP3[26]		 J26 I/O IPD
DVDD_GPMC		 EMAC[0], VIN[1]B
PINCNTL238
DSIS: PIN		 General-Purpose Input/Output (I/O) 3 [GP3] pin 26.
EMAC[0]_MCRS/
EMAC[0]_RGRXD[2]/
VIN[1]B_D[2]/
EMAC[0]_RMRXD[1]/
GP3[25]		 R25 I/O IPD
DVDD_GPMC		 EMAC[0], VIN[1]B
PINCNTL237
DSIS: PIN		 General-Purpose Input/Output (I/O) 3 [GP3] pin 25.
EMAC[0]_MCOL/
EMAC[0]_RGRXCTL/
VIN[1]B_D[1]/
EMAC[0]_RMRXD[0]/
GP3[24]		 L23 I/O IPD
DVDD_GPMC		 EMAC[0], VIN[1]B
PINCNTL236
DSIS: PIN		 General-Purpose Input/Output (I/O) 3 [GP3] pin 24.
EMAC[0]_MTCLK/
EMAC[0]_RGRXC/
VIN[1]B_D[0]/
SPI[3]_SCS[3]/
I2C[2]_SDA/
GP3[23]		 L24 I/O IPD
DVDD_GPMC		 EMAC[0], VIN[1]B, SPI[3], I2C[2]
PINCNTL235
DSIS: PIN		 General-Purpose Input/Output (I/O) 3 [GP3] pin 23.
VOUT[1]_R_CR[2]/
GPMC_A[15]/
VIN[1]A_D[23]/
HDMI_HPDET/
SPI[2]_D[1]/
GP3[22]		 AE27 I/O IPD
DVDD		 VOUT[1], GPMC, VIN[1]A, HDMI, SPI[2]
PINCNTL230
DSIS: PIN		 General-Purpose Input/Output (I/O) 3 [GP3] pin 22.
VOUT[1]_R_CR[3]/
GPMC_A[14]/
VIN[1]A_D[22]/
HDMI_SDA/
SPI[2]_SCLK/
I2C[2]_SDA
GP3[21]		 AG28 I/O IPU
DVDD		 VOUT[1], GPMC, VIN[1]A, HDMI, SPI[2], I2C[2]
PINCNTL229
DSIS: PIN		 General-Purpose Input/Output (I/O) 3 [GP3] pin 21.
VOUT[1]_G_Y_YC[2]/
GPMC_A[13]/
VIN[1]A_D[21]/
HDMI_SCL/
SPI[2]_SCS[2]/
I2C[2]_SCL/
GP3[20]		 AF27 I/O IPU
DVDD		 VOUT[1], GPMC, VIN[1]A, HDMI, SPI[2], I2C[2]
PINCNTL228
DSIS: PIN		 General-Purpose Input/Output (I/O) 3 [GP3] pin 20.
VOUT[1]_R_CR[9]/
EMAC[1]_MTXEN/
VIN[1]A_D[20]/
UART5_TXD/
GP3[19]		 Y24 I/O IPD
DVDD		 VOUT[1], EMAC[1], VIN[1]A, UART5
PINCNTL227
DSIS: PIN		 General-Purpose Input/Output (I/O) 3 [GP3] pin 19.
VOUT[1]_R_CR[8]/
EMAC[1]_MTXD[7]/
VIN[1]A_D[19]/
UART5_RXD/
GP3[18]		 W23 I/O IPD
DVDD		 VOUT[1], EMAC[1], VIN[1]A, UART5
PINCNTL226
DSIS: PIN		 General-Purpose Input/Output (I/O) 3 [GP3] pin 18.
VOUT[1]_R_CR[7]/
EMAC[1]_MTXD[6]/
VIN[1]A_D[18]/
SPI[3]_D[0]/
GP3[17]		 V22 I/O IPD
DVDD		 VOUT[1], EMAC[1], VIN[1]A, SPI[3]
PINCNTL225
DSIS: PIN		 General-Purpose Input/Output (I/O) 3 [GP3] pin 17.
VOUT[1]_R_CR[6]/
EMAC[1]_MTXD[5]/
VIN[1]A_D[17]/
SPI[3]_D[1]/
GP3[16]		 AA25 I/O IPD
DVDD		 VOUT[1], EMAC[1], VIN[1]A, SPI[3]
PINCNTL224
DSIS: PIN		 General-Purpose Input/Output (I/O) 3 [GP3] pin 16.
VOUT[1]_R_CR[5]/
EMAC[1]_MTXD[4]/
VIN[1]A_D[16]/
SPI[3]_SCLK/
GP3[15]		 AC26 I/O IPD
DVDD		 VOUT[1], EMAC[1], VIN[1]A, SPI[3]
PINCNTL223
DSIS: PIN		 General-Purpose Input/Output (I/O) 3 [GP3] pin 15.
VOUT[1]_R_CR[4]/
EMAC[1]_MTXD[3]/
VIN[1]A_D[15]/
SPI[3]_SCS[1]/
GP3[14]		 AG27 I/O IPD
DVDD		 VOUT[1], EMAC[1], VIN[1]A, SPI[3]
PINCNTL222
DSIS: PIN		 General-Purpose Input/Output (I/O) 3 [GP3] pin 14.
VOUT[1]_G_Y_YC[9]/
EMAC[1]_MTXD[2]/
VIN[1]A_D[14]/
GP3[13]		 AD26 I/O IPD
DVDD		 VOUT[1], EMAC[1], VIN[1]A
PINCNTL221
DSIS: PIN		 General-Purpose Input/Output (I/O) 3 [GP3] pin 13.
VOUT[1]_G_Y_YC[8]/
EMAC[1]_MTXD[1]/
VIN[1]A_D[13]/
GP3[12]		 AE26 I/O IPD
DVDD		 VOUT[1], EMAC[1], VIN[1]A
PINCNTL220
DSIS: PIN		 General-Purpose Input/Output (I/O) 3 [GP3] pin 12.
VOUT[1]_G_Y_YC[7]/
EMAC[1]_MTXD[0]/
VIN[1]A_D[12]/
GP3[11]		 AF26 I/O IPD
DVDD		 VOUT[1], EMAC[1], VIN[1]A
PINCNTL219
DSIS: PIN		 General-Purpose Input/Output (I/O) 3 [GP3] pin 11.
VOUT[1]_G_Y_YC[6]/
EMAC[1]_GMTCLK/
VIN[1]A_D[11]/
GP3[10]		 AH27 I/O IPD
DVDD		 VOUT[1], EMAC[1], VIN[1]A
PINCNTL218
DSIS: PIN		 General-Purpose Input/Output (I/O) 3 [GP3] pin 10.
VOUT[1]_G_Y_YC[5]/
EMAC[1]_MRXDV/
VIN[1]A_D[10]/
GP3[9]		 AG26 I/O IPD
DVDD		 VOUT[1], EMAC[1], VIN[1]A
PINCNTL217
DSIS: PIN		 General-Purpose Input/Output (I/O) 3 [GP3] pin 9.
VOUT[1]_G_Y_YC[4]/
EMAC[1]_MRXD[7]/
VIN[1]A_D[9]/
GP3[8]		 W22 I/O IPD
DVDD		 VOUT[1], EMAC[1], VIN[1]A
PINCNTL216
DSIS: PIN		 General-Purpose Input/Output (I/O) 3 [GP3] pin 8.
VOUT[1]_G_Y_YC[3]/
EMAC[1]_MRXD[6]/
VIN[1]A_D[8]/
GP3[7]		 Y23 I/O IPD
DVDD		 VOUT[1], EMAC[1], VIN[1]A
PINCNTL215
DSIS: PIN		 General-Purpose Input/Output (I/O) 3 [GP3] pin 7.
VOUT[1]_B_CB_C[9]/
EMAC[1]_MRXD[5]/
VIN[1]A_D[6]/
I2C[3]_SDA/
GP3[6]		 AA24 I/O IPD
DVDD		 VOUT[1], EMAC[1], VIN[1]A, I2C[3]
PINCNTL214
DSIS: PIN		 General-Purpose Input/Output (I/O) 3 [GP3] pin 6.
VOUT[1]_B_CB_C[8]/
EMAC[1]_MRXD[4]/
VIN[1]A_D[5]/
I2C[3]_SCL/
GP3[5]		 AH26 I/O IPD
DVDD		 VOUT[1], EMAC[1], VIN[1]A, I2C[3]
PINCNTL213
DSIS: PIN		 General-Purpose Input/Output (I/O) 3 [GP3] pin 5.
VOUT[1]_B_CB_C[7]/
EMAC[1]_MRXD[3]/
VIN[1]A_D[4]/
UART3_TXD/
GP3[4]		 AC25 I/O IPD
DVDD		 VOUT[1], EMAC[1], VIN[1]A, UART3
PINCNTL212
DSIS: PIN		 General-Purpose Input/Output (I/O) 3 [GP3] pin 4.
VOUT[1]_B_CB_C[6]/
EMAC[1]_MRXD[2]/
VIN[1]A_D[3]/
UART3_RXD/
GP3[3]		 AD25 I/O IPD
DVDD		 VOUT[1], EMAC[1], VIN[1]A, UART3
PINCNTL211
DSIS: PIN		 General-Purpose Input/Output (I/O) 3 [GP3] pin 3.
VOUT[1]_B_CB_C[5]/
EMAC[1]_MRXD[1]/
VIN[1]A_D[2]/
UART4_TXD/
GP3[2]		 AF25 I/O IPD
DVDD		 VOUT[1], EMAC[1], VIN[1]A, UART4
PINCNTL210
DSIS: PIN		 General-Purpose Input/Output (I/O) 3 [GP3] pin 2.
VOUT[1]_B_CB_C[4]/
EMAC[1]_MRXD[0]/
VIN[1]A_D[1]/
UART4_RXD/
GP3[1]		 AG25 I/O IPD
DVDD		 VOUT[1], EMAC[1], VIN[1]A, UART4
PINCNTL209
DSIS: PIN		 General-Purpose Input/Output (I/O) 3 [GP3] pin 1.
VOUT[1]_B_CB_C[3]/
EMAC[1]_MRCLK/
VIN[1]A_D[0]/
UART4_CTS/
GP3[0]		 AH25 I/O IPD
DVDD		 VOUT[1], EMAC[1], VIN[1]A, UART4
PINCNTL208
DSIS: PIN		 General-Purpose Input/Output (I/O) 2 [GP2] pin 0.
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS = De-selected Input State
(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the Internal Pull after Reset. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see Section 3.5.1, Pullup/Pulldown Resistors and Section 6.3.17, Pin Behaviors at Reset.
(3) Specifies the operating I/O supply voltage for each signal

2.11.8 GPMC

Table 2-14 GPMC Terminal Functions

SIGNAL TYPE(1) OTHER(2) (3) MUXED DESCRIPTION
NAME NO.
GPMC_CLK/
GPMC_CS[5]/
GPMC_WAIT[1]/
CLKOUT1/
EDMA_EVT3/
TIM4_IO/
GP1[27]		 R26 O IPU
DVDD_GPMCB		 GPMC, CLKOUT1, EDMA, TIMER4, GP1
PINCNTL127
DSIS: 0		 GPMC Clock output
SD2_DAT[4]/
GPMC_A[27]/
GPMC_A[23]/
GPMC_CS[7]/
EDMA_EVT0/
TIM7_IO/
GP1[22]		 R24 O IPU
DVDD_GPMC		 SD2, GPMC, EDMA, TIMER7, GP1
PINCNTL116
DSIS: N/A		 GPMC Chip Select 7
GPMC_ADV_ALE/
GPMC_CS[6]/
TIM5_IO/
GP1[28]		 M26 O IPU
DVDD_GPMCB		 GPMC, TIMER5, GP1
PINCNTL128
DSIS: N/A		 GPMC Chip Select 6
GPMC_CLK/
GPMC_CS[5]/
GPMC_WAIT[1]/
CLKOUT1/
EDMA_EVT3/
TIM4_IO/
GP1[27]		 R26 O IPU
DVDD_GPMCB		 GPMC, CLKOUT1, EDMA, TIMER4, GP1
PINCNTL127
DSIS: N/A		 GPMC Chip Select 5
GPMC_CS[4]/
SD2_CMD/
GP1[8]		 P25 O IPU
DVDD_GPMC		 SD2, GP1
PINCNTL126
DSIS: N/A		 GPMC Chip Select 4
GPMC_CS[3]/
VIN[1]B_CLK/
SPI[2]_SCS[0]/
GP1[26]		 P26 O IPU
DVDD_GPMC		 VIN[1]B, SPI[2], GP1
PINCNTL125
DSIS: N/A		 GPMC Chip Select 3
GPMC_CS[2]/
GPMC_A[24]/
GP1[25]		 M25 O IPU
DVDD_GPMC		 GPMC, GP1
PINCNTL124
DSIS: N/A		 GPMC Chip Select 2
GPMC_CS[1]/
GPMC_A[25]/
GP1[24]		 K28 O IPU
DVDD_GPMCB		 GPMC, GP1
PINCNTL123
DSIS: N/A		 GPMC Chip Select 1
GPMC_CS[0]/
GP1[23]		 T28 O IPU
DVDD_GPMCB		 GP1
PINCNTL122
DSIS: N/A		 GPMC Chip Select 0
GPMC_WE U28 O IPU
DVDD_GPMCB		 –
PINCNTL130
DSIS: N/A		 GPMC Write Enable output
GPMC_OE_RE T27 O IPU
DVDD_GPMCB		 –
PINCNTL129
DSIS: N/A		 GPMC Output Enable output
GPMC_BE[1]/
GPMC_A[24]/
EDMA_EVT1/
TIM7_IO/
GP1[30]		 V28 O IPD
DVDD_GPMCB		 GPMC, EDMA, TIMER7, GP1
PINCNTL132
DSIS: N/A		 GPMC Upper Byte Enable output
GPMC_BE[0]_CLE/
GPMC_A[25]/
EDMA_EVT2/
TIM6_IO/
GP1[29]		 U27 O IPD
DVDD_GPMCB		 GPMC, EDMA, TIMER6, GP1
PINCNTL131
DSIS: PIN		 GPMC Lower Byte Enable output or Command Latch Enable output
GPMC_ADV_ALE/
GPMC_CS[6]/
TIM5_IO/
GP1[28]		 M26 O IPU
DVDD_GPMCB		 GPMC, TIMER5, GP1
PINCNTL128
DSIS: N/A		 GPMC Address Valid output or Address Latch Enable output
GPMC_CLK/
GPMC_CS[5]/
GPMC_WAIT[1]/
CLKOUT1/
EDMA_EVT3/
TIM4_IO/
GP1[27]		 R26 I IPU
DVDD_GPMCB		 GPMC, CLKOUT1, EDMA, TIMER4, GP1
PINCNTL127
DSIS: 1		 GPMC Wait input 1
GPMC_WAIT[0]/
GPMC_A[26]/
EDMA_EVT0/
GP1[31]		 W28 I IPU
DVDD_GPMCB		 GPMC, EDMA, GP1
PINCNTL133
DSIS: 1		 GPMC Wait input 0
EMAC[0]_MRXD[3]/
EMAC[1]_RGRXCTL/
GPMC_A[27]/
GPMC_A[26]/
GPMC_A[0]/
UART5_RXD		 J25 O IPD
DVDD_GPMC		 EMAC[0], EMAC[1], GPMC, UART5
PINCNTL243
DSIS: N/A
MM: MUX1		 GPMC Address 27
SD2_DAT[4]/
GPMC_A[27]/
GPMC_A[23]/
GPMC_CS[7]/
EDMA_EVT0/
TIM7_IO/
GP1[22]		 R24 O IPU
DVDD_GPMC		 SD2, GPMC, EDMA, TIMER7, GP1
PINCNTL116
DSIS: N/A
MM: MUX0
GPMC_WAIT[0]/
GPMC_A[26]/
EDMA_EVT0/
GP1[31]		 W28 O IPU
DVDD_GPMCB		 GPMC, EDMA, GP1
PINCNTL133
DSIS: N/A
MM: MUX2		 GPMC Address 26
EMAC[0]_MRXD[3]/
EMAC[1]_RGRXCTL/
GPMC_A[27]/
GPMC_A[26]/
GPMC_A[0]/
UART5_RXD		 J25 O IPD
DVDD_GPMC		 EMAC[0], EMAC[1], GPMC, UART5
PINCNTL243
DSIS: N/A
MM: MUX1
SD2_DAT[5]/
GPMC_A[26]/
GPMC_A[22]/
TIM6_IO/
GP1[21]		 P22 O IPU
DVDD_GPMC		 SD2, GPMC, TIMER6, GP1
PINCNTL115
DSIS: N/A
MM: MUX0
GPMC_BE[0]_CLE/
GPMC_A[25]/
EDMA_EVT2/
TIM6_IO/
GP1[29]		 U27 O IPD
DVDD_GPMCB		 GPMC, EDMA, TIMER6, GP1
PINCNTL131
DSIS: N/A
MM: MUX2		 GPMC Address 25
GPMC_CS[1]/
GPMC_A[25]/
GP1[24]		 K28 O IPU
DVDD_GPMCB		 GPMC, GP1
PINCNTL123
DSIS: N/A
MM: MUX1
SD2_DAT[6]/
GPMC_A[25]/
GPMC_A[21]/
UART2_TXD/
GP1[20]		 N23 O IPU
DVDD_GPMC		 SD2, GPMC, UART2, GP1
PINCNTL114
DSIS: N/A
MM: MUX0
GPMC_BE[1]/
GPMC_A[24]/
EDMA_EVT1/
TIM7_IO/
GP1[30]		 V28 O IPD
DVDD_GPMCB		 GPMC, EDMA, TIMER7, GP1
PINCNTL132
DSIS: N/A
MM: MUX2		 GPMC Address 24
GPMC_CS[2]/
GPMC_A[24]/
GP1[25]		 M25 O IPU
DVDD_GPMC		 GPMC, GP1
PINCNTL124
DSIS: N/A
MM: MUX1
SD2_DAT[7]/
GPMC_A[24]/
GPMC_A[20]/
UART2_RXD/
GP1[19]		 L25 O IPU
DVDD_GPMC		 SD2, GPMC, UART2, GP1
PINCNTL113
DSIS: N/A
MM: MUX0
SD2_DAT[4]/
GPMC_A[27]/
GPMC_A[23]/
GPMC_CS[7]/
EDMA_EVT0/
TIM7_IO/
GP1[22]		 R24 O IPU
DVDD_GPMC		 SD2, GPMC, EDMA, TIMER5, GP1
PINCNTL116
DSIS: N/A
MM: MUX1		 GPMC Address 23
GPMC_A[23]/
SPI[2]_SCLK/
HDMI_HPDET/
TIM5_IO/
GP1[18]		 AA26 O IPD
DVDD_GPMCB		 SPI[2], HDMI, TIMER5, GP1
PINCNTL112
DSIS: N/A
MM: MUX0
SD2_DAT[5]/
GPMC_A[26]/
GPMC_A[22]/
TIM6_IO/
GP1[21]		 P22 O IPU
DVDD_GPMC		 SD2, GPMC, TIMER6, GP1
PINCNTL115
DSIS: N/A
MM: MUX1		 GPMC Address 22
GPMC_A[22]/
SPI[2]_D[1]/
HDMI_CEC/
TIM4_IO/
GP1[17]		 AB27 O IPU
DVDD_GPMCB		 SPI[2], HDMI, TIMER4, GP1
PINCNTL111
DSIS: N/A
MM: MUX0
SD2_DAT[6]/
GPMC_A[25]/
GPMC_A[21]/
UART2_TXD/
GP1[20]		 N23 O IPU
DVDD_GPMC		 SD2, GPMC, UART2, GP1
PINCNTL114
DSIS: N/A
MM: MUX1		 GPMC Address 21
GPMC_A[21]/
SPI[2]_D[0]/
GP1[16]		 AC28 O IPD
DVDD_GPMCB		 SPI[2], GP1
PINCNTL110
DSIS: N/A
MM: MUX0
SD2_DAT[7]/
GPMC_A[24]/
GPMC_A[20]/
UART2_RXD/
GP1[19]		 L25 O IPU
DVDD_GPMC		 SD2, GPMC, UART2, GP1
PINCNTL113
DSIS: N/A
MM: MUX1		 GPMC Address 20
GPMC_A[20]/
SPI[2]_SCS[1]/
GP1[15]		 AD28 O IPU
DVDD_GPMCB		 SPI[2], GP1
PINCNTL109
DSIS: N/A
MM: MUX0
GPMC_A[19]/
TIM3_IO/
GP1[14]		 AC27 O IPD
DVDD_GPMCB		 TIMER2, GP1
PINCNTL108
DSIS: N/A		 GPMC Address 19
GPMC_A[18]/
TIM2_IO/
GP1[13]		 AE28 O IPD
DVDD_GPMCB		 TIMER2, GP1
PINCNTL107
DSIS: N/A		 GPMC Address 18
GPMC_A[17]/
GP2[6]		 V23 O IPD
DVDD_GPMCB		 GP2
PINCNTL106
DSIS: N/A		 GPMC Address 17
GPMC_A[16]/
GP2[5]		 AD27 O IPD
DVDD_GPMCB		 GP2
PINCNTL105
DSIS: N/A		 GPMC Address 16
VOUT[1]_R_CR[2]/
GPMC_A[15]/
VIN[1]A_D[23]/
HDMI_HPDET/
SPI[2]_D[1]/
GP3[22]		 AE27 O IPD
DVDD		 VOUT[1], VIN[1]A, HDMI, SPI[2],GP3
PINCNTL230
DSIS: N/A
MM: MUX1		 GPMC Address 15
EMAC[0]_MTXEN/
EMAC[1]_RGRXD[2]/
EMAC[1]_RMTXEN/
GPMC_A[15]/
UART1_RTS		 J23 O IPD
DVDD_GPMC		 EMAC[0], EMAC[1], UART1
PINCNTL258
DSIS: N/A
MM: MUX0
VOUT[1]_R_CR[3]/
GPMC_A[14]/
VIN[1]A_D[22]/
HDMI_SDA/
SPI[2]_SCLK/
I2C[2]_SDA/
GP3[21]		 AG28 O IPU
DVDD		 VOUT[1], VIN[1]A, HDMI, SPI[2], I2C[2], GP3
PINCNTL229
DSIS: N/A
MM: MUX1		 GPMC Address 14
EMAC[0]_MTXD[7]/
EMAC[1]_RGTXD[3]/
EMAC[1]_RMTXD[1]/
GPMC_A[14]/
UART1_CTS		 H24 O IPD
DVDD_GPMC		 EMAC[0], EMAC[1], UART1
PINCNTL257
DSIS: N/A
MM: MUX0
VOUT[1]_G_Y_YC[2]/
GPMC_A[13]/
VIN[1]A_D[21]/
HDMI_SCL/
SPI[2]_SCS[2]/
I2C[2]_SCL/
GP3[20]		 AF27 O IPU
DVDD		 VOUT[1], VIN[1]A, HDMI, SPI[2], I2C[2], GP3
PINCNTL228
DSIS: N/A
MM: MUX1		 GPMC Address 13
EMAC[0]_MTXD[6]/
EMAC[1]_RGRXD[0]/
EMAC[1]_RMTXD[0]/
GPMC_A[13]/
UART1_TXD		 J22 O IPD
DVDD_GPMC		 EMAC[0], EMAC[1], UART1
PINCNTL256
DSIS: N/A
MM: MUX0
VOUT[0]_FLD/
CAM_PCLK/
GPMC_A[12]/
UART2_RTS/
GP2[2]		 AF18 O IPD
DVDD_C		 VOUT[0], CAMERA_I/F, UART2, GP2
PINCNTL175
DSIS: N/A
MM: MUX1		 GPMC Address 12
EMAC[0]_MTXD[5]/
EMAC[1]_RGTXC/
EMAC[1]_RMCRSDV/
GPMC_A[12]/
UART1_RXD		 F27 O IPD
DVDD_GPMC		 EMAC[0], EMAC[1], UART1
PINCNTL255
DSIS: N/A
MM: MUX0
VOUT[1]_FLD/
CAM_FLD/
CAM_WE/
GPMC_A[11]/
UART2_CTS/
GP0[28]		 AB23 O IPD
DVDD_C		 VOUT[1], CAMERA_I/F, UART2, GP0
PINCNTL174
DSIS: N/A
MM: MUX1		 GPMC Address 11
EMAC[0]_MTXD[4]/
EMAC[1]_RGTXD[2]/
EMAC[1]_RMRXER/
GPMC_A[11]/
UART4_RTS		 G23 O IPD
DVDD_GPMC		 EMAC[0], EMAC[1], UART4
PINCNTL254
DSIS: N/A
MM: MUX0
VOUT[1]_B_CB_C[0]/
CAM_VS/
GPMC_A[10]/
UART2_TXD/
GP0[27]		 AD23 O IPU
DVDD_C		 VOUT[1], CAMERA_I/F, UART2, GP0
PINCNTL173
DSIS: N/A
MM: MUX1		 GPMC Address 10
EMAC[0]_MTXD[3]/
EMAC[1]_RGTXD[0]/
EMAC[1]_RMRXD[1]/
GPMC_A[10]/
UART4_CTS		 H23 O IPD
DVDD_GPMC		 EMAC[0], EMAC[1], UART4
PINCNTL253
DSIS: N/A
MM: MUX0
VOUT[1]_B_CB_C[1]/
CAM_HS/
GPMC_A[9]/
UART2_RXD/
GP0[26]		 AE23 O IPD
DVDD_C		 VOUT[1], CAMERA_I/F, UART2, GP0
PINCNTL172
DSIS: N/A
MM: MUX1		 GPMC Address 9
EMAC[0]_MTXD[2]/
EMAC[1]_RGTXCTL/
EMAC[1]_RMRXD[0]/
GPMC_A[9]/
UART4_TXD		 H22 O IPD
DVDD_GPMC		 EMAC[0], EMAC[1], UART4
PINCNTL252
DSIS: N/A
MM: MUX0
VOUT[1]_R_CR[0]/
CAM_D[0]/
GPMC_A[8]/
UART4_RTS/
GP0[25]		 AA22 O IPD
DVDD_C		 VOUT[1], CAMERA_I/F, UART4, GP0
PINCNTL171
DSIS: N/A
MM: MUX1		 GPMC Address 8
EMAC[0]_MTXD[1]/
EMAC[1]_RGTXD[1]/
GPMC_A[8]/
UART4_RXD		 H25 O IPD
DVDD_GPMC		 EMAC[0], EMAC[1], UART4
PINCNTL251
DSIS: N/A
MM: MUX0
VOUT[1]_R_CR[1]/
CAM_D[1]/
GPMC_A[7]/
UART4_CTS/
GP0[24]		 AC19 O IPD
DVDD_C		 VOUT[1], CAMERA_I/F, UART4, GP0
PINCNTL170
DSIS: N/A
MM: MUX1		 GPMC Address 7
EMAC[0]_MTXD[0]/
EMAC[1]_RGRXD[3]/
GPMC_A[7]/
SPI[2]_D[0]		 J24 O IPD
DVDD_GPMC		 EMAC[0], EMAC[1], SPI[2]
PINCNTL250
DSIS: N/A
MM: MUX0
VOUT[1]_G_Y_YC[0]/
CAM_D[2]/
GPMC_A[6]/
UART4_TXD/
GP0[23]		 AC18 O IPD
DVDD_C		 VOUT[1], CAMERA_I/F, UART4, GP0
PINCNTL169
DSIS: N/A
MM: MUX1		 GPMC Address 6
EMAC[0]_GMTCLK/
EMAC[1]_RGRXC/
GPMC_A[6]/
SPI[2]_D[1]		 K23 O IPD
DVDD_GPMC		 EMAC[0], EMAC[1], SPI[2]
PINCNTL249
DSIS: N/A
MM: MUX0
VOUT[1]_G_Y_YC[1]/
CAM_D[3]/
GPMC_A[5]/
UART4_RXD/
GP0[22]		 AD18 O IPU
DVDD_C		 VOUT[1], CAMERA_I/F, UART4, GP0
PINCNTL168
DSIS: N/A
MM: MUX1		 GPMC Address 5
EMAC[0]_MRXDV/
EMAC[1]_RGRXD[1]/
GPMC_A[5]/
SPI[2]_SCLK		 K22 O IPD
DVDD_GPMC		 EMAC[0], EMAC[1], SPI[2]
PINCNTL248
DSIS: N/A
MM: MUX0
SD2_DAT[0]/
GPMC_A[4]/
GP1[14]		 L26 O IPU
DVDD_GPMCB		 SD2, GP1
PINCNTL120
DSIS: N/A
MM: MUX1		 GPMC Address 4
EMAC[0]_MRXD[7]/
EMAC[0]_RGTXD[1]/
GPMC_A[4]/
SPI[2]_SCS[3]		 G27 O IPD
DVDD_GPMC		 EMAC[0], SPI[2]
PINCNTL247
DSIS: N/A
MM: MUX0
SD2_DAT[1]_ SDIRQ/
GPMC_A[3]/
GP1[13]		 M24 O IPU
DVDD_GPMC		 SD2, GP1
PINCNTL119
DSIS: N/A
MM: MUX1		 GPMC Address 3
EMAC[0]_MRXD[6]/
EMAC[0]_RGTXD[2]/
GPMC_A[3]/
UART5_RTS		 F28 O IPD
DVDD_GPMC		 EMAC[0], UART5
PINCNTL246
DSIS: N/A
MM: MUX0
SD2_DAT[2]_SDRW/
GPMC_A[2]/
GP2[6]		 K27 O IPU
DVDD_GPMC		 SD2, GP2
PINCNTL118
DSIS: N/A
MM: MUX1		 GPMC Address 2
EMAC[0]_MRXD[5]/
EMAC[0]_RGTXD[3]/
GPMC_A[2]/
UART5_CTS		 H26 O IPD
DVDD_GPMC		 EMAC[0], UART5
PINCNTL245
DSIS: N/A
MM: MUX0
SD2_DAT[3]/
GPMC_A[1]/
GP2[5]		 J28 O IPU
DVDD_GPMC		 SD2, GP2
PINCNTL117
DSIS: N/A
MM: MUX1		 GPMC Address 1
EMAC[0]_MRXD[4]/
EMAC[0]_RGRXD[3]/
GPMC_A[1]/
UART5_TXD		 T23 O IPD
DVDD_GPMC		 EMAC[0], UART5
PINCNTL244
DSIS: N/A
MM: MUX0
VOUT[1]_B_CB_C[2]/
GPMC_A[0]/
VIN[1]A_D[7]/
HDMI_CEC/
SPI[2]_D[0]/
GP3[30]		 AF28 O IPU
DVDD		 VOUT[1], VIN[1]A, HDMI, SPI[2], GP3
PINCNTL231
DSIS: N/A
MM: MUX1		 GPMC Address 0
EMAC[0]_MRXD[3]/
EMAC[1]_RGRXCTL/
GPMC_A[27]/
GPMC_A[26]/
GPMC_A[0]/
UART5_RXD		 J25 O IPD
DVDD_GPMC		 EMAC[0], EMAC[1], GPMC, UART5
PINCNTL243
DSIS: N/A
MM: MUX0
GPMC_D[15]/
BTMODE[15]		 Y25 I/O DIS
DVDD_GPMCB		 BTMODE
PINCNTL104
DSIS: PIN		 GPMC Multiplexed Data/Address I/Os.
GPMC_D[14]/
BTMODE[14]		 V24 I/O DIS
DVDD_GPMCB		 BTMODE
PINCNTL103
DSIS: PIN
GPMC_D[13]/
BTMODE[13]		 U23 I/O DIS
DVDD_GPMCB		 BTMODE
PINCNTL102
DSIS: PIN
GPMC_D[12]/
BTMODE[12]		 U24 I/O DIS
DVDD_GPMCB		 BTMODE
PINCNTL101
DSIS: PIN
GPMC_D[11]/
BTMODE[11]		 AA27 I/O DIS
DVDD_GPMCB		 BTMODE
PINCNTL100
DSIS: PIN
GPMC_D[10]/
BTMODE[10]		 Y26 I/O DIS
DVDD_GPMCB		 BTMODE
PINCNTL99
DSIS: PIN
GPMC_D[9]/
BTMODE[9]		 AB28 I/O DIS
DVDD_GPMCB		 BTMODE
PINCNTL98
DSIS: PIN
GPMC_D[8]/
BTMODE[8]		 Y27 I/O DIS
DVDD_GPMCB		 BTMODE
PINCNTL97
DSIS: PIN
GPMC_D[7]/
BTMODE[7]		 V25 I/O DIS
DVDD_GPMCB		 BTMODE
PINCNTL96
DSIS: PIN
GPMC_D[6]/
BTMODE[6]		 U25 I/O DIS
DVDD_GPMCB		 BTMODE
PINCNTL95
DSIS: PIN
GPMC_D[5]/
BTMODE[5]		 AA28 I/O DIS
DVDD_GPMCB		 BTMODE
PINCNTL94
DSIS: PIN
GPMC_D[4]/
BTMODE[4]		 V26 I/O DIS
DVDD_GPMCB		 BTMODE
PINCNTL93
DSIS: PIN
GPMC_D[3]/
BTMODE[3]		 W27 I/O DIS
DVDD_GPMCB		 BTMODE
PINCNTL92
DSIS: PIN
GPMC_D[2]/
BTMODE[2]		 V27 I/O DIS
DVDD_GPMCB		 BTMODE
PINCNTL91
DSIS: PIN
GPMC_D[1]/
BTMODE[1]		 Y28 I/O DIS
DVDD_GPMCB		 BTMODE
PINCNTL90
DSIS: PIN
GPMC_D[0]/
BTMODE[0]		 U26 I/O DIS+
DVDD_GPMCB		 BTMODE
PINCNTL89
DSIS: PIN
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS = De-selected Input State
(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the Internal Pull after Reset. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see Section 3.5.1, Pullup/Pulldown Resistors and the Section 6.3.17, Pin Behaviors at Reset.
(3) Specifies the operating I/O supply voltage for each signal

2.11.9 HDMI

Table 2-15 HDMI Terminal Functions

SIGNAL TYPE(1) OTHER(2) (3) MUXED DESCRIPTION
NAME NO.
HDMI_CLKP AG18 O –
VDDA_HDMI_1P8		 – HDMI Clock Output.

When the HDMI PHY is powered down, these pins should be left unconnected.
HDMI_CLKN AH18 O –
VDDA_HDMI_1P8		 –
HDMI_DN2 AH21 O –
VDDA_HDMI_1P8		 – HDMI Data 2 output.

When the HDMI PHY is powered down, these pins should be left unconnected.
HDMI_DP2 AG21 O –
VDDA_HDMI_1P8		 –
HDMI_DN1 AH20 O –
VDDA_HDMI_1P8		 – HDMI Data 1 output.

When the HDMI PHY is powered down, these pins should be left unconnected.
HDMI_DP1 AG20 O –
VDDA_HDMI_1P8		 –
HDMI_DN0 AH19 O –
VDDA_HDMI_1P8		 – HDMI Data 0 output.

When the HDMI PHY is powered down, these pins should be left unconnected.
HDMI_DP0 AG19 O –
VDDA_HDMI_1P8		 –
VOUT[1]_G_Y_YC[2]/
GPMC_A[13]/
VIN[1]A_D[21]/
HDMI_SCL/
SPI[2]_SCS[2]/
I2C[2]_SCL/
GP3[20]		 AF27 I/O IPU
DVDD		 VOUT[1], GPMC, VIN[1]ASPI[2], I2C[2], GP3
PINCNTL228
DSIS: 1
MM: MUX1		 HDMI I2C Serial Clock Output
I2C[1]_SCL/
HDMI_SCL		 AF24 I/O DVDD I2C[1]
PINCNTL78
DSIS: 1
MM: MUX0
VOUT[1]_R_CR[3]/
GPMC_A[14]/
VIN[1]A_D[22]/
HDMI_SDA/
SPI[2]_SCLK/
I2C[2]_SDA/
GP3[21]		 AG28 I/O IPU
DVDD		 VOUT[1], GPMC, VIN[1]ASPI[2], I2C[2], GP3
PINCNTL229
DSIS: 1
MM: MUX1		 HDMI I2C Serial Data I/O
I2C[1]_SDA/
HDMI_SDA		 AG24 I/O DVDD I2C[1]
PINCNTL79
DSIS: 1
MM: MUX0
VOUT[1]_B_CB_C[2]/
GPMC_A[0]/
VIN[1]A_D[7]/
HDMI_CEC/
SPI[2]_D[0]/
GP3[30]		 AF28 I/O IPU
DVDD		 VOUT[1], GPMC, VIN[1]A, SPI[2], GP3
PINCNTL231
DSIS: 1
MM: MUX1		 HDMI Consumer Electronics Control I/O
GPMC_A[22]/
SPI[2]_D[1]/
HDMI_CEC/
TIM4_IO/
GP1[17]		 AB27 I/O IPU
DVDD_GPMC		 GPMC, SPI[2], TIMER4, GP1
PINCNTL111
DSIS: 1
MM: MUX0
VOUT[1]_R_CR[2]/
GPMC_A[15]/
VIN[1]A_D[23]/
HDMI_HPDET/
SPI[2]_D[1]/
GP3[22]		 AE27 I IPD
DVDD		 VOUT[1], GPMC, VIN[1]ASPI[2], GP3
PINCNTL230
DSIS: 0
MM: MUX1		 HDMI Hot Plug Detect Input. Signals the connection / removal of an HDMI cable at the connector.
GPMC_A[23]/
SPI[2]_SCLK/
HDMI_HPDET/
TIM5_IO/
GP1[18]		 AA26 I IPD
DVDD_GPMC		 GPMC, SPI[2], TIMER5, GP1
PINCNTL112
DSIS: 0
MM: MUX0
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS = De-selected Input State
(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the Internal Pull after Reset. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see Section 3.5.1, Pullup/Pulldown Resistors and Section 6.3.17, Pin Behaviors at Reset.
(3) Specifies the operating I/O supply voltage for each signal

2.11.10 I2C

Table 2-16 I2C Terminal Functions

SIGNAL TYPE(1) OTHER(2) (3) MUXED DESCRIPTION
NAME NO.
I2C[0]
I2C[0]_SCL AC4 I/O DVDD –
PINCNTL263		 I2C[0] Clock I/O. For proper device operation, this pin must be pulled up via external resistor.
I2C[0]_SDA AB6 I/O DVDD –
PINCNTL264		 I2C[0] Data I/O. For proper device operation, this pin must be pulled up via external resistor.
I2C[1]
I2C[1]_SCL/
HDMI_SCL		 AF24 I/O DVDD HDMI
PINCNTL78
DSIS: 1		 I2C[1] Clock I/O. For proper device operation in I2C mode, this pin must be pulled up via external resistor.
I2C[1]_SDA/
HDMI_SDA		 AG24 I/O DVDD HDMI
PINCNTL79
DSIS: 1		 I2C[1] Data I/O. For proper device operation in I2C mode, this pin must be pulled up via external resistor.
I2C[2]
VIN[0]A_FLD/
VIN[0]B_VSYNC/
UART5_RXD/
I2C[2]_SCL/
GP2[1]		 AA20 I/O IPU
DVDD		 VIN[0]A, VIN[0]B,UART5, GP2
PINCNTL136
DSIS: 1
MM: MUX3		 I2C[2] Clock I/O. For proper device operation in I2C mode, this pin must be pulled up via external resistor.
VOUT[1]_G_Y_YC[2]/
GPMC_A[13]/
VIN[1]A_D[21]/
HDMI_SCL/
SPI[2]_SCS[2]/
I2C[2]_SCL/
GP3[20]		 AF27 I/O IPU
DVDD		 VOUT[1], GPMC, VIN[1]A, HDMI, SPI[2], GP3
PINCNTL228
DSIS: 1
MM: MUX2
VIN[0]A_D[16]/
CAM_D[8]/
I2C[2]_SCL/
GP0[10]		 AA21 I/O IPU
DVDD_C		 VIN[0]A, CAM I/F, GP0
PINCNTL156
DSIS: 1
MM: MUX1
UART0_DCD/
UART3_RXD/
SPI[0]_SCS[3]/
I2C[2]_SCL/
SD1_POW/
GP1[2]		 AH4 I/O IPU
DVDD		 UART0, UART3, SPI[0], SD1, GP1
PINCNTL74
DSIS: 1
MM: MUX0
EMAC[0]_MTCLK/
EMAC[0]_RGRXC/
VIN[1]B_D[0]/
SPI[3]_SCS[3]/
I2C[2]_SDA/
GP3[23]		 L24 I/O IPD
DVDD_GPMC		 EMAC[0], VIN[1]B, SPI[3], GP3
PINCNTL235
DSIS: 1
MM: MUX3		 I2C[2] Data I/O. For proper device operation in I2C mode, this pin must be pulled up via external resistor.
VOUT[1]_R_CR[3]/
GPMC_A[14]/
VIN[1]A_D[22]/
HDMI_SDA/
SPI[2]_SCLK/
I2C[2]_SDA/
GP3[21]		 AG28 I/O IPU
DVDD		 VOUT[1], GPMC, VIN[1]A, HDMI, SPI[2], GP3
PINCNTL229
DSIS: 1
MM: MUX2
VIN[0]A_DE/
VIN[0]B_HSYNC/
UART5_TXD/
I2C[2]_SDA/
GP2[0]		 AE21 I/O IPU
DVDD		 VIN[0]A, VIN[0]B, UART5, GP2
PINCNTL135
DSIS: 1
MM: MUX1
UART0_DSR/
UART3_TXD/
SPI[0]_SCS[2]/
I2C[2]_SDA/
SD1_SDWP/
GP1[3]		 AG4 I/O IPU
DVDD		 UART0, UART3, SPI[0], SD1, GP1
PINCNTL75
DSIS: 1
MM: MUX0
I2C3
VOUT[1]_B_CB_C[8]/
EMAC[1]_MRXD[4]/
VIN[1]A_D[5]/
I2C[3]_SCL/
GP3[5]		 AH26 I/O IPD
DVDD		 VOUT[1], EMAC[1], VIN[1]A, GP3
PINCNTL213
DSIS: 1
MM: MUX3		 I2C3 Clock I/O. For proper device operation in I2C mode, this pin must be pulled up via external resistor.
VIN[0]A_D[18]/
CAM_D[10]/
EMAC[1]_RMRXD[1]/
I2C[3]_SCL/
GP0[12]		 AF20 I/O IPU
DVDD_C		 VIN[0]A, CAM I/F, EMAC[1], GP0
PINCNTL158
DSIS: 1
MM: MUX2
DCAN0_RX/
UART2_RXD/
I2C[3]_SCL/
GP1[1]		 AG6 I/O IPU
DVDD		 DCAN0, UART2, GP1
PINCNTL69
DSIS: 1
MM: MUX1
MCA[0]_AXR[1]/
I2C[3]_SCL		 J1 I/O IPU
DVDD		 MCA[0]
PINCNTL22
DSIS: 1
MM: MUX0
VOUT[1]_B_CB_C[9]/
EMAC[1]_MRXD[5]/
VIN[1]A_D[6]/
I2C[3]_SDA/
GP3[6]		 AA24 I/O IPD
DVDD		 VOUT[1], EMAC[1], VIN[1]A, GP3
PINCNTL214
DSIS: 1
MM: MUX3		 I2C3 Data I/O. For proper device operation in I2C mode, this pin must be pulled up via external resistor.
VIN[0]A_D[19]/
CAM_D[11]/
EMAC[1]_RMRXD[0]/
I2C[3]_SDA/
GP0[13]		 AF21 I/O IPU
DVDD_C		 VIN[0]A, CAM I/F, EMAC[1], GP0
PINCNTL159
DSIS: 1
MM: MUX2
DCAN0_TX/
UART2_TXD/
I2C[3]_SDA/
GP1[0]		 AH6 I/O IPU
DVDD		 DCAN0, UART2, GP1
PINCNTL68
DSIS: 1
MM: MUX1
MCA[0]_AXR[2]/
I2C[3]_SDA		 L4 I/O IPU
DVDD		 MCA[0]
PINCNTL23
DSIS: 1
MM: MUX0
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS = De-selected Input State
(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the Internal Pull after Reset. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see Section 3.5.1, Pullup/Pulldown Resistors and the Section 6.3.17, Pin Behaviors at Reset.
(3) Specifies the operating I/O supply voltage for each signal

2.11.11 McASP

Table 2-17 McASP0 Terminal Functions

SIGNAL TYPE(1) OTHER(2)(3) MUXED DESCRIPTION
NAME NO.
McASP0
MCA[0]_ACLKR/
MCA[5]_AXR[2]		 K2 I/O IPD
DVDD		 MCA[5]
PINCNTL19
DSIS: 0		 McASP0 Receive Bit Clock I/O
MCA[0]_AFSR/
MCA[5]_AXR[3]		 K1 I/O IPD
DVDD		 MCA[5]
PINCNTL20
DSIS: 0		 McASP0 Receive Frame Sync I/O
MCA[0]_ACLKX R4 I/O IPD
DVDD		 –
PINCNTL17		 McASP0 Transmit Bit Clock I/O
AUD_CLKIN0/
MCA[0]_AXR[7]/
MCA[0]_AHCLKX/
MCA[3]_AHCLKX/USB1_DRVVBUS		 L5 I/O IPD
DVDD		 AUD_CLKIN0, MCA[0], MCA[3], USB1
PINCNTL14
DSIS: PIN		 McASP0 Transmit High-Frequency Master Clock I/O
MCA[0]_AFSX L3 I/O IPD
DVDD		 –
PINCNTL18		 McASP0 Transmit Frame Sync I/O
AUD_CLKIN2/
MCA[0]_AXR[9]/
MCA[2]_AHCLKX/
MCA[5]_AHCLKX/
EDMA_EVT2/
TIM3_IO/
GP0[9]		 H1 I/O IPD
DVDD		 AUD_CLKIN2, MCA[1], MCA[4], EDMA, TIMER2, GP0
PINCNTL16
DSIS: PIN
MM: MUX1		 McASP0 Transmit/Receive Data I/Os
MCA[0]_AXR[9]/
MCB_CLKX/
MCB_CLKR		 M6 I/O IPD
DVDD		 MCB
PINCNTL30
DSIS: PIN
MM: MUX0
AUD_CLKIN1/
MCA[0]_AXR[8]/
MCA[1]_AHCLKX/
MCA[4]_AHCLKX/
EDMA_EVT3/
TIM2_IO/
GP0[8]		 R5 I/O IPD
DVDD		 AUD_CLKIN1, MCA[1], MCA[4], EDMA, TIMER2, GP0
PINCNTL15
DSIS: PIN
MM: MUX1
MCA[0]_AXR[8]/
MCB_FSX/
MCB_FSR		 L1 I/O IPD
DVDD		 MCB
PINCNTL29
DSIS: PIN
MM: MUX0
AUD_CLKIN0/
MCA[0]_AXR[7]/
MCA[0]_AHCLKX/
MCA[3]_AHCLKX/USB1_DRVVBUS		 L5 I/O IPD
DVDD		 AUD_CLKIN0, MCA[0], MCA[3], USB1
PINCNTL14
DSIS: PIN
MM: MUX1
MCA[0]_AXR[7]/
MCB_DX		 L2 I/O IPD
DVDD		 MCB
PINCNTL28
DSIS: PIN
MM: MUX0
MCA[0]_AXR[6]/
MCB_DR		 M4 I/O IPD
DVDD		 MCB
PINCNTL27
DSIS: PIN		 McASP0 Transmit/Receive Data I/Os
MCA[0]_AXR[5]/
MCA[1]_AXR[9]		 M3 I/O IPD
DVDD		 MCA[1]
PINCNTL26
DSIS: PIN
MCA[0]_AXR[4]/
MCA[1]_AXR[8]		 R6 I/O IPD
DVDD		 MCA[1]
PINCNTL25
DSIS: PIN
MCA[0]_AXR[3]/ M5 I/O IPD
DVDD		 PINCNTL24
DSIS: PIN
MCA[0]_AXR[2]/
I2C[3]_SDA		 L4 I/O IPU
DVDD		 I2C[3]
PINCNTL23
DSIS: PIN
MCA[0]_AXR[1]/
I2C[3]_SCL		 J1 I/O IPU
DVDD		 I2C[3]
PINCNTL22
DSIS: PIN
MCA[0]_AXR[0] J2 I/O IPD
DVDD		 PINCNTL21
DSIS: PIN
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS = De-selected Input State
(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the Internal Pull during and after Reset. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see Section 3.5.1, Pullup/Pulldown Resistors and Section 6.3.17, Pin Behaviors at Reset.
(3) Specifies the operating I/O supply voltage for each signal

Table 2-18 McASP1 Terminal Functions

SIGNAL TYPE(1) OTHER(2)(3) MUXED DESCRIPTION
NAME NO.
McASP1
MCA[1]_ACLKR/
MCA[1]_AXR[4]		 M1 I/O IPD
DVDD		 MCA[1]
PINCNTL33
DSIS: 0		 McASP1 Receive Bit Clock I/O
MCA[1]_AFSR/
MCA[1]_AXR[5]		 M2 I/O IPD
DVDD		 MCA[1]
PINCNTL34
DSIS: 0		 McASP1 Receive Frame Sync I/O
MCA[1]_ACLKX U5 I/O IPD
DVDD		 –
PINCNTL31		 McASP1 Transmit Bit Clock I/O
AUD_CLKIN1/
MCA[0]_AXR[8]/
MCA[1]_AHCLKX/
MCA[4]_AHCLKX/
EDMA_EVT3/
TIM2_IO/
GP0[8]		 R5 I/O IPD
DVDD		 AUD_CLKIN1, MCA[0], MCA[4], EDMA, TIMER2, GP0
PINCNTL15
DSIS: PIN		 McASP1 Transmit High-Frequency Master Clock I/O
MCA[1]_AFSX V3 I/O IPD
DVDD		 –
PINCNTL32		 McASP1 Transmit Frame Sync I/O
MCA[3]_AXR[3]/
MCA[1]_AXR[9]/		 J6 I/O IPD
DVDD		 MCA[3]
PINCNTL50
DSIS: PIN
MM: MUX1		 McASP1 Transmit/Receive Data I/Os
MCA[0]_AXR[5]/
MCA[1]_AXR[9]		 M3 I/O IPD
DVDD		 MCA[0]
PINCNTL26
DSIS: PIN
MM: MUX0
MCA[3]_AXR[2]/
MCA[1]_AXR[8]/
GP0[20]		 F2 I/O IPD
DVDD		 MCA[3], GP0
PINCNTL49
DSIS: PIN
MM: MUX1
MCA[0]_AXR[4]/
MCA[1]_AXR[8]		 R6 I/O IPD
DVDD		 MCA[0]
PINCNTL25
DSIS: PIN
MM: MUX0
MCA[2]_AXR[3]/
MCA[1]_AXR[7]/
TIM3_IO/
GP0[15]		 H2 I/O IPD
DVDD		 MCA[2], TIMER3, GP0
PINCNTL44
DSIS: PIN
MCA[2]_AXR[2]/
MCA[1]_AXR[6]/
TIM2_IO/
GP0[14]		 V5 I/O IPD
DVDD		 MCA[2], TIMER2, GP0
PINCNTL43
DSIS: PIN
MCA[1]_AFSR/
MCA[1]_AXR[5]		 M2 I/O IPD
DVDD		 MCA[1]
PINCNTL34
DSIS: PIN
MCA[1]_ACLKR/
MCA[1]_AXR[4]		 M1 I/O IPD
DVDD		 MCA[1]
PINCNTL33
DSIS: PIN
MCA[1]_AXR[3]/
MCB_CLKR		 N6 I/O IPD
DVDD		 MCB
PINCNTL38
DSIS: PIN
MCA[1]_AXR[2]/
MCB_FSR		 R3 I/O IPD
DVDD		 MCB
PINCNTL37
DSIS: PIN
MCA[1]_AXR[1]/
SD0_DAT[5]/		 T6 I/O IPU
DVDD		 SD0
PINCNTL36
DSIS: PIN		 McASP1 Transmit/Receive Data I/Os
MCA[1]_AXR[0]/
SD0_DAT[4]/		 V4 I/O IPU
DVDD		 SD0
PINCNTL35
DSIS: PIN
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS = De-selected Input State
(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the Internal Pull during and after Reset. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see Section 3.5.1, Pullup/Pulldown Resistors and Section 6.3.17, Pin Behaviors at Reset.
(3) Specifies the operating I/O supply voltage for each signal

Table 2-19 McASP2 Terminal Functions

SIGNAL TYPE(1) OTHER(2)(3) MUXED DESCRIPTION
NAME NO.
McASP2
MCA[2]_ACLKX/
GP0[10]		 U6 I/O IPU
DVDD		 GP0
PINCNTL39
DSIS: 0		 McASP2 Transmit Bit Clock I/O
AUD_CLKIN2/
MCA[0]_AXR[9]/
MCA[2]_AHCLKX/
MCA[5]_AHCLKX/
EDMA_EVT2/
TIM3_IO/
GP0[9]		 H1 I/O IPD
DVDD		 AUD_CLKIN2, MCA[0], MCA[5], EDMA, TIMER3, GP0
PINCNTL16
DSIS: PIN		 McASP2 Transmit High-Frequency Master Clock I/O
MCA[2]_AFSX/
GP0[11]		 AA5 I/O IPU
DVDD		 GP0
PINCNTL40
DSIS: 0		 McASP2 Transmit Frame Sync I/O
MCA[2]_AXR[3]/
MCA[1]_AXR[7]/
TIM3_IO/
GP0[15]		 H2 I/O IPD
DVDD		 MCA[1], TIMER3, GP0
PINCNTL44
DSIS: PIN		 McASP2 Transmit/Receive Data I/Os
MCA[2]_AXR[2]/
MCA[1]_AXR[6]/
TIM2_IO/
GP0[14]		 V5 I/O IPD
DVDD		 MCA[1], TIMER2, GP0
PINCNTL43
DSIS: PIN
MCA[2]_AXR[1]/
SD0_DAT[7]/
UART5_TXD/
GP0[13]		 V6 I/O IPU
DVDD		 SD0, UART5, GP0
PINCNTL42
DSIS: PIN
MCA[2]_AXR[0]/
SD0_DAT[6]/
UART5_RXD/
GP0[12]		 N2 I/O IPU
DVDD		 SD0, UART5, GP0
PINCNTL41
DSIS: PIN
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS = De-selected Input State
(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the Internal Pull during and after Reset. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see Section 3.5.1, Pullup/Pulldown Resistors and Section 6.3.17,Pin Behaviors at Reset.
(3) Specifies the operating I/O supply voltage for each signal

Table 2-20 McASP3 Terminal Functions

SIGNAL TYPE(1) OTHER(2)(3) MUXED DESCRIPTION
NAME NO.
McASP3
MCA[3]_ACLKX/
GP0[16]		 G6 I/O IPD
DVDD		 GP0
PINCNTL45
DSIS: 0		 McASP3 Transmit Bit Clock I/O
AUD_CLKIN0/
MCA[0]_AXR[7]/
MCA[0]_AHCLKX/
MCA[3]_AHCLKX/USB1_DRVVBUS		 L5 I/O IPD
DVDD		 AUD_CLKIN0, MCA[0], USB1
PINCNTL14
DSIS: PIN		 McASP3 Transmit High-Frequency Master Clock I/O
MCA[3]_AFSX/
GP0[17]		 H4 I/O IPD
DVDD		 GP0
PINCNTL46
DSIS: 0		 McASP3 Transmit Frame Sync I/O
MCA[3]_AXR[3]/
MCA[1]_AXR[9]/		 J6 I/O IPD
DVDD		 MCA[1]
PINCNTL50
DSIS: PIN		 McASP3 Transmit/Receive Data I/Os
MCA[3]_AXR[2]/
MCA[1]_AXR[8]/
GP0[20]		 F2 I/O IPD
DVDD		 MCA[1], GP0
PINCNTL49
DSIS: PIN
MCA[3]_AXR[1]/
TIM5_IO/
GP0[19]		 G2 I/O IPD
DVDD		 TIMER5, GP0
PINCNTL48
DSIS: PIN
MCA[3]_AXR[0]/
TIM4_IO/
GP0[18]		 G1 I/O IPD
DVDD		 TIMER4, GP0
PINCNTL47
DSIS: PIN
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS = De-selected Input State
(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the Internal Pull before after Reset. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see Section 3.5.1, Pullup/Pulldown Resistors and Section 6.3.17, Pin Behaviors at Reset.
(3) Specifies the operating I/O supply voltage for each signal

Table 2-21 McASP4 Terminal Functions

SIGNAL TYPE(1) OTHER(2)(3) MUXED DESCRIPTION
NAME NO.
McASP4
MCA[4]_ACLKX/
GP0[21]		 K7 I/O IPD
DVDD		 GP0
PINCNTL51
DSIS: 0		 McASP4 Transmit Bit Clock I/O
AUD_CLKIN1/
MCA[0]_AXR[8]/
MCA[1]_AHCLKX/
MCA[4]_AHCLKX/
EDMA_EVT3/
TIM2_IO/
GP0[8]		 R5 I/O IPD
DVDD		 AUD_CLKIN1, MCA[0], MCA[1], EDMA, TIMER2, GP0
PINCNTL15
DSIS: PIN		 McASP4 Transmit High-Frequency Master Clock I/O
MCA[4]_AFSX/
GP0[22]		 H3 I/O IPD
DVDD		 GP0
PINCNTL52
DSIS: 0		 McASP4 Transmit Frame Sync I/O
MCA[5]_AXR[1]/
MCA[4]_AXR[3]/
TIM7_IO/
GP0[28]		 L6 I/O IPD
DVDD		 MCA[5], TIMER7, GP0
PINCNTL58
DSIS: PIN		 McASP4 Transmit/Receive Data I/Os
MCA[5]_AXR[0]/
MCA[4]_AXR[2]/
GP0[27]		 L7 I/O IPD
DVDD		 MCA[5], GP0
PINCNTL57
DSIS: PIN
MCA[4]_AXR[1]/
TIM6_IO/
GP0[24]		 J4 I/O IPD
DVDD		 TIMER6, GP0
PINCNTL54
DSIS: PIN
MCA[4]_AXR[0]/
GP0[23]		 H6 I/O IPD
DVDD		 GP0
PINCNTL53
DSIS: PIN
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the Internal Pull during and after Reset. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see Section 3.5.1, Pullup/Pulldown Resistors and Section 6.3.17, Pin Behaviors at Reset.
(3) Specifies the operating I/O supply voltage for each signal

Table 2-22 McASP5 Terminal Functions

SIGNAL TYPE(1) OTHER(2)(3) MUXED DESCRIPTION
NAME NO.
McASP5
MCA[5]_ACLKX/
GP0[25]		 J3 I/O IPD
DVDD		 GP0
PINCNTL55
DSIS: 0		 McASP5 Transmit Bit Clock I/O
AUD_CLKIN2/
MCA[0]_AXR[9]/
MCA[2]_AHCLKX/
MCA[5]_AHCLKX/
EDMA_EVT2/
TIM3_IO/
GP0[9]		 H1 I/O IPD
DVDD		 AUD_CLKIN2, MCA[0], MCA[2], EDMA, TIMER3, GP0
PINCNTL16
DSIS: PIN		 McASP5 Transmit High-Frequency Master Clock I/O
MCA[5]_AFSX/
GP0[26]		 H5 I/O IPD
DVDD		 GP0
PINCNTL56
DSIS: 0		 McASP5 Transmit Frame Sync I/O
MCA[0]_AFSR/
MCA[5]_AXR[3]		 K1 I/O IPD
DVDD		 MCA[0]
PINCNTL20
DSIS: PIN		 McASP5 Transmit/Receive Data I/Os
MCA[0]_ACLKR/
MCA[5]_AXR[2]		 K2 I/O IPD
DVDD		 MCA[0]
PINCNTL19
DSIS: PIN
MCA[5]_AXR[1]/
MCA[4]_AXR[3]/
TIM7_IO/
GP0[28]		 L6 I/O IPD
DVDD		 MCA[4], TIMER7, GP0
PINCNTL58
DSIS: PIN
MCA[5]_AXR[0]/
MCA[4]_AXR[2]/
GP0[27]		 L7 I/O IPD
DVDD		 MCA[4], GP0
PINCNTL57
DSIS: PIN
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS = De-selected Input State
(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the Internal Pull during and after Reset. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see Section 3.5.1, Pullup/Pulldown Resistors and Section 6.3.17, Pin Behaviors at Reset.

2.11.12 McBSP

Table 2-23 McBSP Terminal Functions

SIGNAL TYPE(1) OTHER(2)(3) MUXED DESCRIPTION
NAME NO.
McBSP
MCA[0]_AXR[9]/
MCB_CLKX/
MCB_CLKR		 M6 I/O IPD
DVDD		 MCA[0], MCB
PINCNTL30
DSIS: PIN
MM: MUX1		 McBSP Receive Clock I/O
MCA[1]_AXR[3]/
MCB_CLKR		 N6 I/O IPD
DVDD		 MCA[1]
PINCNTL38
DSIS: PIN
MM: MUX0
MCA[0]_AXR[8]/
MCB_FSX/
MCB_FSR 		L1 I/O IPD
DVDD		 MCA[0], MCB
PINCNTL29
DSIS: PIN
MM: MUX1		 McBSP Receive Frame Sync I/O
MCA[1]_AXR[2]/
MCB_FSR		 R3 I/O IPD
DVDD		 MCA[1], MCB
PINCNTL37
DSIS: PIN
MM: MUX0
MCA[0]_AXR[6]/
MCB_DR 		M4 I/O IPD
DVDD		 MCA[0]
PINCNTL27
DSIS: PIN		 McBSP Receive Data Input
MCA[0]_AXR[9]/
MCB_CLKX/
MCB_CLKR		 M6 I/O IPD
DVDD		 MCA[0], MCB
PINCNTL30
DSIS: PIN		 McBSP Transmit Clock I/O
MCA[0]_AXR[8]/
MCB_FSX/
MCB_FSR		 L1 I/O IPD
DVDD		 MCA[0], MCB
PINCNTL29
DSIS: PIN		 McBSP Transmit Frame Sync I/O
MCA[0]_AXR[7]/
MCB_DX 		L2 I/O IPD
DVDD		 MCA[0]
PINCNTL28
DSIS: PIN		 McBSP Transmit Data Output
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS = De-selected Input State
(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the Internal Pull during and after Reset. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see Section 3.5.1, Pullup/Pulldown Resistors and Section 6.3.17, Pin Behaviors at Reset.
(3) Specifies the operating I/O supply voltage for each signal

2.11.13 PCI-Express (PCIe)

Table 2-24 PCI-Express (PCIe) Terminal Functions

SIGNAL TYPE(1) OTHER(2)(3) DESCRIPTION
NAME NO.
PCIE_TXP0 AD2 O –
VDDA_PCIE_1P8		 PCIE Transmit Data Lane 0.

When the PCIe SERDES are powered down, these pins should be left unconnected.
PCIE_TXN0 AD1 O
PCIE_RXP0 AC2 I –
VDDA_PCIE_1P8		 PCIE Receive Data Lane 0.

When the PCIe SERDES are powered down, these pins should be left unconnected.
PCIE_RXN0 AC1 I
SERDES_CLKP AF1 I –
SERDES_CLK LDO
(internal)		 PCIE Serdes Reference Clock Inputs and optional SATA Reference Clock Inputs.
Shared between PCI-Express and Serial ATA. When PCI-Express is not used, and these pins are not used as optional SATA Reference Clock Inputs, these pins can be left unconnected.
SERDES_CLKN AF2 I –
SERDES_CLK LDO
(internal)
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS = De-selected Input State
(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the Internal Pull after Reset. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see Section 3.5.1, Pullup/Pulldown Resistors and Section 6.3.17, Pin Behaviors at Reset.
(3) Specifies the operating I/O supply voltage for each signal

2.11.14 Reset, Interrupts, and JTAG Interface

Table 2-25 RESET, Interrupts, and JTAG Terminal Functions

SIGNAL TYPE(1) OTHER(2)(3) MUXED DESCRIPTION
NAME NO.
RESET
RESET J5 I IPU
DVDD		 –
PINCNTL260		 Device Reset input
POR F1 I –
DVDD		 – Power-On Reset input
RSTOUT_WD_OUT K6 O DIS
DVDD		 –
PINCNTL262		 Reset output (RSTOUT) or watchdog out (WD_OUT)

For more detailed information on RSTOUT_WD_OUT pin behavior, see Section 6.3.14, RSTOUT_WD_OUT Pin.
INTERRUPTS
NMI H7 I IPU
DVDD		 –
PINCNTL261		 Nonmaskable Interrupt input
GP0[31:0] see
Table 2-10		 I/O see
NOTE 		see
Table 2-10		 Interrupt-capable general-purpose I/Os.
NOTE: All pins are multiplexed with other pin functions. See Table 2-10, GP0 Terminal Functions table for muxing and internal pullup/pulldown/disable details.
GP1[31:0] see
Table 2-11		 I/O see
NOTE 		see
Table 2-11		 Interrupt-capable general-purpose I/Os.
NOTE: All pins are multiplexed with other pin functions. See Table 2-11, GP1 Terminal Functions table for muxing and internal pullup/pulldown/disable details.
GP2[31:0] see
Table 2-12		 I/O see
NOTE 		see
Table 2-12		 Interrupt-capable general-purpose I/Os.
NOTE: All pins are multiplexed with other pin functions. See Table 2-12, GP2 Terminal Functions table for muxing and internal pullup/pulldown/disable details.
GP3[31:0] see
Table 2-13		 I/O see
NOTE 		see
Table 2-13		 Interrupt-capable general-purpose I/Os.
NOTE: All pins are multiplexed with other pin functions. See Table 2-13, GP3 Terminal Functions table for muxing and internal pullup/pulldown/disable details.
JTAG
TCLK W7 I IPU
DVDD		 – JTAG test clock input
RTCK AD4 O IPU/DIS
DVDD		 – JTAG return clock output
The internal pullup (IPU) is enabled for this pin when the device is in reset and the IPU is disabled (DIS) when reset is released.
TDI Y7 I IPU
DVDD		 – JTAG test data input
TDO AC5 O IPU
DVDD		 – JTAG test port data output
TMS AA7 I IPU
DVDD		 – JTAG test port mode select input. For proper operation, do not oppose the IPU on this pin.
TRST AA4 I IPD
DVDD		 – JTAG test port reset input
VOUT[0]_R_CR[2]/
EMU4/
GP2[26]		 AD9 I/O IPD
DVDD		 VOUT[0], GP2
PINCNTL196
DSIS: PIN		 Emulator pin 4
VOUT[0]_G_Y_YC[2]/
EMU3/
GP2[24]		 AH7 I/O IPD
DVDD		 VOUT[0], GP2
PINCNTL188
DSIS: PIN		 Emulator pin 3
VOUT[0]_B_CB_C[2]/
EMU2/
GP2[22]		 AG7 I/O IPD
DVDD		 VOUT[0], GP0
PINCNTL180
DSIS: PIN		 Emulator pin 2
EMU1 AE11 I/O IPU
DVDD		 – Emulator pin 1
EMU0 AG8 I/O IPU
DVDD		 – Emulator pin 0
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS = De-selected Input State
(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the Internal Pull during and after Reset. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see Section 3.5.1, Pullup/Pulldown Resistors and Section 6.3.17, Pin Behaviors at Reset.
(3) Specifies the operating I/O supply voltage for each signal

2.11.15 Serial ATA (SATA) Signals

Table 2-26 Serial ATA (SATA) Terminal Functions

SIGNAL TYPE(1) OTHER(2) (3) MUXED DESCRIPTION
NAME NO.
SATA_TXN0 AB1 O –
VDDA_SATA_1P8		 – Serial ATA Data Transmit.

When the SATA SERDES are powered down, these pins should be left unconnected.
SATA_TXP0 AB2 O –
VDDA_SATA_1P8		 –
SATA_RXN0 AA2 I –
VDDA_SATA_1P8		 – Serial ATA Data Receive.

When the SATA SERDES are powered down, these pins should be left unconnected.
SATA_RXP0 AA1 I –
VDDA_SATA_1P8		 –
SPI[0]_SCS[1]/
SD1_SDCD/
SATA_ACT0_LED/
EDMA_EVT1/
TIM4_IO/
GP1[6]		 AE5 O IPU
DVDD		 SPI[0], SD1, EDMA, TIMER 4, GP1
PINCNTL80
DSIS: N/A		 Serial ATA disk 0 Activity LED output
SERDES_CLKP AF1 I –
SERDES_CLK LDO (internal)		 – PCIE Serdes Reference Clock Inputs and optional SATA Reference Clock Inputs.
Shared between PCI-Express and Serial ATA. When PCI-Express is not used, and these pins are not used as optional SATA Reference Clock Inputs, these pins should be left unconnected.
SERDES_CLKN AF2 I –
SERDES_CLK LDO (internal)		 –
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS = De-selected Input State
(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the Internal Pull during and after Reset. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see Section 3.5.1, Pullup/Pulldown Resistors and Section 6.3.17, Pin Behaviors at Reset.
(3) Specifies the operating I/O supply voltage for each signal

2.11.16 SD Signals (MMC/SD/SDIO)

Table 2-27 SD0 Terminal Functions

SIGNAL TYPE(1) OTHER(2) (3) MUXED DESCRIPTION
NAME NO.
SD0_CLK/
GP0[1]		 Y6 O IPU
DVDD_SD		 GP0
PINCNTL8
DSIS: 1		 SD0 Clock output
SD0_CMD/
SD1_CMD/
GP0[2]		 N1 I/O IPU
DVDD_SD		 SD1, GP0
PINCNTL9
DSIS: 1		 SD0 Command input/output
SD0_DAT[0]/
SD1_DAT[4]/
GP0[3]		 R7 I/O IPU
DVDD_SD		 SD1, GP0
PINCNTL10
DSIS: PIN		 SD0 Data0 I/O. Functions as data bit 0 for 4-/8-bit SD mode and single data bit for 1-bit SD mode.
SD0_DAT[1]_SDIRQ/
SD1_DAT[5]/
GP0[4]		 Y5 I/O IPU
DVDD_SD		 SD1, GP0
PINCNTL11
DSIS: PIN		 SD0 Data1 I/O. Functions as data bit 1 for 4-/8-bit SD mode and as an IRQ input for 1-bit SD mode.
SD0_DAT[2]_SDRW/
SD1_DAT[6]/
GP0[5]		 Y3 I/O IPU
DVDD_SD		 SD1, GP0
PINCNTL12
DSIS: PIN		 SD0 Data2 I/O. Functions as data bit 2 for 4-/8-bit SD mode and as a Read Wait input for 1-bit SD mode.
SD0_DAT[3]/
SD1_DAT[7]/
GP0[6]		 Y4 I/O IPU
DVDD_SD		 SD1, GP0
PINCNTL13
DSIS: PIN		 SD0 Data3 I/O. Functions as data bit 3 for 4-/8-bit SD mode.
MCA[1]_AXR[0]/
SD0_DAT[4]/		 V4 I/O IPU
DVDD		 MCA[1]
PINCNTL35
DSIS: PIN		 SD0 Data4 I/O. Functions as data bit 4 for 8-bit SD mode.
MCA[1]_AXR[1]/
SD0_DAT[5]/		 T6 I/O IPU
DVDD		 MCA[1], SC0
PINCNTL36
DSIS: PIN		 SD0 Data5 I/O. Functions as data bit 5 for 8-bit SD mode.
MCA[2]_AXR[0]/
SD0_DAT[6]/
UART5_RXD/
GP0[12]		 N2 I/O IPU
DVDD		 MCA[2], UART5, GP0
PINCNTL41
DSIS: PIN		 SD0 Data6 I/O. Functions as data bit 6 for 8-bit SD mode.
MCA[2]_AXR[1]/
SD0_DAT[7]/
UART5_TXD/
GP0[13]		 V6 I/O IPU
DVDD		 MCA[2], UART5, GP0
PINCNTL42
DSIS: PIN		 SD0 Data7 I/O. Functions as data bit 7 for 8-bit SD mode.
UART0_CTS/
UART4_RXD/
DCAN1_TX/
SPI[1]_SCS[3]/
SD0_SDCD		 AE6 I IPD
DVDD		 UART0, UART4, DCAN1, SPI[1]
PINCNTL72
DSIS: 1		 SD0 Card Detect input
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS = De-selected Input State
(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the Internal Pull after Reset. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see Section 3.5.1, Pullup/Pulldown Resistors and Section 6.3.17, Pin Behaviors at Reset.
(3) Specifies the operating I/O supply voltage for each signal

Table 2-28 SD1 Terminal Functions

SIGNAL TYPE(1) OTHER(2) (3) MUXED DESCRIPTION
NAME NO.
SD1_CLK P3 O IPU
DVDD_SD		 –
PINCNTL1
DSIS: N/A		 SD1 Clock output
SD0_CMD/
SD1_CMD/
GP0[2]		 N1 I/O IPU
DVDD_SD		 SD0, GP0
PINCNTL9
DSIS: N/A
MM: MUX1		 SD1 Command input/output
SD1_CMD/
GP0[0]		 P2 I/O IPU
DVDD_SD		 GP1
PINCNTL2
DSIS: N/A
MM: MUX0
SD1_DAT[0] P1 I/O IPU
DVDD_SD		 –
PINCNTL3		 SD1 Data0 I/O. Functions as data bit 0 for 4-/8-bit SD mode and single data bit for 1-bit SD mode.
SD1_DAT[1]_SDIRQ P5 I/O IPU
DVDD_SD		 –
PINCNTL4		 SD1 Data1 I/O. Functions as data bit 1 for 4-/8-bit SD mode and as an IRQ input for 1-bit SD mode.
SD1_DAT[2]_SDRW P4 I/O IPU
DVDD_SD		 –
PINCNTL5		 SD1 Data2 I/O. Functions as data bit 2 for 4-/8-bit SD mode and as a Read Wait input for 1-bit SD mode.
SD1_DAT[3] P6 I/O IPU
DVDD_SD		 –
PINCNTL6		 SD1 Data3 I/O. Functions as data bit 3 for 4-/8-bit SD mode.
SD0_DAT[0]/
SD1_DAT[4]/
GP0[3]		 R7 I/O IPU
DVDD_SD		 SD0, GP0
PINCNTL10
DSIS: PIN		 SD1 Data4 I/O. Functions as data bit 4 for 8-bit SD mode.
SD0_DAT[1]_SDIRQ/
SD1_DAT[5]/
GP0[4]		 Y5 I/O IPU
DVDD_SD		 SD0, GP0
PINCNTL11
DSIS: PIN		 SD1 Data5 I/O. Functions as data bit 5 for 8-bit SD mode.
SD0_DAT[2]_SDRW/
SD1_DAT[6]/
GP0[5]		 Y3 I/O IPU
DVDD_SD		 SD0, GP0
PINCNTL12
DSIS: PIN		 SD1 Data6 I/O. Functions as data bit 6 for 8-bit SD mode.
SD0_DAT[3]/
SD1_DAT[7]/
GP0[6]		 Y4 I/O IPU
DVDD_SD		 SD0, GP0
PINCNTL13
DSIS: PIN		 SD1 Data7 I/O. Functions as data bit 7 for 8-bit SD mode.
UART0_DCD/
UART3_RXD/
SPI[0]_SCS[3]/
I2C[2]_SCL/
SD1_POW/
GP1[2]		 AH4 O IPU
DVDD		 UART0, UART3, SPI[0], I2C[2], GP1
PINCNTL74
DSIS: PIN		 SD1 Card Power Enable output
SPI[0]_SCS[1]/
SD1_SDCD/
SATA_ACT0_LED/
EDMA_EVT1/
TIM4_IO/
GP1[6]		 AE5 I IPU
DVDD		 SPI[0], SATA, EDMA, TIM4, GP1
PINCNTL80
DSIS: 1		 SD1 Card Detect input
UART0_DSR/
UART3_TXD/
SPI[0]_SCS[2]/
I2C[2]_SDA/
SD1_SDWP/
GP1[3]		 AG4 I IPU
DVDD		 UART0, UART3, SPI[0], I2C[2], GP1
PINCNTL75
DSIS: 0		 SD1 Card Write Protect input
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS = De-selected Input State
(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the Internal Pull after Reset. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see Section 3.5.1, Pullup/Pulldown Resistors and Section 6.3.17, Pin Behaviors at Reset.
(3) Specifies the operating I/O supply voltage for each signal

Table 2-29 SD2 Terminal Functions

SIGNAL TYPE(1) OTHER(2) (3) MUXED DESCRIPTION
NAME NO.
SD2_SCLK/
GP1[15]		 M23 O IPU
DVDD_GPMC		 GP1
PINCNTL121
DSIS: N/A		 SD2 Clock output
GPMC_CS[4]/
SD2_CMD/
GP1[8]		 P25 I/O IPU
DVDD_GPMC		 GPMC, GP1
PINCNTL126
DSIS: N/A		 SD2 Command input/output
SD2_DAT[0]/
GPMC_A[4]/
GP1[14]		 L26 I/O IPU
DVDD_GPMC		 GPMC, GP1
PINCNTL120
DSIS: PIN		 SD2 Data0 I/O. Functions as data bit 0 for 4-/8-bit SD mode and single data bit for 1-bit SD mode.
SD2_DAT[1]_SDIRQ/
GPMC_A[3]/
GP1[13]		 M24 I/O IPU
DVDD_GPMC		 GMPC, GP1
PINCNTL119
DSIS: PIN		 SD2 Data1 I/O. Functions as data bit 1 for 4-/8-bit SD mode and as an IRQ input for 1-bit SD mode
SD2_DAT[2]_SDRW/
GPMC_A[2]/
GP2[6]		 K27 I/O IPU
DVDD_GPMC		 GPMC, GP2
PINCNTL118
DSIS: PIN		 SD2 Data2 I/O. Functions as data bit 2 for 4-/8-bit SD mode and as a Read Wait input for 1-bit SD mode.
SD2_DAT[3]/
GPMC_A[1]/
GP2[5]		 J28 I/O IPU
DVDD_GPMC		 GPMC, GP2
PINCNTL117
DSIS: PIN		 SD2 Data3 I/O. Functions as data bit 3 for 4-/8-bit SD mode.
SD2_DAT[4]/
GPMC_A[27]/
GPMC_A[23]/
GPMC_CS[7]/
EDMA_EVT0/
TIM7_IO/
GP1[22]		 R24 I/O IPU
DVDD_GPMC		 GPMC, EDMA, TIM7, GP1
PINCNTL116
DSIS: PIN		 SD2 Data4 I/O. Functions as data bit 4 for 8-bit SD mode.
SD2_DAT[5]/
GPMC_A[26]/
GPMC_A[22]/
TIM6_IO/
GP1[21]		 P22 I/O IPU
DVDD_GPMC		 GPMC, TIM6, GP1
PINCNTL115
DSIS: PIN		 SD2 Data5 I/O. Functions as data bit 5 for 8-bit SD mode.
SD2_DAT[6]/
GPMC_A[25]/
GPMC_A[21]/
UART2_TXD/
GP1[20]		 N23 I/O IPU
DVDD_GPMC		 GPMC, UART2, GP1
PINCNTL114
DSIS: PIN		 SD2 Data6 I/O. Functions as data bit 6 for 8-bit SD mode.
SD2_DAT[7]/
GPMC_A[24]/
GPMC_A[20]/
UART2_RXD/
GP1[19]		 L25 I/O IPU
DVDD_GPMC		 GPMC, UART2, GP1
PINCNTL113
DSIS: PIN		 SD2 Data7 I/O. Functions as data bit 7 for 8-bit SD mode.
UART0_RTS/
UART4_TXD/
DCAN1_RX/
SPI[1]_SCS[2]/
SD2_SDCD		 AF5 I IPD
DVDD		 UART0, UART4, DCAN1, SPI[1]
PINCNTL73
DSIS: 1		 SD2 Card Detect input.
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS = De-selected Input State
(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the Internal Pull during and after Reset. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see Section 3.5.1, Pullup/Pulldown Resistors and Section 6.3.17, Pin Behaviors at Reset.
(3) Specifies the operating I/O supply voltage for each signal

2.11.17 SPI

Table 2-30 SPI 0 Terminal Functions

SIGNAL TYPE(1) OTHER(2) (3) MUXED DESCRIPTION
NAME NO.
SPI[0]_SCLK AC7 I/O IPU
DVDD		 –
PINCNTL82		 SPI Clock I/O
UART0_DCD/
UART3_RXD/
SPI[0]_SCS[3]/
I2C[2]_SCL/
SD1_POW/
GP1[2]		 AH4 I/O IPU
DVDD		 UART0, UART3, I2C[2], SD1, GP1
PINCNTL74
DSIS: PIN		 SPI Chip Select I/O
UART0_DSR/
UART3_TXD/
SPI[0]_SCS[2]/
I2C[2]_SDA/
SD1_SDWP/
GP1[3]		 AG4 I/O IPU
DVDD		 UART0, UART3, I2C[2], SD1, GP1
PINCNTL75
DSIS: PIN
SPI[0]_SCS[1]/
SD1_SDCD/
SATA_ACT0_LED/
EDMA_EVT1/
TIM4_IO/
GP1[6]		 AE5 I/O IPU
DVDD		 SD1, SATA, EDMA, TIMER4, GP1
PINCNTL80
DSIS: PIN
SPI[0]_SCS[0] AD6 I/O IPU
DVDD		 –
PINCNTL81
SPI[0]_D[1] AF3 I/O IPU
DVDD		 –
PINCNTL83		 SPI Data I/O. Can be configured as either MISO or MOSI
SPI[0]_D[0] AE3 I/O IPU
DVDD		 –
PINCNTL84
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS = De-selected Input State
(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the Internal Pull during and after Reset. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see Section 3.5.1, Pullup/Pulldown Resistors and Section 6.3.17, Pin Behaviors at Reset.
(3) Specifies the operating I/O supply voltage for each signal

Table 2-31 SPI 1 Terminal Functions

SIGNAL TYPE(1) OTHER(2) (3) MUXED DESCRIPTION
NAME NO.
SPI[1]_SCLK/
GP1[17]		 AC3 I/O IPU
DVDD		 GP1
PINCNTL86
DSIS: PIN		 SPI Clock I/O
UART0_CTS/
UART4_RXD/
DCAN1_TX/
SPI[1]_SCS[3]/
SD0_SDCD		 AE6 I/O IPU
DVDD		 UART0, UART4, DCAN1, SD0
PINCNTL72
DSIS: PIN		 SPI Chip Select I/O
UART0_RTS/
UART4_TXD/
DCAN1_RX/
SPI[1]_SCS[2]/
SD2_SDCD		 AF5 I/O IPU
DVDD		 UART0, UART4, DCAN1, SD2
PINCNTL73
DSIS: PIN
DEVOSC_WAKE/
SPI[1]_SCS[1]/
TIM5_IO/
GP1[7]		 W6 I/O IPU
DVDD_SD		 DEVOSC, TIMER5, GP1
PINCNTL7
DSIS: PIN
SPI[1]_SCS[0]/
GP1[16]		 AD3 I/O IPU
DVDD		 GP1
PINCNTL85
DSIS: PIN
SPI[1]_D[1]/
GP1[18]		 AA3 I/O IPU
DVDD		 GP1
PINCNTL87
DSIS: PIN		 SPI Data I/O. Can be configured as either MISO or MOSI
SPI[1]_D[0]/
GP1[26]		 AA6 I/O IPU
DVDD		 GP1
PINCNTL88
DSIS: PIN
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS = De-selected Input State
(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the Internal Pull during and after Reset. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see Section 3.5.1, Pullup/Pulldown Resistors and Section 6.3.17, Pin Behaviors at Reset.
(3) Specifies the operating I/O supply voltage for each signal

Table 2-32 SPI 2 Terminal Functions

SIGNAL TYPE(1) OTHER(2) (3) MUXED DESCRIPTION
NAME NO.
EMAC[0]_MRXDV/
EMAC[1]_RGRXD[1]/
GPMC_A[5]/
SPI[2]_SCLK		 K22 I/O IPD
DVDD_GPMC		 EMAC[0], EMAC[1], GPMC
PINCNTL248
DSIS: 1
MM: MUX2		 SPI Clock I/O
VOUT[1]_R_CR[3]/
GPMC_A[14]/
VIN[1]A_D[22]/
HDMI_SDA/
SPI[2]_SCLK/
I2C[2]_SDA/
GP3[21]		 AG28 I/O IPU
DVDD		 VOUT[1], GPMC, VIN[1]A, HDMI, I2C[2], GP3
PINCNTL229
DSIS: 1
MM: MUX1
GPMC_A[23]/
SPI[2]_SCLK/
HDMI_HPDET/
TIM5_IO/
GP1[18]		 AA26 I/O IPD
DVDD_GPMC		 GPMC, HDMI, TIMER5, GP1
PINCNTL112
DSIS: 1
MM: MUX0
EMAC[0]_MRXD[7]/
EMAC[0]_RGTXD[1]/
GPMC_A[4]/
SPI[2]_SCS[3]/		 G27 I/O IPD
DVDD_GPMC		 EMAC[0], GPMC
PINCNTL247
DSIS: 1		 SPI Chip Select I/O
VOUT[1]_G_Y_YC[2]/
GPMC_A[13]/
VIN[1]A_D[21]/
HDMI_SCL/
SPI[2]_SCS[2]/
I2C[2]_SCL/
GP3[20]		 AF27 I/O IPU
DVDD		 VOUT[1]. VIN[1]A, HDMI, I2C[2], GP3
PINCNTL228
DSIS: 1
GPMC_A[20]/
SPI[2]_SCS[1]/
GP1[15]		 AD28 I/O IPU
DVDD_GPMC		 GPMC, GP1
PINCNTL109
DSIS: 1
GPMC_CS[3]/
VIN[1]B_CLK/
SPI[2]_SCS[0]/
GP1[26]		 P26 I/O IPU
DVDD_GPMC		 GPMC, VIN[1]B, GP1
PINCNTL125
DSIS: 1
EMAC[0]_GMTCLK/
EMAC[1]_RGRXC/
GPMC_A[6]/
SPI[2]_D[1]		 K23 I/O IPD
DVDD_GPMC		 EMAC[0], EMAC[1], GPMC
PINCNTL249
DSIS: PIN
MM: MUX2		 SPI Data I/O. Can be configured as either MISO or MOSI
VOUT[1]_R_CR[2]/
GPMC_A[15]/
VIN[1]A_D[23]/
HDMI_HPDET/
SPI[2]_D[1]/
GP3[22]		 AE27 I/O IPD
DVDD		 VOUT[1], GPMC, VIN[1]A, HDMI, GP3
PINCNTL230
DSIS: PIN
MM: MUX1
GPMC_A[22]/
SPI[2]_D[1]/
HDMI_CEC/
TIM4_IO/
GP1[17]		 AB27 I/O IPU
DVDD_GPMC		 GPMC, HDMI, TIMER 4, GP1
PINCNTL111
DSIS: PIN
MM: MUX0
EMAC[0]_MTXD[0]/
EMAC[1]_RGRXD[3]/
GPMC_A[7]/
SPI[2]_D[0]		 J24 I/O IPD
DVDD_GPMC		 EMAC[0], EMAC[1], GPMC
PINCNTL250
DSIS: PIN
MM: MUX2
VOUT[1]_B_CB_C[2]/
GPMC_A[0]/
VIN[1]A_D[7]/
HDMI_CEC/
SPI[2]_D[0]/
GP3[30]		 AF28 I/O IPU
DVDD		 VOUT[1], GPMC, VIN[1]A, HDMI, GP3
PINCNTL231
DSIS: PIN
MM: MUX1
GPMC_A[21]/
SPI[2]_D[0]/
GP1[16]		 AC28 I/O IPD
DVDD_GPMC		 GPMC, GP1
PINCNTL110
DSIS: PIN
MM: MUX0
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS = De-selected Input State
(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the Internal Pull during and after Reset. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see Section 3.5.1, Pullup/Pulldown Resistors and Section 6.3.17, Pin Behaviors at Reset.
(3) Specifies the operating I/O supply voltage for each signal

Table 2-33 SPI 3 Terminal Functions

SIGNAL TYPE(1) OTHER(2) (3) MUXED DESCRIPTION
NAME NO.
VOUT[0]_AVID/
VOUT[0]_FLD/
SPI[3]_SCLK/
TIM7_IO/
GP2[21]		 AA10 I/O IPD
DVDD		 VOUT[0], TIMER 7, GP2
PINCNTL179
DSIS: 1
MM: MUX2		 SPI Clock I/O
VOUT[1]_R_CR[5]/
EMAC[1]_MTXD[4]/
VIN[1]A_D[16]/
SPI[3]_SCLK/
GP3[15]		 AC26 I/O IPD
DVDD		 VOUT[0], EMAC[1], VIN[1]A, GP3
PINCNTL223
DSIS: 1
MM: MUX1
VIN[0]A_D[21]/
CAM_D[13]/
EMAC[1]_RMTXD[0]/
SPI[3]_SCLK/
GP0[15]		 AE18 I/O IPD
DVDD_C		 VIN[0]A, CAMERA_I/F, EMAC[1], GP0
PINCNTL161
DSIS: 1
MM: MUX0
EMAC[0]_MTCLK/
EMAC[0]_RGRXC/
VIN[1]B_D[0]/
SPI[3]_SCS[3]/
I2C[2]_SDA/
GP3[23] 		L24 I/O IPD
DVDD		 EMAC[0], VIN[1]B, I2C[2], GP3
PINCNTL235
DSIS: 1		 SPI Chip Select I/O
EMAC[0]_MRCLK/
EMAC[0]_RGTXC/
VIN[1]B_D[4]/
EMAC[0]_RMCRSDV/
SPI[3]_SCS[2]/
GP3[27] 		H27 I/O IPD
DVDD_GPMC		 EMAC[0], VIN[1]B, GP3
PINCNTL239
DSIS: 1
VOUT[1]_R_CR[4]/
EMAC[1]_MTXD[3]/
VIN[1]A_D[15]/
SPI[3]_SCS[1]/
GP3[14]		 AG27 I/O IPD
DVDD		 VOUT[1]. EMAC[1], VIN[1]A, GP3
PINCNTL222
DSIS: 1
VIN[0]A_D[20]/
CAM_D[12]/
EMAC[1]_RMCRSDV/
SPI[3]_SCS[0]/
GP0[14] 		AC17 I/O IPD
DVDD_C		 VIN[0]A, CAMERA,_I/F, EMAC[1]_RM, GP0
PINCNTL160
DSIS: 1
VOUT[1]_HSYNC/
EMAC[1]_MCOL/
VIN[1]A_VSYNC/
SPI[3]_D[1]/
UART3_RTS/
GP2[29]		 AC24 I/O IPD
DVDD		 VOUT[1], EMAC[1], VIN[1]A, UART3, GP2
PINCNTL205
DSIS: PIN
MM: MUX2		 SPI Data I/O. Can be configured as either MISO or MOSI
VOUT[1]_R_CR[6]/
EMAC[1]_MTXD[5]/
VIN[1]A_D[17]/
SPI[3]_D[1]/
GP3[16]		 AA25 I/O IPD
DVDD		 VOUT[1], EMAC[1], VIN[1]A, GP3
PINCNTL224
DSIS: PIN
MM: MUX1
VIN[0]A_D[22]/
CAM_D[14]/
EMAC[1]_RMTXD[1]/
SPI[3]_D[1]/
GP0[16]		 AC21 I/O IPD
DVDD_C		 VIN[0]A, CAMERA_I/F, EMAC[1]_RM, GP0
PINCNTL162
DSIS: PIN
MM: MUX0
VOUT[1]_VSYNC/
EMAC[1]_MCRS/
VIN[1]A_FLD/
VIN[1]A_DE/
SPI[3]_D[0]/
UART3_CTS/
GP2[30]		 AA23 I/O IPD
DVDD		 VOUT[1], EMAC[1], VIN[1]A, UART3, GP2
PINCNTL206
DSIS: PIN
MM: MUX2
VOUT[1]_R_CR[7]/
EMAC[1]_MTXD[6]/
VIN[1]A_D[18]/
SPI[3]_D[0]/
GP3[17]		 V22 I/O IPD
DVDD		 VOUT[1], EMAC[1], VIN[1]A, GP3
PINCNTL225
DSIS: PIN
MM: MUX1
VIN[0]A_D[23]/
CAM_D[15]/
EMAC[1]_RMTXEN/
SPI[3]_D[0]/
GP0[17]		 AC16 I/O IPD
DVDD_C		 VIN[0]A, CAMERA_I/F, EMAC[1], GP0
PINCNTL163
DSIS: PIN
MM: MUX0
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS = De-selected Input State
(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the Internal Pull during and after Reset. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see Section 3.5.1, Pullup/Pulldown Resistors and Section 6.3.17, Pin Behaviors at Reset.
(3) Specifies the operating I/O supply voltage for each signal

2.11.18 Oscillator/PLL, Audio Reference Clocks, and Clock Generator

Table 2-34 Oscillator/PLL, Audio Reference Clocks, and Clock Generator Terminal Functions

SIGNAL TYPE(1) OTHER(2) (3) MUXED DESCRIPTION
NAME NO.
CLOCK GENERATOR
VIN[0]A_D[12]_BD[4]/
CLKOUT1/
GP2[17]		 AG17 I/O IPD
DVDD		 VIN[0]A, GP2
PINCNTL152
DSIS: PIN		 Device Clock output 1. Can be used as a system clock for other devices.
GPMC_CLK/
GPMC_CS[5]/
GPMC_WAIT[1]/
CLKOUT1/
EDMA_EVT3/
TIM4_IO/
GP1[27]		 R26 O IPU
DVDD_GPMC		 GPMC, EDMA, TIM4, GP1
PINCNTL127
DSIS: N/A
VIN[0]B_CLK/
CLKOUT0/
GP1[9]		 AE17 I/O IPD
DVDD		 VIN[0]B, GP1
PINCNTL134
DSIS: PIN		 Device Clock output 0. Can be used as a system clock for other devices.
CLKIN32/
CLKOUT0/
TIM3_IO/
GP3[31]		 J7 O IPD
DVDD		 CLKIN32, TIM3, GP3
PINCNTL259
DSIS: N/A
OSCILLATOR/PLL
DEVOSC_MXI/
DEV_CLKIN		 AH2 A I –
VDDA_1P8 		– Device Crystal input. Crystal connection to internal oscillator for system clock. Functions as DEV_CLKIN clock input when an external oscillator is used.
DEVOSC_MXO AH3 A O –
VDDA_1P8		 – Device Crystal output. Crystal connection to internal oscillator for system clock. When device oscillator is BYPASSED, leave this pin unconnected.
VSSA_DEVOSC AG3 GND Supply Ground for DEV Oscillator. If the internal oscillator is bypassed, DEVOSC_VSS should be connected to ground (VSS).
AUXOSC_MXI/
AUX_CLKIN		 R1 A I –
VDDA_1P8 		– Auxiliary Crystal input [Optional Audio/Video Reference Crystal Input]. Crystal connection to internal oscillator for auxiliary clock. Functions as AUX_CLKIN clock input when an external oscillator is used.
AUXOSC_MXO T1 A O –
VDDA_1P8		 – Auxiliary Crystal output [Optional Audio/Video Reference Crystal Output]. When auxiliary oscillator is BYPASSED, leave this pin unconnected.
VSSA_AUXOSC R2 GND Supply Ground for AUX Oscillator. If the internal oscillator is bypassed, AUXOSC_VSS should be connected to ground (VSS).
CLKIN32/
CLKOUT0/
TIM3_IO/
GP3[31]		 J7 I IPD
DVDD		 CLKOUT0, TIMER 3, GP3
PINCNTL259
DSIS: PIN		 RTC Clock input. Optional 32.768 KHz clock for RTC reference.
DEVOSC_WAKE/
SPI[1]_SCS[1]/
TIM5_IO/
GP1[7]		 W6 I IPU
DVDD_SD		 SPI[1], TIMER 5, GP1
PINCNTL7
DSIS: 1		 Oscillator Wake-up input.
AUDIO REFERENCE CLOCKS
AUD_CLKIN2/
MCA[0]_AXR[9]/
MCA[2]_AHCLKX/
MCA[5]_AHCLKX/
EDMA_EVT2/
TIM3_IO/
GP0[9]		 H1 I IPD
DVDD		 MCA[0], MCA[2], MCA[5], EDMA, TIMER 3, GP0
PINCNTL16
DSIS: PIN		 Audio Reference Clock 2 for Audio Peripherals.
AUD_CLKIN1/
MCA[0]_AXR[8]/
MCA[1]_AHCLKX/
MCA[4]_AHCLKX/
EDMA_EVT3/
TIM2_IO/
GP0[8]		 R5 I IPD
DVDD		 MCA[0], MCA[1], MCA[4], EDMA, TIMER 2, GP0
PINCNTL15
DSIS: PIN		 Audio Reference Clock 1 for Audio Peripherals.
AUD_CLKIN0/
MCA[0]_AXR[7]/
MCA[0]_AHCLKX/
MCA[3]_AHCLKX/USB1_DRVVBUS		 L5 I IPD
DVDD		 MCA[0], MCA[3], USB1
PINCNTL14
DSIS: PIN		 Audio Reference Clock 0 for Audio Peripherals.
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS = De-selected Input State
(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the Internal Pull during and after Reset. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see Section 3.5.1, Pullup/Pulldown Resistors and Section 6.3.17, Pin Behaviors at Reset.
(3) Specifies the operating I/O supply voltage for each signal

2.11.19 Timer

Table 2-35 Timer Terminal Functions

SIGNAL TYPE(1) OTHER(2) (3) MUXED DESCRIPTION
NAME NO.
Timers 8-1 and Watchdog Timer 0
Timer 8 and Timer1
There are no external pins for these timers.
Timers TCLKIN
TCLKIN/
GP0[30]		 T2 I IPD
DVDD		 GP0
PINCNTL60
DSIS: 0		 Timer external clock input
Timer 7
GPMC_BE[1]/
GPMC_A[24]/
EDMA_EVT1/
TIM7_IO/
GP1[30]		 V28 I/O IPD
DVDD_GPMC		 GPMC, EDMA, GP1
PINCNTL132
DSIS: PIN
MM: MUX3		 Timer 7 capture event input or PWM output
SD2_DAT4
GPMC_A[27]/
GPMC_A[23]/
GPMC_CS[7]/
EDMA_EVT0/
TIM7_IO/
GP1[22]		 R24 I/O IPU
DVDD_GPMC		 SD2, GPMC, EDMA, GP1
PINCNTL116
DSIS: PIN
MM: MUX2
VOUT[0]_AVID/
VOUT[0]_FLD/
SPI[3]_SCLK/
TIM7_IO/
GP2[21]		 AA10 I/O IPD
DVDD		 VOUT[0], SPI[3], GP2
PINCNTL179
DSIS: PIN
MM: MUX1
MCA[5]_AXR[1]/
MCA[4]_AXR[3]/
TIM7_IO/
GP0[28]		 L6 I/O IPD
DVDD		 MCA[5], MCA[4], GP0
PINCNTL58
DSIS: PIN
MM: MUX0
Timer 6
GPMC_BE[0]_CLE/
GPMC_A[25]/
EDMA_EVT2/
TIM6_IO/
GP1[29]		 U27 I/O IPD
DVDD_GPMC		 GPMC, EDMA, GP1
PINCNTL131
DSIS: PIN
MM: MUX3		 Timer 6 capture event input or PWM output
SD2_DAT[5]/
GPMC_A[26]/
GPMC_A[22]/
TIM6_IO/
GP1[21]		 P22 I/O IPU
DVDD_GPMC		 SD2, GPMC, GP1
PINCNTL115
DSIS: PIN
MM: MUX2
VOUT[1]_AVID/
EMAC[1]_MRXER/
VIN[1]A_CLK/
UART4_RTS/
TIM6_IO/
GP2[31]		 Y22 I/O IPD
DVDD		 VOUT[1], EMAC[1], VIN[1]A, UART4, GP2
PINCNTL207
DSIS: PIN
MM: MUX1
MCA[4]_AXR[1]/
TIM6_IO/
GP0[24]		 J4 I/O IPD
DVDD		 MCA[4], GP0
PINCNTL54
DSIS: PIN
MM: MUX0
Timer 5
GPMC_ADV_ALE/
GPMC_CS[6]/
TIM5_IO/
GP1[28]		 M26 I/O IPU
DVDD_GPMC		 GPMC, GP1
PINCNTL128
DSIS: PIN
MM: MUX3		 Timer 5 capture event input or PWM output
GPMC_A[23]/
SPI[2]_SCLK/
HDMI_HPDET/
TIM5_IO/
GP1[18]		 AA26 I/O IPD
DVDD_GPMC		 GPMC, SPI[2], HDMI, GP1
PINCNTL112
DSIS: PIN
MM: MUX2
DEVOSC_WAKE/
SPI[1]_SCS[1]/
TIM5_IO/
GP1[7]		 W6 I/O IPU
DVDD_SD		 OSC, SPI[1], GP1
PINCNTL7
DSIS: PIN
MM: MUX1
MCA[3]_AXR[1]/
TIM5_IO/
GP0[19]		 G2 I/O IPD
DVDD		 MCA[3], GP0
PINCNTL48
DSIS: PIN
MM: MUX0
Timer 4
GPMC_CLK/
GPMC_CS[5]/
GPMC_WAIT[1]/
CLKOUT1/
EDMA_EVT3/
TIM4_IO/
GP1[27]		 R26 I/O IPU
DVDD_GPMC		 GPMC, CLKOUT1, EDMA, GP1
PINCNTL127
DSIS: PIN
MM: MUX3		 Timer 4 capture event input or PWM output
GPMC_A[22]/
SPI[2]_D[1]/
HDMI_CEC/
TIM4_IO/
GP1[17]		 AB27 I/O IPU
DVDD_GPMC		 GPMC, SPI[2], HDMI, GP1
PINCNTL111
DSIS: PIN
MM: MUX2
SPI[0]_SCS[1]/
SD1_SDCD/
SATA_ACT0_LED/
EDMA_EVT1/
TIM4_IO/
GP1[6]		 AE5 I/O IPU
DVDD		 SPI[0], SD1, SATA, EDMA, GP1
PINCNTL80
DSIS: PIN
MM: MUX1
MCA[3]_AXR[0]/
TIM4_IO/
GP0[18]		 G1 I/O IPD
DVDD		 MCA[3], GP0
PINCNTL47
DSIS: PIN
MM: MUX0
Timer 3
CLKIN32/
CLKOUT0/
TIM3_IO/
GP3[31]		 J7 I/O IPD
DVDD		 CLKIN32, CLKOUT, GP3
PINCNTL259
DSIS: PIN
MM: MUX3		 Timer 3 capture event input or PWM output
GPMC_A[19]/
TIM3_IO/
GP1[14]		 AC27 I/O IPD
DVDD_GPMC		 GPMC, GP1
PINCNTL108
DSIS: PIN
MM: MUX2
AUD_CLKIN2/
MCA[0]_AXR[9]/
MCA[2]_AHCLKX/
MCA[5]_AHCLKX/
EDMA_EVT2/
TIM3_IO/
GP0[9]		 H1 I/O IPD
DVDD		 AUD_CLKIN2, MCA[0], MCA[2]. MCA[5], EDMA, GP0
PINCNTL16
DSIS: PIN
MM: MUX1
MCA[2]_AXR[3]/
MCA[1]_AXR[7]/
TIM3_IO/
GP0[15]		 H2 I/O IPD
DVDD		 MCA[2], MCA[1], GP0
PINCNTL44
DSIS: PIN
MM: MUX0
Timer 2
EMAC_RMREFCLK/
TIM2_IO/
GP1[10]		 J27 I/O IPD
DVDD_GPMC		 EMAC, GP1
PINCNTL232
DSIS: PIN
MM: MUX3		 Timer 2 capture event input or PWM output
GPMC_A[18]/
TIM2_IO/
GP0[13]		 AE28 I/O IPD
DVDD_GPMC		 GPMC, GP0
PINCNTL107
DSIS: PIN
MM: MUX2
AUD_CLKIN1/
MCA[0]_AXR[8]/
MCA[1]_AHCLKX/
MCA[4]_AHCLKX/
EDMA_EVT3/
TIM2_IO/
GP0[8]		 R5 I/O IPD
DVDD		 AUD_CLKIN1, MCA[0], MCA[1], MCA[4], EDMA, GP0
PINCNTL15
DSIS: PIN
MM: MUX1
MCA[2]_AXR[2]/
MCA[1]_AXR[6]/
TIM2_IO/
GP0[14]		 V5 I/O IPD
DVDD		 MCA[2], MCA[1], GP0
PINCNTL43
DSIS: PIN
MM: MUX0
Watchdog Timer 0
RSTOUT_WD_OUT O DIS
DVDD		 –
PINCNTL262		 Watchdog timer 0 event output
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS = De-selected Input State
(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the Internal Pull after Reset. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see Section 3.5.1, Pullup/Pulldown Resistors and Section 6.3.17, Pin Behaviors at Reset.
(3) Specifies the operating I/O supply voltage for each signal

2.11.20 UART

Table 2-36 UART0 Terminal Functions

SIGNAL TYPE(1) OTHER(2) (3) MUXED DESCRIPTION
NAME NO.
UART0
UART0_RXD AH5 I IPU
DVDD		 –
PINCNTL70
DSIS: PIN		 UART0 Receive Data Input. Functions as IrDA receive input in IrDA modes and CIR receive input in CIR mode.
UART0_TXD AG5 O IPU
DVDD		 –
PINCNTL71
DSIS: PIN		 UART0 Transmit Data Output. Functions as CIR transmit output in CIR mode.
UART0_RTS/
UART4_TXD/
DCAN1_RX/
SPI[1]_SCS[2]/
SD2_SDCD		 AF5 O IPU
DVDD		 UART4, DCAN1, SPI[1], SD2
PINCNTL73
DSIS: PIN		 UART0 Request to Send Output. Indicates module is ready to receive data. Functions as transmit data output in IrDA modes.
UART0_CTS/
UART4_RXD/
DCAN1_TX/
SPI[1]_SCS[3]/
SD0_SDCD		 AE6 I/O IPU
DVDD		 UART4, DCAN1, SPI[1], SD0
PINCNTL72
DSIS: 1		 UART0 Clear to Send Input. Functions as SD transceiver control output in IrDA and CIR modes.
UART0_DTR/
UART3_CTS/
UART1_TXD/
GP1[4]		 AG2 O IPU
DVDD		 UART3, UART1, GP1
PINCNTL76
DSIS: PIN		 UART0 Data Terminal Ready Output
UART0_DSR/
UART3_TXD/
SPI[0]_SCS[2]/
I2C[2]_SDA/
SD1_SDWP/
GP1[3]		 AG4 I IPU
DVDD		 UART3, SPI[0], I2C[2], SD1, GP1
PINCNTL75
DSIS: 1		 UART0 Data Set Ready Input
UART0_DCD/
UART3_RXD/
SPI[0]_SCS[3]/
I2C[2]_SCL/
SD1_POW/
GP1[2]		 AH4 I IPU
DVDD		 UART3, SPI[0], I2C[2], SD1, GP1
PINCNTL74
DSIS: 1		 UART0 Data Carrier Detect Input
UART0_RIN/
UART3_RTS/
UART1_RXD/
GP1[5]		 AF4 I IPU
DVDD		 UART3, UART1, GP1
PINCNTL77
DSIS: 1		 UART0 Ring Indicator Input
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS = De-selected Input State
(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the Internal Pull after Reset. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see Section 3.5.1, Pullup/Pulldown Resistors and Section 6.3.17, Pin Behaviors at Reset.
(3) Specifies the operating I/O supply voltage for each signal

Table 2-37 UART1 Terminal Functions

SIGNAL TYPE(1) OTHER(2) (3) MUXED DESCRIPTION
NAME NO.
UART1
EMAC[0]_MTXD[5]/
EMAC[1]_RGTXC/
EMAC[1]_RMCRSDV/
GPMC_A[12]/
UART1_RXD		 F27 I IPD
DVDD_GPMC		 EMAC[0], EMAC[1], GPMC
PINCNTL255
DSIS: 1
MM: MUX1		 UART1 Receive Data Input. Functions as IrDA receive input in IrDA modes and CIR receive input in CIR mode.
UART0_RIN/
UART3_RTS/
UART1_RXD/
GP1[5]		 AF4 I IPU
DVDD		 UART0, UART3, GP1
PINCNTL77
DSIS: 1
MM: MUX0
EMAC[0]_MTXD[6]/
EMAC[1]_RGRXD[0]/
EMAC[1]_RMTXD[0]/
GPMC_A[13]/
UART1_TXD		 J22 O IPD
DVDD_GPMC		 EMAC[0], EMAC[1], GPMC
PINCNTL256
DSIS: PIN
MM: MUX1		 UART1 Transmit Data Output. Functions as CIR transmit output in CIR mode.
UART0_DTR/
UART3_CTS/
UART1_TXD/
GP1[4]		 AG2 O IPU
DVDD		 UART0, UART3, GP1
PINCNTL76
DSIS: PIN
MM: MUX0
EMAC[0]_MTXEN/
EMAC[1]_RGRXD[2]/
EMAC[1]_RMTXEN/
GPMC_A[15]/
UART1_RTS		 J23 O IPD
DVDD_GPMC		 EMAC[0], EMAC[1], GPMC
PINCNTL258
DSIS: PIN		 UART1 Request to Send Output. Indicates module is ready to receive data. Functions as transmit data output in IrDA modes.
EMAC[0]_MTXD[7]/
EMAC[1]_RGTXD[3]/
EMAC[1]_RMTXD[1]/
GPMC_A[14]/
UART1_CTS		 H24 I/O IPD
DVDD_GPMC		 EMCA[0], EMAC[1], GPMC
PINCNTL257
DSIS: 1		 UART1 Clear to Send Input. Functions as SD transceiver control output in IrDA and CIR modes.
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS = De-selected Input State
(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the Internal Pull after Reset. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see Section 3.5.1, Pullup/Pulldown Resistors and Section 6.3.17, Pin Behaviors at Reset.
(3) Specifies the operating I/O supply voltage for each signal

Table 2-38 UART2 Terminal Functions

SIGNAL TYPE(1) OTHER(2) (3) MUXED DESCRIPTION
NAME NO.
UART2
SD2_DAT[7]/
GPMC_A[24]/
GPMC_A[20]/
UART2_RXD/
GP1[19]		 L25 I IPU
DVDD_GPMC		 SD2, GPMC, GP1
PINCNTL113
DSIS: 1
MM: MUX3		 UART2 Receive Data Input. Functions as IrDA receive input in IrDA modes and CIR receive input in CIR mode.
DCAN0_RX/
UART2_RXD/
I2C[3]_SCL/
GP1[1]		 AG6 I IPU
DVDD		 DCAN0, I2C[3], GP1
PINCNTL69
DSIS: 1
MM: MUX2
UART2_RXD/
GP0[29]		 U4 I IPD
DVDD		 GP0
PINCNTL59
DSIS: 1
MM: MUX1
VOUT[1]_B_CB_C[1]/
CAM_HS/
GPMC_A[9]/
UART2_RXD/
GP0[26]		 AE23 I IPD
DVDD_C		 VOUT[1], CAMERA_I/F, GPMC, GP0
PINCNTL172
DSIS: 1
MM: MUX0
SD2_DAT[6]/
GPMC_A[25]/
GPMC_A[21]/
UART2_TXD/
GP1[20]		 N23 O IPU
DVDD_GPMC		 SD2, GPMC, GP1
PINCNTL114
DSIS: PIN
MM: MUX3		 UART2 Transmit Data Output. Functions as CIR transmit output in CIR mode.
DCAN0_TX/
UART2_TXD/
I2C[3]_SDA/
GP1[0]		 AH6 O IPU
DVDD		 DCAN0, I2C[3], GP1
PINCNTL68
DSIS: PIN
MM: MUX2
UART2_TXD/
GP0[31]		 U3 O IPD
DVDD		 GP0
PINCNTL61
DSIS: PIN
MM: MUX1
VOUT[1]_B_CB_C[0]/
CAM_VS/
GPMC_A[10]/
UART2_TXD/
GP0[27]		 AD23 O IPU
DVDD_C		 VOUT[1], CAMERA_I/F, GPMC, GP0
PINCNTL173
DSIS: PIN
MM: MUX0
VOUT[0]_FLD/
CAM_PCLK/
GPMC_A[12]/
UART2_RTS/
GP2[2]		 AF18 O IPD
DVDD_C		 VOUT[0], CAMERA_I/F, GPMC, GP2
PINCNTL175
DSIS: PIN		 UART2 Request to Send Output. Indicates module is ready to receive data. Functions as transmit data output in IrDA modes.
VOUT[1]_FLD/
CAM_FLD/
CAM_WE/
GPMC_A[11]/
UART2_CTS/
GP0[28]		 AB23 I/O IPD
DVDD_C		 VOUT[1], CAMERA_I/F, GPMC, GP0
PINCNTL174
DSIS: 1		 UART2 Clear to Send Input. Functions as SD transceiver control output in IrDA and CIR modes.
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS = De-selected Input State
(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the Internal Pull after Reset. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see Section 3.5.1, Pullup/Pulldown Resistors and Section 6.3.17, Pin Behaviors at Reset.
(3) Specifies the operating I/O supply voltage for each signal

Table 2-39 UART3 Terminal Functions

SIGNAL TYPE(1) OTHER(2) (3) MUXED DESCRIPTION
NAME NO.
UART3
VOUT[1]_B_CB_C[6]/
EMAC[1]_MRXD[2]/
VIN[1]A_D[3]/
UART3_RXD/
GP3[3]		 AD25 I IPD
DVDD		 VOUT[1], EMAC[1], VIN[1]A, GP3
PINCNTL211
DSIS: 1
MM: MUX1		 UART3 Receive Data Input. Functions as IrDA receive input in IrDA modes and CIR receive input in CIR mode.
UART0_DCD/
UART3_RXD/
SPI[0]_SCS[3]/
I2C[2]_SCL/
SD1_POW/
GP1[2]		 AH4 I IPU
DVDD		 UART0, SPI[0], I2C[2], SD1, GP1
PINCNTL74
DSIS: 1
MM: MUX0
VOUT[1]_B_CB_C[7]/
EMAC[1]_MRXD[3]/
VIN[1]A_D[4]/
UART3_TXD/
GP3[4]		 AC25 O IPD
DVDD		 VOUT[1], EMAC[1], VIN[1]A, GP3
PINCNTL212
DSIS: PIN
MM: MUX1		 UART3 Transmit Data Output. Functions as CIR transmit output in CIR mode.
UART0_DSR/
UART3_TXD/
SPI[0]_SCS[2]/
I2C[2]_SDA/
SD1_SDWP/
GP1[3]		 AG4 O IPU
DVDD		 UART0, SPI[0], I2C[2], SD1, GP1
PINCNTL75
DSIS: PIN
MM: MUX0
VOUT[1]_HSYNC/
EMAC[1]_MCOL/
VIN[1]A_VSYNC/
SPI[3]_D[1]/
UART3_RTS/
GP2[29]		 AC24 O IPD
DVDD		 VOUT[1], EMAC[1], VIN[1]A, SPI[3], GP2
PINCNTL205
DSIS: PIN
MM: MUX1		 UART3 Request to Send Output. Indicates module is ready to receive data. Functions as transmit data output in IrDA modes.
UART0_RIN/
UART3_RTS/
UART1_RXD/
GP1[5]		 AF4 O IPU
DVDD		 UART0, UART1, GP1
PINCNTL77
DSIS: PIN
MM: MUX0
VOUT[1]_VSYNC/
EMAC[1]_MCRS/
VIN[1]A_FLD/
VIN[1]A_DE/
SPI[3]_D[0]/
UART3_CTS/
GP2[30] 		AA23 I/O IPD
DVDD		 VOUT[1], EMAC[1], VIN[1]A, SPI[3], GP2
PINCNTL206
DSIS: 1
MM: MUX1		 UART3 Clear to Send Input. Functions as SD transceiver control output in IrDA and CIR modes.
UART0_DTR/
UART3_CTS/
UART1_TXD/
GP1[4]		 AG2 I/O IPU
DVDD		 UART3, UART1, GP1
PINCNTL76
DSIS: 1
MM: MUX0
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS = De-selected Input State
(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the Internal Pull after Reset. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see Section 3.5.1, Pullup/Pulldown Resistors and Section 6.3.17, Pin Behaviors at Reset.
(3) Specifies the operating I/O supply voltage for each signal

Table 2-40 UART4 Terminal Functions

SIGNAL TYPE(1) OTHER(2) (3) MUXED DESCRIPTION
NAME NO.
UART4
UART0_CTS/
UART4_RXD/
DCAN1_TX/
SPI[1]_SCS[3]/
SD0_SDCD		 AE6 I IPU
DVDD		 UART0, DCAN1, SPI[1], SD0
PINCNTL72
DSIS: 1
MM: MUX3		 UART4 Receive Data Input. Functions as IrDA receive input in IrDA modes and CIR receive input in CIR mode.
VOUT[1]_B_CB_C[4]/
EMAC[1]_MRXD[0]/
VIN[1]A_D[1]/
UART4_RXD/
GP3[1]		 AG25 I IPD
DVDD		 VOUT[1], EMAC[1], VIN[1]A, GP3
PINCNTL209
DSIS: 1
MM: MUX2
EMAC[0]_MTXD[1]/
EMAC[1]_RGTXD[1]/
GPMC_A[8]/
UART4_RXD		 H25 I IPD
DVDD_GPMC		 EMAC[0], EMAC[1], GPMC
PINCNTL251
DSIS: 1
MM: MUX1
VOUT[1]_G_Y_YC[1]/
CAM_D[3]/
GPMC_A[5]/
UART4_RXD/
GP0[22]		 AD18 I IPU
DVDD_C		 VOUT[1], CAMERA_I/F, GPMC, GP0
PINCNTL168
DSIS: 1
MM: MUX0
UART0_RTS/
UART4_TXD/
DCAN1_RX/
SPI[1]_SCS[2]/
SD2_SDCD		 AF5 O IPU
DVDD		 UART0, DCAN1, SPI[1], SD2
PINCNTL73
DSIS: PIN
MM: MUX3		 UART4 Transmit Data Output. Functions as CIR transmit output in CIR mode.
VOUT[1]_B_CB_C[5]/
EMAC[1]_MRXD[1]/
VIN[1]A_D[2]/
UART4_TXD/
GP3[2]		 AF25 O IPD
DVDD		 VOUT[1], EMAC[1], VIN[1]A, GP3
PINCNTL210
DSIS: PIN
MM: MUX2
EMAC[0]_MTXD[2]/
EMAC[1]_RGTXCTL/
EMAC[1]_RMRXD[0]/
GPMC_A[9]/
UART4_TXD		 H22 O IPD
DVDD_GPMC		 EMAC[0], EMAC[1], GPMC
PINCNTL252
DSIS: PIN
MM: MUX1
VOUT[1]_G_Y_YC[0]/
CAM_D[2]/
GPMC_A[6]/
UART4_TXD/
GP0[23]		 AC18 O IPD
DVDD_C		 VOUT[1], CAMERA_I/F, GPMC, GP0
PINCNTL169
DSIS: PIN
MM: MUX0
VOUT[1]_AVID/
EMAC[1]_MRXER/
VIN[1]A_CLK/
UART4_RTS/
TIM6_IO/
GP2[31]		 Y22 O IPD
DVDD		 VOUT[1], EMAC[1], VIN[1]A, TIMER6, GP2
PINCNTL207
DSIS: PIN
MM: MUX2		 UART4 Request to Send Output. Indicates module is ready to receive data. Functions as transmit data output in IrDA modes.
EMAC[0]_MTXD[4]/
EMAC[1]_RGTXD[2]/
EMAC[1]_RMRXER/
GPMC_A[11]/
UART4_RTS		 G23 O IPD
DVDD_GPMC		 EMAC[0], EMAC[1], GPMC
PINCNTL254
DSIS: PIN
MM: MUX1
VOUT[1]_R_CR[0]/
CAM_D[0]/
GPMC_A[8]/
UART4_RTS/
GP0[25]		 AA22 O IPD
DVDD_C		 VOUT[1], CAMERA_I/F, GPMC, GP0
PINCNTL171
DSIS: PIN
MM: MUX0
VOUT[1]_B_CB_C[3]/
EMAC[1]_MRCLK/
VIN[1]A_D[0]/
UART4_CTS/
GP3[0]		 AH25 I/O IPD
DVDD		 VOUT[1], EMAC[1], VIN[1]A, GP3
PINCNTL208
DSIS: 1
MM: MUX2		 UART4 Clear to Send Input. Functions as SD transceiver control output in IrDA and CIR modes.
EMAC[0]_MTXD[3]/
EMAC[1]_RGTXD[0]/
EMAC[1]_RMRXD[1]/
GPMC_A[10]/
UART4_CTS		 H23 I/O IPD
DVDD_GPMC		 EMAC[0], EMAC[1], GPMC
PINCNTL253
DSIS: 1
MM: MUX1
VOUT[1]_R_CR[1]/
CAM_D[1]/
GPMC_A[7]/
UART4_CTS/
GP0[24]		 AC19 I/O IPD
DVDD_C		 VOUT[1], CAMERA_I/F, GPMC, GP0
PINCNTL170
DSIS: 1
MM: MUX0
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS = De-selected Input State
(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the Internal Pull after Reset. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see Section 3.5.1, Pullup/Pulldown Resistors and Section 6.3.17, Pin Behaviors at Reset.
(3) Specifies the operating I/O supply voltage for each signal

Table 2-41 UART5 Terminal Functions

SIGNAL TYPE(1) OTHER(2) (3) MUXED DESCRIPTION
NAME NO.
UART5
MCA[2]_AXR[0]/
SD0_DAT[6]/
UART5_RXD/
GP0[12]		 N2 I IPU
DVDD		 MCA[2], SD0, GP0
PINCNTL41
DSIS: 1
MM: MUX3		 UART5 Receive Data Input. Functions as IrDA receive input in IrDA modes and CIR receive input in CIR mode.
VOUT[1]_R_CR[8]/
EMAC[1]_MTXD[7]/
VIN[1]A_D[19]/
UART5_RXD/
GP3[18]		 W23 I IPD
DVDD		 VOUT[1], EMAC[1], VIN[1]A, GP3
PINCNTL226
DSIS: 1
MM: MUX2
VIN[0]A_FLD/
VIN[0]B_VSYNC/
UART5_RXD/
I2C[2]_SCL/
GP2[1]		 AA20 I IPU
DVDD		 VIN[0]A, I2C[2], GP2
PINCNTL136
DSIS: 1
MM: MUX1
EMAC[0]_MRXD[3]/
EMAC[1]_RGRXCTL/
GPMC_A[27]/
GPMC_A[26]/
GPMC_A[0]/
UART5_RXD		 J25 I IPD
DVDD_GPMC		 EMAC[0], EMAC[1], GPMC
PINCNTL243
DSIS: 1
MM: MUX0
MCA[2]_AXR[1]/
SD0_DAT[7]/
UART5_TXD/
GP0[13]		 V6 O IPU
DVDD		 MCA[2], SD0, GP0
PINCNTL42
DSIS: PIN
MM: MUX3		 UART5 Transmit Data Output. Functions as CIR transmit output in CIR mode.
VOUT[1]_R_CR[9]/
EMAC[1]_MTXEN/
VIN[1]A_D[20]/
UART5_TXD/
GP3[19]		 Y24 O IPD
DVDD		 VOUT[1], EMAC[1], VIN[1]A, GP3
PINCNTL227
DSIS: PIN
MM: MUX2
VIN[0]A_DE/
VIN[0]B_HSYNC/
UART5_TXD/
I2C[2]_SDA/
GP2[0]		 AE21 O IPU
DVDD		 VIN[0]A, I2C[2], GP0
PINCNTL135
DSIS: PIN
MM: MUX1
EMAC[0]_MRXD[4]/
EMAC[0]_RGRXD[3]/
GPMC_A[1]/
UART5_TXD		 T23 O IPD
DVDD_GPMC		 EMAC[0], GPMC
PINCNTL244
DSIS: PIN
MM: MUX0
VIN[0]A_HSYNC/
UART5_RTS/
GP2[3]		 AC20 O IPU
DVDD		 VIN[0]A, GP2
PINCNTL138
DSIS: PIN
MM: MUX1		 UART5 Request to Send Output. Indicates module is ready to receive data. Functions as transmit data output in IrDA modes.
EMAC[0]_MRXD[6]/
EMAC[0]_RGTXD[2]/
GPMC_A[3]/
UART5_RTS		 F28 O IPD
DVDD_GPMC		 EMAC[0], GPMC
PINCNTL246
DSIS: PIN
MM: MUX0
VIN[0]A_VSYNC/
UART5_CTS/
GP2[4]		 AD20 I/O IPU
DVDD		 VIN[0]A, GP2
PINCNTL139
DSIS: 1
MM: MUX1		 UART5 Clear to Send Input. Functions as SD transceiver control output in IrDA and CIR modes.
EMAC[0]_MRXD[5]/
EMAC[0]_RGTXD[3]/
GPMC_A[2]/
UART5_CTS		 H26 I/O IPD
DVDD_GPMC		 EMAC[0], GPMC
PINCNTL245
DSIS: 1
MM: MUX0
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS = De-selected Input State
(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the Internal Pull after Reset. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see Section 3.5.1, Pullup/Pulldown Resistors and Section 6.3.17, Pin Behaviors at Reset.
(3) Specifies the operating I/O supply voltage for each signal

2.11.21 USB

Table 2-42 USB Terminal Functions

SIGNAL TYPE(1) OTHER(2) (3) MUXED DESCRIPTION
NAME NO.
USB0
USB0_DP AG11 A I/O –
VDDA_USB_3P3		 – USB0 bidirectional data differential signal pair [plus/minus].

When the USB0 PHY is powered down, these pins should be left unconnected.
USB0_DM AH11 A I/O –
VDDA_USB_3P3		 –
USB0_ID AG10 A I –
VDDA_USB_3P3		 – USB0 OTG identification input.

When the USB0 PHY is powered down, this pin should be left unconnected.
USB0_CE AH10 A O –
VDDA_USB_3P3		 – USB0 charger enable.

When the USB0 PHY is powered down, this pin should be left unconnected.
USB0_VBUSIN AG12 A I –
VDDA_USB_3P3		 – 5-V USB0 VBUS comparator input.

This analog input pin senses the level of the USB VBUS voltage and should connect directly to the USB VBUS voltage. When the USB0 PHY is powered down, this pin should be left unconnected.
USB0_DRVVBUS/
GP0[7]		 AF11 O IPD
DVDD		 GP0
PINCNTL270
DSIS: N/A		 When this pin is used as USB0_DRVVBUS and the USB0 Controller is operating as a Host, this signal is used by the USB0 Controller to enable the external VBUS charge pump.

When the USB0 PHY is powered down, this pin should be left unconnected.
USB1
USB1_DP AG13 A I/O –
VDDA_USB_3P3		 – USB1 bidirectional data differential signal pair [plus/minus].

When the USB1 PHY is powered down, these pins should be left unconnected.
USB1_DM AH13 A I/O –
VDDA_USB_3P3		 –
USB1_ID AH12 A I –
VDDA_USB_3P3		 – USB1 OTG identification input.

When the USB1 PHY is powered down, this pin should be left unconnected.
USB1_CE AH14 A O –
VDDA_USB_3P3		 – USB1 charger enable.

When the USB1 PHY is powered down, this pin should be left unconnected.
USB1_VBUSIN AG14 A I –
VDDA_USB_3P3		 – 5-V USB1 VBUS comparator input.

This analog input pin senses the level of the USB VBUS voltage and should connect directly to the USB VBUS voltage. When the USB1 PHY is powered down, this pin should be left unconnected.
AUD_CLKIN0/
MCA[0]_AXR[7]/
MCA[0]_AHCLKX/
MCA[3]_AHCLKX/
USB1_DRVVBUS		 L5 O IPD
DVDD		 AUD_CLKIN0, MCA[0], MCA[3],
PINCNTL14
DSIS: N/A		 When this pin is used as USB1_DRVVBUS and the USB1 Controller is operating as a Host, this signal is used by the USB1 Controller to enable the external VBUS charge pump.

When the USB1 PHY is powered down, this pin should be left unconnected.
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS = De-selected Input State
(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the Internal Pull after Reset. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see Section 3.5.1, Pullup/Pulldown Resistors and Section 6.3.17, Pin Behaviors at Reset.
(3) Specifies the operating I/O supply voltage for each signal

2.11.22 Video Input (Digital)

Table 2-43 Video Input 0 (Digital) Terminal Functions

SIGNAL TYPE(1) OTHER(2) (3) MUXED DESCRIPTION
NAME NO.
Video Input 0 (Digital)
VIN[0]B_CLK/
CLKOUT0/
GP1[9]		 AE17 I IPD
DVDD		 CLKOUT0, GP1
PINCNTL134
DSIS: 0		 Video Input 0 Port B Clock input. Input clock for 8-bit Port B video capture. This signal is not used in 16-bit and 24-bit capture modes.
VIN[0]A_CLK/
GP2[2]		 AB20 I IPD
DVDD		 GP2
PINCNTL137
DSIS: 0		 Video Input 0 Port A Clock input. Input clock for 8-bit , 16-bit, or 24-bit Port A video capture.
VIN[0]A_D[23]/
CAM_D[15]/
EMAC[1]_RMTXEN/
SPI[3]_D[0]/
GP0[17] 		AC16 I IPD
DVDD_C		 CAM_IF, EMAC[1]_RM, SPI[3], GP0
PINCNTL163
DSIS: PIN		 Video Input 0 Data inputs. For 16-bit capture, D[7:0] are Cb/Cr and [15:8] are Y Port A inputs. For 8-bit capture, D[7:0] are Port A YCbCr data inputs and D[15:8] are Port B YCbCr data inputs. For RGB capture, D[23:16] are R, D[15:8] are G, and D[7:0] are B data inputs.
VIN[0]A_D[22]/
CAM_D[14]/
EMAC[1]_RMTXD[1]/
SPI[3]_D[1]/
GP0[16] 		AC21 I IPD
DVDD_C		 CAM_IF, EMAC[1]_RM, SPI[3], GP0
PINCNTL162
DSIS: PIN
VIN[0]A_D[21]/
CAM_D[13]/
EMAC[1]_RMTXD[0]/
SPI[3]_SCLK/
GP0[15] 		AE18 I IPD
DVDD_C		 CAM_IF, EMAC[1]_RM, SPI[3], GP0
PINCNTL161
DSIS: PIN
VIN[0]A_D[20]/
CAM_D[12]/
EMAC[1]_RMCRSDV/
SPI[3]_SCS[0]/
GP0[14]		 AC17 I IPD
DVDD_C		 CAM_IF, EMAC[1]_RM, SPI[3], GP0
PINCNTL160
DSIS: PIN
VIN[0]A_D[19]/
CAM_D[11]/
EMAC[1]_RMRXD[0]/
I2C[3]_SDA/
GP0[13] 		AF21 I IPU
DVDD_C		 CAM_IF, EMAC[1]_RM, I2C[3], GP0
PINCNTL159
DSIS: PIN
VIN[0]A_D[18]/
CAM_D[10]/
EMAC[1]_RMRXD[1]/
I2C[3]_SCL/
GP0[12] 		AF20 I IPU
DVDD_C		 CAM_IF, EMAC[1]_RM, I2C[3], GP0
PINCNTL158
DSIS: PIN
VIN[0]A_D[17]/
CAM_D[9]/
EMAC[1]_RMRXER/
GP0[11] 		AB21 I IPD
DVDD_C		 CAM_IF, EMAC[1]_RM, I2C[3], GP0
PINCNTL157
DSIS: PIN
VIN[0]A_D[16]/
CAM_D[8]/
I2C[2]_SCL/
GP0[10] 		AA21 I IPU
DVDD_C		 CAM_IF, I2C[3], GP0
PINCNTL156
DSIS: PIN
VIN[0]A_D[15]_BD[7]/
CAM_SHUTTER/
GP2[20] 		AC14 I IPD
DVDD		 CAM_IF, GP2
PINCNTL155
DSIS: PIN		 Video Input 0 Data inputs. For 16-bit capture, D[7:0] are Cb/Cr and [15:8] are Y Port A inputs. For 8-bit capture, D[7:0] are Port A YCbCr data inputs and D[15:8] are Port B YCbCr data inputs. For RGB capture, D[23:16] are R, D[15:8] are G, and D[7:0] are B data inputs.
VIN[0]A_D[14]_BD[6]/
CAM_STROBE/
GP2[19] 		AC12 I IPD
DVDD		 CAM_IF, GP2
PINCNTL154
DSIS: PIN
VIN[0]A_D[13]_BD[5]/
CAM_RESET/
GP2[18] 		AF17 I IPD
DVDD		 CAM_IF, GP2
PINCNTL153
DSIS: PIN
VIN[0]A_D[12]_BD[4]/
CLKOUT1/
GP2[17] 		AG17 I IPD
DVDD		 CLKOUT1, GP2
PINCNTL152
DSIS: PIN
VIN[0]A_D[11]_BD[3]/
CAM_WE/
GP2[16] 		AH17 I IPD
DVDD		 CAM_IF, GP2
PINCNTL151
DSIS: PIN
VIN[0]A_D[10]_BD[2]/
GP2[15] 		AH9 I IPD
DVDD		 GP2
PINCNTL150
DSIS: PIN
VIN[0]A_D[9]_BD[1]/
GP2[14] 		AG9 I IPD
DVDD		 GP2
PINCNTL149
DSIS: PIN
VIN[0]A_D[8]_BD[0]/
GP2[13] 		AB15 I IPD
DVDD		 GP2
PINCNTL148
DSIS: PIN
VIN[0]A_D[7]/
GP2[12] 		AA11 I IPD
DVDD		 GP2
PINCNTL147
DSIS: PIN		 Video Input 0 Data inputs. For 16-bit capture, D[7:0] are Cb/Cr and [15:8] are Y Port A inputs. For 8-bit capture, D[7:0] are Port A YCbCr data inputs and D[15:8] are Port B YCbCr data inputs. For RGB capture, D[23:16] are R, D[15:8] are G, and D[7:0] are B data inputs.
VIN[0]A_D[6]/
GP2[11] 		AH16 I IPD
DVDD		 GP2
PINCNTL146
DSIS: PIN
VIN[0]A_D[5]/
GP2[10] 		AG16 I IPD
DVDD		 GP2
PINCNTL145
DSIS: PIN
VIN[0]A_D[4]/
GP2[9] 		AH8 I IPD
DVDD		 GP2
PINCNTL144
DSIS: PIN
VIN[0]A_D[3]/
GP2[8] 		AE12 I IPD
DVDD		 GP2
PINCNTL143
DSIS: PIN
VIN[0]A_D[2]/
GP2[7] 		AC9 I IPD
DVDD		 GP2
PINCNTL142
DSIS: PIN
VIN[0]A_D[1]/
GP1[12] 		AB11 I IPD
DVDD		 GP1
PINCNTL141
DSIS: PIN
VIN[0]A_D[0]/
GP1[11] 		AF9 I IPD
DVDD		 GP1
PINCNTL140
DSIS: PIN
VIN[0]A_DE/
VIN[0]B_HSYNC/
UART5_TXD/
I2C[2]_SDA/
GP2[0] 		AE21 I IPU
DVDD		 VIN[0]A, UART5, I2C[2], GP2
PINCNTL135
DSIS: 0		 Video Input 0 Port B Horizontal Sync input. Discrete horizontal synchronization signal for Port B 8-bit YCbCr capture without embedded syncs (“BT.601” modes). Not used in RGB or 16-bit YCbCr capture modes
VIN[0]A_HSYNC/
UART5_RTS/
GP2[3] 		AC20 I IPU
DVDD		 UART5, GP2
PINCNTL138
DSIS: 0		 Video Input 0 Port A Horizontal Sync0 input. Discrete horizontal synchronization signal for Port A RGB capture mode or YCbCr capture without embedded syncs (“BT.601” modes).
VIN[0]A_FLD/
VIN[0]B_VSYNC/
UART5_RXD/
I2C[2]_SCL/
GP2[1] 		AA20 I IPU
DVDD		 VIN[0]A, UART5, I2C[2], GP2
PINCNTL136
DSIS:0		 Video Input 0 Port B Vertical Sync1 input. Discrete vertical synchronization signal for Port B 8-bit YCbCr capture without embedded syncs (“BT.601” modes). Not used in RGB or 16-bit YCbCr capture modes.
VIN[0]A_VSYNC/
UART5_CTS/
GP2[4] 		AD20 I IPU
DVDD		 UART5, GP2
PINCNTL139
DSIS: 0		 Video Input 0 Port A Vertical Sync0 input. Discrete vertical synchronization signal for Port A RGB capture mode or YCbCr capture without embedded syncs (“BT.601” modes).
VIN[0]B_FLD/
CAM_D[4]/
GP0[21]		 AD17 I IPU
DVDD_C		 CAMERA_I/F, GP0
PINCNTL167
DSIS: 0		 Video Input 0 Port B Field ID input. Discrete field identification signal for Port B 8-bit YCbCr capture without embedded syncs (“BT.601” modes). Not used in RGB or 16-bit YCbCr capture modes.
VIN[0]A_FLD/
CAM_D[5]/
GP0[20]		 AC22 I IPU
DVDD_C		 CAMERA_I/F, GP0
PINCNTL166
DSIS: 0
MM: MUX1		 Video Input 0 Port A Field ID input. Discrete field identification signal for Port A RGB capture mode or YCbCr capture without embedded syncs (“BT.601” modes).
VIN[0]A_FLD/
VIN[0]B_VSYNC/
UART5_RXD/
I2C[2]_SCL/
GP2[1]		 AA20 I IPU
DVDD		 VIN[0]B, UART5, I2C[2], GP2
PINCNTL136
DSIS: 0
MM: MUX0

VIN[0]B_DE/
CAM_D[6]/
GP0[19]		 AC15 I IPU
DVDD_C		 CAMERA_I/F, GP0
PINCNTL165
DSIS: 0		 Video Input 0 Port B Data Enable input. Discrete data valid signal for Port B RGB capture mode or YCbCr capture without embedded syncs (“BT.601” modes).
VIN[0]A_DE/
CAM_D[7]/
GP0[18] 		AB17 I IPU
DVDD_C		 CAMERA_I/F, GP0
PINCNTL164
DSIS: 0
MM: MUX1		 Video Input 0 Port A Data Enable input. Discrete data valid signal for Port A RGB capture mode or YCbCr capture without embedded syncs ("BT.601" modes).
VIN[0]A_DE/
VIN[0]B_HSYNC/
UART5_TXD/
I2C[2]_SDA/
GP2[0]		 AE21 I IPU
DVDD		 VIN[0]B, UART5, I2C[2], GP2
PINCNTL135
DSIS: 0
MM: MUX0
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS = De-selected Input State
(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the Internal Pull after Reset. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see Section 3.5.1, Pullup/Pulldown Resistors and Section 6.3.17, Pin Behaviors at Reset.
(3) Specifies the operating I/O supply voltage for each signal.

Table 2-44 Video Input 1 (Digital) Terminal Functions

SIGNAL TYPE(1) OTHER(2) (3) MUXED DESCRIPTION
NAME NO.
Video Input 1 (Digital)
GPMC_CS[3]/
VIN[1]B_CLK/
SPI[2]_SCS[0]/
GP1[26]		 P26 I IPU
DVDD_GPMC		 GPMC, SPI[2], GP1
PINCNTL125
DSIS: 0		 Video Input 1 Port B Clock input. Input clock for 8-bit Port B video capture. Input data is sampled on the CLK1 edge. This signal is not used in 16-bit and 24-bit capture modes.
VOUT[1]_AVID/
EMAC[1]_MRXER/
VIN[1]A_CLK/
UART4_RTS/
TIM6_IO/
GP2[31]		 Y22 I IPD
DVDD		 VOUT[1], EMAC[1], UART4, TIMER 6, GP2
PINCNTL207
DSIS: 0		 Video Input 1 Port A Clock input. Input clock for 8-bit , 16-bit, or 24-bit Port A video capture. Input data is sampled on the CLK0 edge.
VOUT[1]_R_CR[2]/
GPMC_A[15]/
VIN[1]A_D[23]/
HDMI_HPDET/
SPI[2]_D[1]/
GP3[22]		 AE27 I IPD
DVDD		 VOUT[1], GPMC, HDMI, SPI[2], GP3
PINCNTL230
DSIS: PIN		 Video Input 1 Data inputs. For 16-bit capture, D[7:0] are Cb/Cr and [15:8] are Y Port A inputs. For 8-bit capture, D[7:0] are Port A YCbCr data inputs. For RGB capture, D[23:16] are R, D[15:8] are G, and D[7:0] are B Port A data inputs.
VOUT[1]_R_CR[3]/
GPMC_A[14]/
VIN[1]A_D[22]/
HDMI_SDA/
SPI[2]_SCLK/
I2C[2]_SDA/
GP3[21]		 AG28 I IPU
DVDD		 VOUT[1], GPMC, HDMI, SPI[2], I2C[2], GP3
PINCNTL229
DSIS: PIN
VOUT[1]_G_Y_YC[2]/
GPMC_A[13]/
VIN[1]A_D[21]/
HDMI_SCL/
SPI[2]_SCS[2]/
I2C[2]_SCL/
GP3[20]		 AF27 I IPU
DVDD		 VOUT[1], GPMC, HDMI, SPI[2], I2C[2], GP3
PINCNTL228
DSIS: PIN
VOUT[1]_R_CR[9]/
EMAC[1]_MTXEN/
VIN[1]A_D[20]/
UART5_TXD/
GP3[19]		 Y24 I IPD
DVDD		 VOUT[1], EMAC[1], UART5, GP3
PINCNTL227
DSIS: PIN
VOUT[1]_R_CR[8]/
EMAC[1]_MTXD[7]/
VIN[1]A_D[19]/
UART5_RXD/
GP3[18] 		W23 I IPD
DVDD		 VOUT[1], EMAC[1], UART5, GP3
PINCNTL226
DSIS: PIN		 Video Input 1 Data inputs. For 16-bit capture, D[7:0] are Cb/Cr and [15:8] are Y Port A inputs. For 8-bit capture, D[7:0] are Port A YCbCr data inputs. For RGB capture, D[23:16] are R, D[15:8] are G, and D[7:0] are B Port A data inputs.
VOUT[1]_R_CR[7]/
EMAC[1]_MTXD[6]/
VIN[1]A_D[18]/
SPI[3]_D[0]/
GP3[17]		 V22 I IPD
DVDD		 VOUT[1], EMAC[1], SPI[3], GP3
PINCNTL225
DSIS: PIN
VOUT[1]_R_CR[6]/
EMAC[1]_MTXD[5]/
VIN[1]A_D[17]/
SPI[3]_D[1]/
GP3[16]		 AA25 I IPD
DVDD		 VOUT[1], EMAC[1], SPI[3], GP3
PINCNTL224
DSIS: PIN
VOUT[1]_R_CR[5]/
EMAC[1]_MTXD[4]/
VIN[1]A_D[16]/
SPI[3]_SCLK/
GP3[15]		 AC26 I IPD
DVDD		 VOUT[1], EMAC[1], SPI[3], GP3
PINCNTL223
DSIS: PIN
VOUT[1]_R_CR[4]/
EMAC[1]_MTXD[3]/
VIN[1]A_D[15]/
SPI[3]_SCS[1]/
GP3[14]		 AG27 I IPD
DVDD		 VOUT[1], EMAC[1], SPI[3], GP3
PINCNTL222
DSIS: PIN		 Video Input 1 Data inputs. For 16-bit capture, D[7:0] are Cb/Cr and [15:8] are Y Port A inputs. For 8-bit capture, D[7:0] are Port A YCbCr data inputs. For RGB capture, D[23:16] are R, D[15:8] are G, and D[7:0] are B Port A data inputs.
VOUT[1]_G_Y_YC[9]/
EMAC[1]_MTXD[2]/
VIN[1]A_D[14]/
GP3[13]		 AD26 I IPD
DVDD		 VOUT[1], EMAC[1], GP3
PINCNTL221
DSIS: PIN
VOUT[1]_G_Y_YC[8]/
EMAC[1]_MTXD[1]/
VIN[1]A_D[13]/
GP3[12] 		AE26 I IPD
DVDD		 VOUT[1], EMAC[1], GP3
PINCNTL220
DSIS: PIN
VOUT[1]_G_Y_YC[7]/
EMAC[1]_MTXD[0]/
VIN[1]A_D[12]/
GP3[11] 		AF26 I IPD
DVDD		 VOUT[1], EMAC[1], GP3
PINCNTL219
DSIS: PIN
VOUT[1]_G_Y_YC[6]/
EMAC[1]_GMTCLK/
VIN[1]A_D[11]/
GP3[10]		 AH27 I IPD
DVDD		 VOUT[1], EMAC[1], GP3
PINCNTL218
DSIS: PIN
VOUT[1]_G_Y_YC[5]/
EMAC[1]_MRXDV/
VIN[1]A_D[10]/
GP3[9] 		AG26 I IPD
DVDD		 VOUT[1], EMAC[1], GP3
PINCNTL217
DSIS: PIN
VOUT[1]_G_Y_YC[4]/
EMAC[1]_MRXD[7]/
VIN[1]A_D[9]/
GP3[8] 		W22 I IPD
DVDD		 VOUT[1], EMAC[1], GP3
PINCNTL216
DSIS: PIN
VOUT[1]_G_Y_YC[3]/
EMAC[1]_MRXD[6]/
VIN[1]A_D[8]/
GP3[7]		 Y23 I IPD
DVDD		 VOUT[1], EMAC[1], GP3
PINCNTL215
DSIS: PIN
VOUT[1]_B_CB_C[2]/
GPMC_A[0]/
VIN[1]A_D[7]/
HDMI_CEC/
SPI[2]_D[0]/
GP3[30] 		AF28 I IPU
DVDD		 VOUT[1], GPMC, HDMI, SPI[2], GP3
PINCNTL231
DSIS: PIN		 Video Input 1 Data inputs. For 16-bit capture, D[7:0] are Cb/Cr and [15:8] are Y Port A inputs. For 8-bit capture, D[7:0] are Port A YCbCr data inputs. For RGB capture, D[23:16] are R, D[15:8] are G, and D[7:0] are B Port A data inputs.
VOUT[1]_B_CB_C[9]/
EMAC[1]_MRXD[5]/
VIN[1]A_D[6]/
I2C[3]_SDA/
GP3[6]		 AA24 I IPD
DVDD		 VOUT[1], EMAC[1], I2C[3], GP3
PINCNTL214
DSIS: PIN
VOUT[1]_B_CB_C[8]/
EMAC[1]_MRXD[4]/
VIN[1]A_D[5]/
I2C[3]_SCL/
GP3[5] 		AH26 I IPD
DVDD		 VOUT[1], EMAC[1], I2C[3], GP3
PINCNTL213
DSIS: PIN
VOUT[1]_B_CB_C[7]/
EMAC[1]_MRXD[3]/
VIN[1]A_D[4]/
UART3_TXD/
GP3[4] 		AC25 I IPD
DVDD		 VOUT[1], EMAC[1], UART3, GP3
PINCNTL212
DSIS: PIN
VOUT[1]_B_CB_C[6]/
EMAC[1]_MRXD[2]/
VIN[1]A_D[3]/
UART3_RXD/
GP3[3] 		AD25 I IPD
DVDD		 VOUT[1], EMAC[1], UART3, GP3
PINCNTL211
DSIS: PIN
VOUT[1]_B_CB_C[5]/
EMAC[1]_MRXD[1]/
VIN[1]A_D[2]/
UART4_TXD/
GP3[2] 		AF25 I IPD
DVDD		 VOUT[1], EMAC[1], UART4, GP3
PINCNTL210
DSIS: PIN
VOUT[1]_B_CB_C[4]/
EMAC[1]_MRXD[0]/
VIN[1]A_D[1]/
UART4_RXD/
GP3[1] 		AG25 I IPD
DVDD		 VOUT[1], EMAC[1], UART4, GP3
PINCNTL209
DSIS: PIN
VOUT[1]_B_CB_C[3]/
EMAC[1]_MRCLK/
VIN[1]A_D[0]/
UART4_CTS/
GP3[0] 		AH25 I IPD
DVDD		 VOUT[1], EMAC[1], UART4, GP3
PINCNTL208
DSIS: PIN
EMAC[0]_MRXD[2]/
EMAC[0]_RGRXD[1]/
VIN[1]B_D[7]/
EMAC[0]_RMTXEN/
GP3[30]		 R23 I IPD
DVDD_GPMC		 EMAC[0], GP3
PINCNTL242
DSIS: PIN		 Video Input 1 Port B Data inputs. For 8-bit capture, B_D[7:0] are Port B YCbCr data inputs.
EMAC[0]_MRXD[1]/
EMAC[0]_RGRXD[0]/
VIN[1]B_D[6]/
EMAC[0]_RMTXD[1]/
GP3[29]		 P23 I IPD
DVDD_GPMC		 EMAC[0], GP3
PINCNTL241
DSIS: PIN
EMAC[0]_MRXD[0]/
EMAC[0]_RGTXD[0]/
VIN[1]B_D[5]/
EMAC[0]_RMTXD[0]/
GP3[28]		 G28 I IPD
DVDD_GPMC		 EMAC[0], GP3
PINCNTL240
DSIS: PIN
EMAC[0]_MRCLK/
EMAC[0]_RGTXC/
VIN[1]B_D[4]/
EMAC[0]_RMCRSDV/
SPI[3]_SCS[2]/
GP3[27]		 H27 I IPD
DVDD_GPMC		 EMAC[0], SPI[3], GP3
PINCNTL239
DSIS: PIN
EMAC[0]_MRXER/
EMAC[0]_RGTXCTL/
VIN[1]B_D[3]/
EMAC[0]_RMRXER/
GP3[26]		 J26 I IPD
DVDD_GPMC		 EMAC[0], GP3
PINCNTL238
DSIS: PIN		 Video Input Port B Data inputs. For 8-bit capture, B_D[7:0] are Port B YCbCr data inputs.
EMAC[0]_MCRS/
EMAC[0]_RGRXD[2]/
VIN[1]B_D[2]/
EMAC[0]_RMRXD[1]/
GP3[25]		 R25 I IPD
DVDD_GPMC		 EMAC[0], GP3
PINCNTL237
DSIS: PIN
EMAC[0]_MCOL/
EMAC[0]_RGRXCTL/
VIN[1]B_D[1]/
EMAC[0]_RMRXD[0]/
GP3[24]		 L23 I IPD
DVDD_GPMC		 EMAC[0], GP3
PINCNTL236
DSIS: PIN
EMAC[0]_MTCLK/
EMAC[0]_RGRXC/
VIN[1]B_D[0]/
SPI[3]_SCS[3]/
I2C[2]_SDA/
GP3[23]		 L24 I IPD
DVDD_GPMC		 EMAC[0], SPI[3], I2C[2], GP3
PINCNTL235
DSIS: PIN
VOUT[1]_CLK/
EMAC[1]_MTCLK/
VIN[1]A_HSYNC/
GP2[28]		 AE24 I IPD
DVDD		 VOUT[1], EMAC[1], GP2
PINCNTL204
DSIS: 0		 Video Input 1 Port A Horizontal Sync input. Discrete horizontal synchronization signal forPort A YCbCr capture modes without embedded syncs (“BT.601” modes).
VOUT[1]_HSYNC/
EMAC[1]_MCOL/
VIN[1]A_VSYNC/
SPI[3]_D[1]/
UART3_RTS/
GP2[29]		 AC24 I IPD
DVDD		 VOUT[1], EMAC[1], SPI[3], UART3, GP2
PINCNTL205
DSIS: 0		 Video Input 1 Port A Vertical Sync input. Discrete vertical synchronization signal for Port A YCbCr capture modes without embedded syncs (“BT.601” modes).
VOUT[1]_VSYNC/
EMAC[1]_MCRS/
VIN[1]A_FLD/
VIN[1]A_DE/
SPI[3]_D[0]/
UART3_CTS/
GP2[30] 		AA23 I IPD
DVDD		 VOUT[1], EMAC[1], VIN[1]A, SPI[3], UART3, GP2
PINCNTL206
DSIS: 0		 Video Input 1 Port A Data Enable input. Discrete data valid signal for Port A YCbCr capture modes without embedded syncs (“BT.601” modes).
VOUT[1]_VSYNC/
EMAC[1]_MCRS/
VIN[1]A_FLD/
VIN[1]A_DE/
SPI[3]_D[0]/
UART3_CTS/
GP2[30] 		AA23 I IPD
DVDD		 VOUT[1], EMAC[1], VIN[1]A, SPI[3], UART3, GP2
PINCNTL206
DSIS: 0		 Video Input 1 Port A Field ID input. Discrete field identification signal for Port A YCbCr capture modes without embedded syncs (“BT.601” modes).
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS = De-selected Input State
(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the Internal Pull after Reset. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see Section 3.5.1, Pullup/Pulldown Resistors and Section 6.3.17, Pin Behaviors at Reset.
(3) Specifies the operating I/O supply voltage for each signal

2.11.23 Video Output (Digital)

Table 2-45 Video Output 0 (Digital) Terminal Functions

SIGNAL TYPE(1) OTHER(2) (3) MUXED DESCRIPTION
NAME NO.
Video Output 0
VOUT[0]_CLK AD12 O IPD
DVDD		 –
PINCNTL176		 Video Output Clock output.
VOUT[0]_G_Y_YC[9] AF14 O IPD
DVDD		 –
PINCNTL195		 Video Output Data. These signals represent the 8 MSBs of G/Y/YC video data. For RGB mode they are green data bits, for YUV444 mode they are Y data bits, for Y/C mode they are Y (Luma) data bits and for BT.656 mode they are multiplexed Y/Cb/Cr (Luma and Chroma) data bits.
VOUT[0]_G_Y_YC[8] AE14 O IPD
DVDD		 –
PINCNTL194
VOUT[0]_G_Y_YC[7] AD14 O IPD
DVDD		 –
PINCNTL193
VOUT[0]_G_Y_YC[6] AA8 O IPD
DVDD		 –
PINCNTL192
VOUT[0]_G_Y_YC[5] AB12 O IPD
DVDD		 –
PINCNTL191
VOUT[0]_G_Y_YC[4] AB8 O IPD
DVDD		 –
PINCNTL190
VOUT[0]_G_Y_YC[3]/
GP2[25]		 AH15 O IPD
DVDD		 GP2
PINCNTL189
DSIS: PIN
VOUT[0]_G_Y_YC[2]/
EMU3/
GP2[24]		 AH7 O IPD
DVDD		 EMU, GP2
PINCNTL188
DSIS: PIN
VOUT[0]_B_CB_C[9] AG15 O IPD
DVDD		 –
PINCNTL187		 Video Output Data. These signals represent the 8 MSBs of B/CB/C video data. For RGB mode they are blue data bits, for YUV444 mode they are Cb (Chroma) data bits, for Y/C mode they are multiplexed Cb/Cr (Chroma) data bits and for BT.656 mode they are unused.
VOUT[0]_B_CB_C[8] AF15 O IPD
DVDD		 –
PINCNTL186
VOUT[0]_B_CB_C[7] AB10 O IPD
DVDD		 –
PINCNTL185
VOUT[0]_B_CB_C[6] AC10 O IPD
DVDD		 –
PINCNTL184
VOUT[0]_B_CB_C[5] AD15 O IPD
DVDD		 –
PINCNTL183
VOUT[0]_B_CB_C[4] AD11 O IPD
DVDD		 –
PINCNTL182
VOUT[0]_B_CB_C[3]/
GP2[23]		 AE15 O IPD
DVDD		 GP2
PINCNTL181
DSIS: PIN
VOUT[0]_B_CB_C[2]/
EMU2/
GP2[22]		 AG7 O IPD
DVDD		 EMU2, GP2
PINCNTL180
DSIS: PIN
VOUT[0]_R_CR[9]/ AC13 O IPD
DVDD		 –
PINCNTL203		 Video Output Data. These signals represent the 8 MSBs of R/CR video data. For RGB mode they are red data bits, for YUV444 mode they are Cr (Chroma) data bits, for Y/C mode and BT.656 modes they are unused.
VOUT[0]_R_CR[8]/ AE8 O IPD
DVDD		 –
PINCNTL202
VOUT[0]_R_CR[7]/ AF12 O IPD
DVDD		 –
PINCNTL201
VOUT[0]_R_CR[6]/ AF6 O IPD
DVDD		 –
PINCNTL200
VOUT[0]_R_CR[5]/ AF8 O IPD
DVDD		 –
PINCNTL199
VOUT[0]_R_CR[4]/ AA9 O IPD
DVDD		 –
PINCNTL198
VOUT[0]_R_CR[3]/
GP2[27]		 AB9 O IPD
DVDD		 GP2
PINCNTL197
DSIS: PIN
VOUT[0]_R_CR[2]/
EMU4/
GP2[26]		 AD9 O IPD
DVDD		 EMU4, GP2
PINCNTL196
DSIS: PIN
VOUT[0]_VSYNC AB13 O IPD
DVDD		 –
PINCNTL178		 Video Output Vertical Sync output. This is the discrete vertical synchronization output. This signal is not used for embedded sync modes.
VOUT[0]_HSYNC AC11 O IPD
DVDD		 –
PINCNTL177		 Video Output Horizontal Sync output. This is the discrete horizontal synchronization output. This signal is not used for embedded sync modes.
VOUT[0]_FLD/
CAM_PCLK/
GPMC_A[12]/
UART2_RTS/
GP2[2]		 AF18 O IPD
DVDD_C		 CAMERA_I/F, GPMC, UART2, GP2
PINCNTL175
DSIS: N/A
MM: MUX1		 Video Output Field ID output. This is the discrete field identification output. This signal is not used for embedded sync modes.
VOUT[0]_AVID/
VOUT[0]_FLD/
SPI[3]_SCLK/
TIM7_IO/
GP2[21]		 AA10 O IPD
DVDD		 VOUT[0], SPI[3], TIMER7, GP2
PINCNTL179
DSIS: N/A
MM: MUX0
VOUT[0]_AVID/
VOUT[0]_FLD/
SPI[3]_SCLK/
TIM7_IO/
GP2[21]		 AA10 O IPD
DVDD		 VOUT[0], SPI[3], TIMER7, GP2
PINCNTL179
DSIS: N/A		 Video Output Active Video output. This is the discrete active video indicator output. This signal is not used for embedded sync modes.
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS = De-selected Input State
(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the Internal Pull after Reset. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see Section 3.5.1, Pullup/Pulldown Resistors and Section 6.3.17, Pin Behaviors at Reset.
(3) Specifies the operating I/O supply voltage for each signal

Table 2-46 Video Output 1 Terminal Functions

SIGNAL TYPE(1) OTHER(2) (3) MUXED DESCRIPTION
NAME NO.
Video Output 1
VOUT[1]_CLK/
EMAC[1]_MTCLK/
VIN[1]A_HSYNC/
GP2[28] 		AE24 O IPD
DVDD		 EMAC[1], VIN[1]A, GP2
PINCNTL204
DSIS: N/A		 Video Output Clock output
VOUT[1]_G_Y_YC[9]/
EMAC[1]_MTXD[2]/
VIN[1]A_D[14]/
GP3[13]		 AD26 O IPD
DVDD		 EMAC[1], VIN[1]A, GP3
PINCNTL221
DSIS: N/A		 Video Output Data. These signals represent the 8 MSBs of G/Y/YC video data. For RGB mode they are green data bits, for YUV444 mode they are Y data bits, for Y/C mode they are Y (Luma) data bits and for BT.656 mode they are multiplexed Y/Cb/Cr (Luma and Chroma) data bits.
VOUT[1]_G_Y_YC[8]/
EMAC[1]_MTXD[1]/
VIN[1]A_D[13]/
GP3[12] 		AE26 O IPD
DVDD		 EMAC[1], VIN[1]A, GP3
PINCNTL220
DSIS: N/A
VOUT[1]_G_Y_YC[7]/
EMAC[1]_MTXD[0]/
VIN[1]A_D[12]/
GP3[11] 		AF26 O IPD
DVDD		 EMAC[1], VIN[1]A, GP3
PINCNTL219
DSIS: N/A
VOUT[1]_G_Y_YC[6]/
EMAC[1]_GMTCLK/
VIN[1]A_D[11]/
GP3[10] 		AH27 O IPD
DVDD		 EMAC[1], VIN[1]A, GP3
PINCNTL218
DSIS: N/A
VOUT[1]_G_Y_YC[5]/
EMAC[1]_MRXDV/
VIN[1]A_D[10]/
GP3[9] 		AG26 O IPD
DVDD		 EMAC[1], VIN[1]A, GP3
PINCNTL217
DSIS: N/A		 Video Output Data. These signals represent the 8 MSBs of G/Y/YC video data. For RGB mode they are green data bits, for YUV444 mode they are Y data bits, for Y/C mode they are Y (Luma) data bits and for BT.656 mode they are multiplexed Y/Cb/Cr (Luma and Chroma) data bits.
VOUT[1]_G_Y_YC[4]/
EMAC[1]_MRXD[7]/
VIN[1]A_D[9]/
GP3[8] 		W22 O IPD
DVDD		 EMAC[1], VIN[1]A, GP3
PINCNTL216
DSIS: N/A
VOUT[1]_G_Y_YC[3]
EMAC[1]_MRXD[6]/
VIN[1]A_D[8]/
GP3[7] 		Y23 O IPD
DVDD		 EMAC[1], VIN[1]A, GP3
PINCNTL215
DSIS: N/A
VOUT[1]_G_Y_YC[2]/
GPMC_A[13]/
VIN[1]A_D[21]/
HDMI_SCL/
SPI[2]_SCS[2]/
I2C[2]_SCL/
GP3[20] 		AF27 O IPU
DVDD		 GPMC, VIN[1]A, HDMI, SPI[2], I2C[2], GP3
PINCNTL228
DSIS: N/A
VOUT[1]_G_Y_YC[1]/
CAM_D[3]/
GPMC_A[5]/
UART4_RXD/
GP0[22] 		AD18 O IPU
DVDD_C		 CAMERA_I/F, GPMC, UART4, GP0
PINCNTL168
DSIS: N/A		 Video Output Data. These signals represent the 2 LSBs of G/Y/YC video data for 10-bit, 20-bit, and 30-bit video modes (VOUT[1] only). For RGB mode they are green data bits, for YUV444 mode they are Y data bits, for Y/C mode they are Y (Luma) data bits and for BT-656 mode they are multiplexed Y/Cb/Cr (Luma and Chroma) data bits. These signals are not used in 8/16/24-bit modes.
VOUT[1]_G_Y_YC[0]/
CAM_D[2]/
GPMC_A[6]/
UART4_TXD/
GP0[23] 		AC18 O IPD
DVDD_C		 CAMERA_I/F, GPMC, UART4, GP0
PINCNTL169
DSIS: N/A
VOUT[1]_B_CB_C[9]/
EMAC[1]_MRXD[5]/
VIN[1]A_D[6]/
I2C[3]_SDA/
GP3[6] 		AA24 O IPD
DVDD		 EMAC[1], VIN[1]A, I2C[3], GP3
PINCNTL214
DSIS: N/A		 Video Output Data. These signals represent the 8 MSBs of B/CB/C video data. For RGB mode they are blue data bits, for YUV444 mode they are Cb (Chroma) data bits, for Y/C mode they are multiplexed Cb/Cr (Luma) data bits, and for BT.656 mode they are not used.
VOUT[1]_B_CB_C[8]/
EMAC[1]_MRXD[4]/
VIN[1]A_D[5]/
I2C[3]_SCL/
GP3[5] 		AH26 O IPD
DVDD		 EMAC[1], VIN[1]A, I2C[3], GP3
PINCNTL213
DSIS: N/A
VOUT[1]_B_CB_C[7]/
EMAC[1]_MRXD[3]/
VIN[1]A_D[4]/
UART3_TXD/
GP3[4] 		AC25 O IPD
DVDD		 EMAC[1], VIN[1]A, UART3, GP3
PINCNTL212
DSIS: N/A
VOUT[1]_B_CB_C[6]/
EMAC[1]_MRXD[2]/
VIN[1]A_D[3]/
UART3_RXD/
GP3[3] 		AD25 O IPD
DVDD		 EMAC[1], VIN[1]A, UART3, GP3
PINCNTL211
DSIS: N/A
VOUT[1]_B_CB_C[5]/
EMAC[1]_MRXD[1]/
VIN[1]A_D[2]/
UART4_TXD/
GP3[2] 		AF25 O IPD
DVDD		 EMAC[1], VIN[1]A, UART4, GP3
PINCNTL210
DSIS: N/A		 Video Output Data. These signals represent the 8 MSBs of B/CB/C video data. For RGB mode they are blue data bits, for YUV444 mode they are Cb (Chroma) data bits, for Y/C mode they are multiplexed Cb/Cr (Luma) data bits, and for BT.656 mode they are not used.
VOUT[1]_B_CB_C[4]/
EMAC[1]_MRXD[0]/
VIN[1]A_D[1]/
UART4_RXD/
GP3[1] 		AG25 O IPD
DVDD		 EMAC[1], VIN[1]A, UART4, GP3
PINCNTL209
DSIS: N/A
VOUT[1]_B_CB_C[3]/
EMAC[1]_MRCLK/
VIN[1]A_D[0]/
UART4_CTS/
GP3[0] 		AH25 O IPD
DVDD		 EMAC[1], VIN[1]A, UART4, GP3
PINCNTL208
DSIS: N/A
VOUT[1]_B_CB_C[2]/
GPMC_A[0]/
VIN[1]A_D[7]/
HDMI_CEC/
SPI[2]_D[0]/
GP3[30] 		AF28 O IPU
DVDD		 GPMC, VIN[1]A, HDMI, SPI[2], GP3
PINCNTL231
DSIS: N/A
VOUT[1]_B_CB_C[1]/
CAM_HS/
GPMC_A[9]/
UART2_RXD/
GP0[26] 		AE23 O IPD
DVDD_C		 CAMERA_I/F, GPMC, UART2, GP0
PINCNTL172
DSIS: N/A		 Video Output Data. These signals represent the 2 LSBs of B/CB/C video data for 20-bit, and 30-bit video modes. For RGB mode they are blue data bits, for YUV444 mode they are Cb (Chroma) data bits, for Y/C mode they are multiplexed Cb/Cr (Chroma) data bits and for BT.656 mode they are unused. These signals are not used in 16/24-bit modes.
VOUT[1]_B_CB_C[0]/
CAM_VS/
GPMC_A[10]/
UART2_TXD/
GP0[27] 		AD23 O IPU
DVDD_C		 CAMERA_I/F, GPMC, UART2, GP0
PINCNTL173
DSIS: N/A
VOUT[1]_R_CR[9]/
EMAC[1]_MTXEN/
VIN[1]A_D[20]/
UART5_TXD/
GP3[19] 		Y24 O IPD
DVDD		 EMAC[1], VIN[1]A, UART5, GP3
PINCNTL227
DSIS: N/A		 Video Output Data. These signals represent the 8 MSBs of R/CR video data. For RGB mode they are red data bits, for YUV444 mode they are Cr (Chroma) data bits, for Y/C mode and BT.656 mode they are not used.
VOUT[1]_R_CR[8]/
EMAC[1]_MTXD[7]/
VIN[1]A_D[19]/
UART5_RXD/
GP3[18] 		W23 O IPD
DVDD		 EMAC[1], VIN[1]A, UART5, GP3
PINCNTL226
DSIS: N/A
VOUT[1]_R_CR[7]/
EMAC[1]_MTXD[6]/
VIN[1]A_D[18]/
SPI[3]_D[0]/
GP3[17] 		V22 O IPD
DVDD		 EMAC[1], VIN[1]A, SPI[3], GP3
PINCNTL225
DSIS: N/A
VOUT[1]_R_CR[6]/
EMAC[1]_MTXD[5]/
VIN[1]A_D[17]/
SPI[3]_D[1]/
GP3[16] 		AA25 O IPD
DVDD		 EMAC[1], VIN[1]A, SPI[3], GP3
PINCNTL224
DSIS: N/A
VOUT[1]_R_CR[5]/
EMAC[1]_MTXD[4]/
VIN[1]A_D[16]/
SPI[3]_SCLK/
GP3[15] 		AC26 O IPD
DVDD		 EMAC[1], VIN[1]A, SPI[3], GP3
PINCNTL223
DSIS: N/A		 Video Output Data. These signals represent the 8 MSBs of R/CR video data. For RGB mode they are red data bits, for YUV444 mode they are Cr (Chroma) data bits, for Y/C mode and BT.656 mode they are not used.
VOUT[1]_R_CR[4]/
EMAC[1]_MTXD[3]/
VIN[1]A_D[15]/
SPI[3]_SCS[1]/
GP3[14] 		AG27 O IPD
DVDD		 EMAC[1], VIN[1]A, SPI[3], GP3
PINCNTL222
DSIS: N/A
VOUT[1]_R_CR[3]/
GPMC_A[14]/
VIN[1]A_D[22]/
HDMI_SDA/
SPI[2]_SCLK/
I2C[2]_SDA/
GP3[21]		 AG28 O IPU
DVDD		 GPMC, VIN[1]A, HDMI, SPI[2], I2C[2], GP3
PINCNTL229
DSIS: N/A
VOUT[1]_R_CR[2]/
GPMC_A[15]/
VIN[1]A_D[23]/
HDMI_HPDET/
SPI[2]_D[1]/
GP3[22] 		AE27 O IPU
DVDD		 GPMC, VIN[1]A, HDMI, SPI[2], I2C[2], GP3
PINCNTL230
DSIS: N/A
VOUT[1]_R_CR[1]/
CAM_D[1]/
GPMC_A[7]/
UART4_CTS/
GP0[24] 		AC19 O IPD
DVDD_C		 CAMERA_I/F, GPMC, UART4, GP0
PINCNTL170
DSIS: N/A		 Video Output Data. These signals represent the 2 LSBs of R/CR video data for 30-bit video modes. For RGB mode they are red data bits, for YUV444 mode they are Cr (Chroma) data bits, for Y/C mode and BT.656 modes they are not used. These signals are not used in 24-bit mode.
VOUT[1]_R_CR[0]/
CAM_D[0]/
GPMC_A[8]/
UART4_RTS/
GP0[25] 		AA22 O IPD
DVDD_C		 CAMERA_I/F, GPMC, UART4, GP0
PINCNTL171
DSIS: N/A
VOUT[1]_VSYNC/
EMAC[1]_MCRS/
VIN[1]A_FLD/
VIN[1]A_DE/
SPI[3]_D[0]/
UART3_CTS/
GP2[30] 		AA23 O IPD
DVDD		 EMAC[1], VIN[1]A, SPI[3], UART3, GP2
PINCNTL206
DSIS: N/A		 Video Output Vertical Sync output. This is the discrete vertical synchronization output. This signal is not used for embedded sync modes
VOUT[1]_HSYNC/
EMAC[1]_MCOL/
VIN[1]A_VSYNC/
SPI[3]_D[1]/
UART3_RTS/
GP2[29] 		AC24 O IPD
DVDD		 EMAC[1], VIN[1]A, SPI[3], UART3, GP2
PINCNTL205
DSIS: N/A		 Video Output Horizontal Sync output. This is the discrete horizontal synchronization output. This signal is not used for embedded sync modes.
VOUT[1]_FLD/
CAM_FLD/
CAM_WE/
GPMC_A[11]/
UART2_CTS/
GP0[28] 		AB23 O IPD
DVDD_C		 CAMERA_I/F, GPMC, UART2, GP0
PINCNTL174
DSIS: N/A		 Video Output Field ID output. This is the discrete field identification output. This signal is not used for embedded sync modes.
VOUT[1]_AVID/
EMAC[1]_MRXER/
VIN[1]A_CLK/
UART4_RTS/
TIM6_IO/
GP2[31] 		Y22 O IPD
DVDD		 EMAC[1], VIN[1]A, UART4, TIMER6, GP2
PINCNTL207
DSIS: N/A		 Video Output Active Video output. This is the discrete active video indicator output. This signal is not used for embedded sync modes.
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS = De-selected Input State
(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the Internal Pull after Reset. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see Section 3.5.1, Pullup/Pulldown Resistors and Section 6.3.17, Pin Behaviors at Reset.
(3) Specifies the operating I/O supply voltage for each signal

2.11.24 Video Output (Analog, TV)

Table 2-47 Video Outupt (Analog, TV) Terminal Functions

SIGNAL TYPE(1) OTHER(2) (3) DESCRIPTION
NAME NO.
VIDEO INTERFACES (TV)
TV_OUT0 AH24 O –
VDDA_VDAC_1P8		 Composite/S-Video (Luminance) Amplifier Output.

In Normal mode (internal amplifier used), this pin drives the 75-Ω TV load. An external resistor (Rout) should be connected between this pin and the TV_VFB0 pin and be placed as close to the pins as possible. The nominal value of Rout is 2700 Ω.

In TVOUT Bypass mode (internal amplifier not used), this pin is not used.

When this pin is not used or the TV output is powered-down, this pin should be left unconnected.
TV_OUT1 AH22 O –
VDDA_VDAC_1P8		 S-Video (Chrominance) Amplifier Output.

In Normal mode (internal amplifier used), this pin drives the 75-Ω TV load.
An external resistor (Rout) should be connected between this pin and the TV_VFB1 pin and be placed as close to the pins as possible. The nominal value of Rout is 2700 Ω.

In TVOUT Bypass mode (internal amplifier not used), this pin is not used.

When this pin is not used or the TV output is powered-down, this pin should be left unconnected.
TV_VFB0 AG23 A O –
VDDA_VDAC_1P8		 Composite/S-Video (Luminance) Feedback.

In Normal mode (internal amplifier used), this pin acts as the buffer feedback node.
An external resistor (Rout) should be connected between this pin and the TV_OUT0 pin.

In TVOUT Bypass mode (internal amplifier not used), this pin acts as the direct Video DAC output and should be connected to ground through a load resistor (Rload) and to an external video amplifier. The nominal value of Rload is 1500 Ω.

When this pin is not used or the TV output is powered-down, this pin should be left unconnected.
TV_VFB1 AG22 A O –
VDDA_VDAC_1P8		 S-Video (Chrominance) Feedback.

In Normal mode (internal amplifier used), this pin acts as the buffer feedback node.
An external resistor (Rout) should be connected between this pin and the TV_OUT1 pin.

In TVOUT Bypass mode (internal amplifier not used), it acts as the direct Video DAC output and should be connected to ground through a load resistor (Rload) and to an external video amplifier. The nominal value of Rload is 1500 Ω.

When this pin is not used or the TV output is powered-down, this pin should be left unconnected.
TV_RSET AH23 A –
VDDA_VDAC_1P8		 TV Input Reference Current Setting.
An external resistor (Rset) should be connected between this pin and VSSA_VDAC to set the reference current of the video DAC. The value of the resistor depends on the mode of operation.

In Normal mode (internal amplifier used), the nominal value for Rset is 4700 Ω.

In TVOUT Bypass mode (internal amplifier not used), the nominal value for Rset is 10000 Ω.

When the TV output is not used, this pin should be connected to ground (VSS).
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS = De-selected Input State
(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the Internal Pull after Reset. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see Section 3.5.1, Pullup/Pulldown Resistors and Section 6.3.17, Pin Behaviors at Reset.
(3) Specifies the operating I/O supply voltage for each signal

2.11.25 Reserved Pins

Table 2-48 Reserved Terminal Functions

SIGNAL TYPE(1) OTHER DESCRIPTION
NAME NO.
RSV1 AD8 O Reserved. (Leave unconnected, do not connect to power or ground.)
RSV2 U8 O Reserved. (Leave unconnected, do not connect to power or ground.)
RSV3 V8 O Reserved. (Leave unconnected, do not connect to power or ground.)
RSV4 Y14 I Reserved. (Leave unconnected, do not connect to power or ground.)
RSV5 AC8 I
RSV6 L27 I Reserved. (Leave unconnected, do not connect to power or ground.)
RSV7 L28 I
RSV8 M27 I
RSV9 M28 I
RSV10 N28 I
RSV11 N27 I
RSV12 P28 I
RSV13 P27 I
RSV14 R27 I
RSV15 R28 I
RSV16 U1 I Reserved. (Leave unconnected, do not connect to power or ground.)
RSV17 U2 I Reserved. (Leave unconnected, do not connect to power or ground.)
RSV18 N10 S Reserved. For proper device operation, this pin must always be tied directly to a 1-µF capacitor to ground (VSS).
RSV19 N11 S Reserved. For proper device operation, this pin must always be tied directly to a 1-µF capacitor to ground (VSS).
RSV20 P11 S Reserved. For proper device operation, this pin must be tied directly to the 1.8-V core supply.
RSV21 P10 S Reserved. For proper device operation, this pin must always be tied directly to a 1-µF capacitor to ground (VSS).
RSV22 M11 S Reserved. For proper device operation, this pin must always be tied directly to a 1-µF capacitor to ground (VSS).
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS = De-selected Input State

2.11.26 Supply Voltages

Table 2-49 Supply Voltages Terminal Functions

SIGNAL TYPE(1) OTHER DESCRIPTION
NAME NO.
VREFSSTL_DDR[0] G15 S Reference Power Supply DDR[0]
VREFSSTL_DDR[1] G14 S Reference Power Supply DDR[1]
CVDD K9, K10, K12, K18, L9, L10, L11, L12, L14, L15, L17, L19, M10, M12, M13, M14, M16, M18, N9, N13, N14, N17, N19, P12, P14, P16, R15, R17, R19, T12, U11, U13, U17, U19, W11 S Variable Voltage Supply for the CORE_L Core Logic Voltage Domain
For actual voltage supply ranges, see Section 5.2, Recommended Operating Conditions.
CVDD_ARM T14, T15, T16, U15, U16, V15, V16 S Variable Voltage Supply for the ARM_L Core Logic Voltage Domain
For actual voltage supply ranges, see Section 5.2, Recommended Operating Conditions.
DVDD M8, N7, P8, T7, U21, U22, V20,Y11, Y16, AA15, AA17, AB14, AB16 S 3.3 V/1.8 V Power Supply for General I/Os
DVDD_GPMC K20, L21, M20 S 3.3 V/1.8 V Power Supply for GPMC I/Os (that is, GPMC, SD2, and so forth)
DVDD_GPMCB P20, T20 S 3.3 V/1.8 V Power Supply for GPMCB I/Os
DVDD_SD P7, P9 S 3.3 V/1.8 V Power Supply for MMC/SD/SDIO I/Os (specifically, SD0, SD1, and pin W6)
DVDD_DDR[0] E20, E21, G16, H16, H17, J15, J16, J17, J18 S 1.5 V/1.8 V Power Supply for DDR[0] I/Os
DVDD_DDR[1] E8, E9, G13, H12, H13, H14, J10, J11, J13 S 1.5 V/1.8 V Power Supply for DDR[1] I/Os
DVDD_M R10 S 1.8 V Power Supply . For proper device operation, this pin must always be connected to a 1.8-V Power Supply.
DVDD_C W19, W20 S 3.3 V/1.8 V Power Supply for Camera I/F I/Os
VDDA_ARMPLL_1P8 R13 S 1.8 V Analog Power Supply for PLL_ARM and PLL_SGX
VDDA_VID0PLL_1P8 AB18 S 1.8 V Analog Power Supply for PLL_VIDEO0
VDDA_VID1PLL_1P8 AA18 S 1.8 V Analog Power Supply for PLL_VIDEO1
VDDA_AUDIOPLL_1P8 R18 S 1.8 V Analog Power Supply for PLL_AUDIO
VDDA_DDRPLL_1P8 H15 S 1.8 V Analog Power Supply for PLL_DDR
VDDA_L3PLL_1P8 N18 S 1.8 V Analog Power Supply for PLL_L3, PLL_HDVPSS, and PLL_MEDIACTL
VDDA_PCIE_1P8 W9, W10 S 1.8 V Analog Power Supply for PCIe.
For proper device operation, this pin must always be connected to a 1.8-V Power Supply, even if the PCIe is not being used.
VDDA_SATA_1P8 U9, U10 S 1.8 V Analog Power Supply for SATA.
For proper device operation, this pin must always be connected to a 1.8-V Power Supply, even if the SATA is not being used.
VDDA_HDMI_1P8 W18 S 1.8 V Analog Power Supply for HDMI PHY and PLL_VIDEO2.
For proper device operation, this pin must always be connected to a 1.8-V Power Supply, even if the HDMI is not being used.
VDDA_USB0_1P8 AA12 S 1.8 V Analog Power Supply for USB0 and PLL_USB.
For proper device operation, this pin must always be connected to a 1.8-V Power Supply, even if the USB0 is not being used.
VDDA_USB1_1P8 W13 S 1.8 V Analog Power Supply for USB1.
For proper device operation, this pin must always be connected to a 1.8-V Power Supply, even if the USB1 is not being used.
VDDA_VDAC_1P8 AB19 S 1.8 V Reference Power Supply for VDAC.
For proper device operation, this pin must always be connected to a 1.8-V Power Supply, even if the VDAC is not being used.
VDDA_USB_3P3 AA13 S 3.3 V Analog Power Supply for USB0 and USB1.
For proper device operation, this pin must always be connected to a 3.3-V Power Supply, even if USB0 and USB1 are not being used.
VDDA_1P8 L20, M7, M22, R20, U7, V10, W15, Y13 S 1.8 V Power Supply for on-chip LDOs and I/O biasing
LDOCAP_ARM W14 A ARM Cortex-A8 VBB LDO output.
This pin must always be connected via a 1-uF capacitor to VSS.
LDOCAP_ARMRAM V14 A ARM Cortex-A8 RAM LDO output.
This pin must always be connected via a 1-uF capacitor to VSS.
LDOCAP_RAM0 P18 A CORE RAM0 LDO output.
This pin must always be connected via a 1-uF capacitor to VSS.
LDOCAP_RAM1 R11 A CORE RAM1 LDO output.
This pin must always be connected via a 1-uF capacitor to VSS.
LDOCAP_RAM2 L18 A CORE RAM2 LDO output.
This pin must always be connected via a 1-uF capacitor to VSS.
LDOCAP_SGX T10 A SGX530 VBB LDO output.
This pin must always be connected via a 1-uF capacitor to VSS.
LDOCAP_SERDESCLK T11 A SERDES_CLKP/N Pins LDO output.
This pin must always be connected via a 1-uF capacitor to VSS.
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS = De-selected Input State

2.11.27 Ground Pins (VSS)

Table 2-50 Ground Terminal Functions

SIGNAL TYPE(1) OTHER DESCRIPTION
NAME NO.
VSS A1, A12, A17, A28, D9, D20, J12, J14, J19, K11, K13, K14, K15, K16, K17, K19, L8, L13, L16, L22, M9, M15, M17, M19, M21, N8, N12, N15, N16, N20, N21, N22, P13, P15, P17, P19, P21, R8, R9, R12, R14, R16, R21, R22, T8, T9, T13, T17, T18, T19, T21, T22, U12, U14, U18, U20, V7, V9, V11, V17, V19, V21, W12, W16, W17, Y1, Y2, Y10, Y12, Y15, Y17, Y18, Y19, AA14, AA16, AD21, AE1, AE2, AE9, AE20, AF23, AG1, AH1, AH28 GND Ground (GND)
VSSA_VDAC AA19 GND Analog GND for VDAC.
For proper device operation, this pin must always be connected to ground, even if the VDAC is not being used.
VSSA_HDMI V18 GND Analog GND for HDMI
For proper device operation, this pin must always be connected to ground, even if the HDMI is not being used.
VSSA_USB V12, V13 GND Analog GND for USB0 and USB1.
For proper device operation, this pin must always be connected to ground, even if USB0 and USB1 are not being used.
VSSA_DEVOSC AG3 GND Ground for Device Oscillator
VSSA_AUXOSC R2 GND Ground for Auxiliary Oscillator
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS = De-selected Input State