SPRS695D September   2011  – January 2016 AM3871 , AM3874

PRODUCTION DATA.  

  1. 1High-Performance System-on-Chip (SoC)
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
    1. 2.1  Device Comparison
    2. 2.2  Device Characteristics
    3. 2.3  Device Compatibility
    4. 2.4  ARM Cortex-A8 Microprocessor Unit (MPU) Subsystem Overview
      1. 2.4.1 ARM Cortex-A8 RISC Processor
      2. 2.4.2 Embedded Trace Module (ETM)
      3. 2.4.3 ARM Cortex-A8 Interrupt Controller (AINTC)
      4. 2.4.4 ARM Cortex-A8 PLL (PLL_ARM)
      5. 2.4.5 ARM MPU Interconnect
    5. 2.5  Media Controller Overview
    6. 2.6  SGX530 Overview
    7. 2.7  Spinlock Module Overview
    8. 2.8  Mailbox Module Overview
    9. 2.9  Memory Map Summary
      1. 2.9.1 L3 Memory Map
      2. 2.9.2 L4 Memory Map
        1. 2.9.2.1 L4 Fast Peripheral Memory Map
        2. 2.9.2.2 L4 Slow Peripheral Memory Map
      3. 2.9.3 DDR DMM TILER Extended Addressing Map
    10. 2.10 Pin Maps
    11. 2.11 Terminal Functions
      1. 2.11.1  Boot Configuration
      2. 2.11.2  Camera Interface (I/F)
      3. 2.11.3  Controller Area Network (DCAN) Modules (DCAN0, DCAN1)
      4. 2.11.4  DDR2/DDR3 Memory Controller
      5. 2.11.5  EDMA
      6. 2.11.6  EMAC [(R)(G)MII Modes] and MDIO
      7. 2.11.7  General-Purpose Input/Outputs (GPIOs)
      8. 2.11.8  GPMC
      9. 2.11.9  HDMI
      10. 2.11.10 I2C
      11. 2.11.11 McASP
      12. 2.11.12 McBSP
      13. 2.11.13 PCI-Express (PCIe)
      14. 2.11.14 Reset, Interrupts, and JTAG Interface
      15. 2.11.15 Serial ATA (SATA) Signals
      16. 2.11.16 SD Signals (MMC/SD/SDIO)
      17. 2.11.17 SPI
      18. 2.11.18 Oscillator/PLL, Audio Reference Clocks, and Clock Generator
      19. 2.11.19 Timer
      20. 2.11.20 UART
      21. 2.11.21 USB
      22. 2.11.22 Video Input (Digital)
      23. 2.11.23 Video Output (Digital)
      24. 2.11.24 Video Output (Analog, TV)
      25. 2.11.25 Reserved Pins
      26. 2.11.26 Supply Voltages
      27. 2.11.27 Ground Pins (VSS)
  3. 3Device Configurations
    1. 3.1 Control Module Registers
    2. 3.2 Boot Modes
      1. 3.2.1 XIP (NOR) Boot Options
      2. 3.2.2 NAND Flash Boot
      3. 3.2.3 NAND I2C Boot (I2C EEPROM)
      4. 3.2.4 MMC/SD Cards Boot
      5. 3.2.5 SPI Boot
      6. 3.2.6 Ethernet PHY Mode Selection
      7. 3.2.7 PCIe Bootmode (PCIE_32 and PCIE_64)
      8. 3.2.8 UART Bootmode
    3. 3.3 Pin Multiplexing Control
    4. 3.4 Handling Unused Pins
    5. 3.5 DeBugging Considerations
      1. 3.5.1 Pullup/Pulldown Resistors
  4. 4 System Interconnect
  5. 5Device Operating Conditions
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Recommended Operating Conditions
    3. 5.3 Power-On Hours (POH)
    4. 5.4 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Temperature (Unless Otherwise Noted)
    5. 5.5 Thermal Resistance Characteristics (PBGA Package) [CYE-04] (Thinner Top Hat)
  6. 6Power, Reset, Clocking, and Interrupts
    1. 6.1 Power, Reset and Clock Management (PRCM) Module
    2. 6.2 Power
      1. 6.2.1 Voltage and Power Domains
        1. 6.2.1.1 Core Logic Voltage Domains
        2. 6.2.1.2 Memory Voltage Domains
        3. 6.2.1.3 Power Domains
      2. 6.2.2 SmartReflex [Not Supported]
        1. 6.2.2.1 Dynamic Voltage Frequency Scaling (DVFS)
        2. 6.2.2.2 Adaptive Voltage Scaling [Not Supported]
      3. 6.2.3 Memory Power Management
      4. 6.2.4 SERDES_CLKP and SERDES_CLKN LDO
      5. 6.2.5 Dual Voltage I/Os
      6. 6.2.6 I/O Power-Down Modes
      7. 6.2.7 Standby Mode
      8. 6.2.8 Supply Sequencing
        1. 6.2.8.1 Power-Up Sequence
        2. 6.2.8.2 Power-Down Sequence
      9. 6.2.9 Power-Supply Decoupling
        1. 6.2.9.1 Analog and PLL
        2. 6.2.9.2 Digital
    3. 6.3 Reset
      1. 6.3.1  System-Level Reset Sources
      2. 6.3.2  Power-on Reset (POR pin)
      3. 6.3.3  External Warm Reset (RESET pin)
      4. 6.3.4  Emulation Warm Reset
      5. 6.3.5  Watchdog Reset
      6. 6.3.6  Software Global Cold Reset
      7. 6.3.7  Software Global Warm Reset
      8. 6.3.8  Test Reset (TRST pin)
      9. 6.3.9  Local Reset
      10. 6.3.10 Reset Priority
      11. 6.3.11 Reset Status Register
      12. 6.3.12 PCIE Reset Isolation
      13. 6.3.13 EMAC Switch Reset Isolation
      14. 6.3.14 RSTOUT_WD_OUT Pin
      15. 6.3.15 Effect of Reset on Emulation and Trace
      16. 6.3.16 Reset During Power Domain Switching
      17. 6.3.17 Pin Behaviors at Reset
      18. 6.3.18 Reset Electrical Data/Timing
    4. 6.4 Clocking
      1. 6.4.1  Device (DEV) and Auxiliary (AUX) Clock Inputs
        1. 6.4.1.1 Using the Internal Oscillators
        2. 6.4.1.2 Using a 1.8V LVCMOS-Compatible Clock Input
      2. 6.4.2  SERDES_CLKN/P Input Clock
      3. 6.4.3  AUD_CLKINx Input Clocks
      4. 6.4.4  CLKIN32 Input Clock
      5. 6.4.5  External Input Clocks
      6. 6.4.6  Output Clocks Select Logic
      7. 6.4.7  Input/Output Clocks Electrical Data/Timing
      8. 6.4.8  PLLs
        1. 6.4.8.1 PLL Power Supply Filtering
        2. 6.4.8.2 PLL Multipliers and Dividers
        3. 6.4.8.3 PLL Frequency Limits
        4. 6.4.8.4 PLL Register Descriptions
      9. 6.4.9  SYSCLKs
      10. 6.4.10 Module Clocks
    5. 6.5 Interrupts
      1. 6.5.1 ARM Cortex-A8 Interrupts
  7. 7 Peripheral Information and Timings
    1. 7.1  Parameter Information
      1. 7.1.1 1.8-V and 3.3-V Signal Transition Levels
      2. 7.1.2 3.3-V Signal Transition Rates
      3. 7.1.3 Timing Parameters and Board Routing Analysis
    2. 7.2  Recommended Clock and Control Signal Transition Behavior
    3. 7.3  Controller Area Network Interface (DCAN)
      1. 7.3.1 DCAN Peripheral Register Descriptions
      2. 7.3.2 DCAN Electrical Data/Timing
    4. 7.4  EDMA
      1. 7.4.1 EDMA Channel Synchronization Events
      2. 7.4.2 EDMA Peripheral Register Descriptions
    5. 7.5  Emulation Features and Capability
      1. 7.5.1 Advanced Event Triggering (AET)
      2. 7.5.2 Trace
      3. 7.5.3 IEEE 1149.1 JTAG
        1. 7.5.3.1 JTAG ID (JTAGID) Register Description
        2. 7.5.3.2 JTAG Electrical Data/Timing
    6. 7.6  Ethernet MAC Switch (EMAC SW)
      1. 7.6.1 EMAC Peripheral Register Descriptions
      2. 7.6.2 EMAC Electrical Data/Timing
        1. 7.6.2.1 EMAC MII and GMII Electrical Data/Timing
        2. 7.6.2.2 EMAC RMII Electrical Data/Timing
        3. 7.6.2.3 EMAC RGMII Electrical Data/Timing
      3. 7.6.3 Management Data Input/Output (MDIO)
        1. 7.6.3.1 MDIO Peripheral Register Descriptions
        2. 7.6.3.2 MDIO Electrical Data/Timing
    7. 7.7  General-Purpose Input/Output (GPIO)
      1. 7.7.1 GPIO Peripheral Register Descriptions
      2. 7.7.2 GPIO Electrical Data/Timing
    8. 7.8  General-Purpose Memory Controller (GPMC) and Error Location Module (ELM)
      1. 7.8.1 GPMC and ELM Peripherals Register Descriptions
      2. 7.8.2 GPMC Electrical Data/Timing
        1. 7.8.2.1 GPMC/NOR Flash Interface Synchronous Mode Timing (Nonmultiplexed and Multiplexed Modes)
        2. 7.8.2.2 GPMC/NOR Flash Interface Asynchronous Mode Timing (Nonmultiplexed and Multiplexed Modes)
        3. 7.8.2.3 GPMC/NAND Flash and ELM Interface Timing
    9. 7.9  High-Definition Multimedia Interface (HDMI)
      1. 7.9.1 HDMI Design Guidelines
        1. 7.9.1.1 HDMI Interface Schematic
        2. 7.9.1.2 TMDS Routing
        3. 7.9.1.3 DDC Signals
        4. 7.9.1.4 HDMI ESD Protection Device (Required)
        5. 7.9.1.5 PCB Stackup Specifications
        6. 7.9.1.6 Grounding
    10. 7.10 High-Definition Video Processing Subsystem (HDVPSS)
      1. 7.10.1 HDVPSS Electrical Data/Timing
      2. 7.10.2 Video DAC Guidelines and Electrical Data/Timing
    11. 7.11 Inter-Integrated Circuit (I2C)
      1. 7.11.1 I2C Peripheral Register Descriptions
      2. 7.11.2 I2C Electrical Data/Timing
    12. 7.12 Imaging Subsystem (ISS)
      1. 7.12.1 ISSCAM Electrical Data/Timing
    13. 7.13 DDR2/DDR3 Memory Controller
      1. 7.13.1 DDR2/3 Memory Controller Register Descriptions
      2. 7.13.2 DDR2/DDR3 PHY Register Descriptions
      3. 7.13.3 DDR-Related Control Module Registers Description
      4. 7.13.4 DDR2/DDR3 Memory Controller Electrical Data/Timing
        1. 7.13.4.1 DDR2 Routing Specifications
          1. 7.13.4.1.1 DDR2 Interface
            1. 7.13.4.1.1.1  DDR2 Interface Schematic
            2. 7.13.4.1.1.2  Compatible JEDEC DDR2 Devices
            3. 7.13.4.1.1.3  PCB Stackup
            4. 7.13.4.1.1.4  Placement
            5. 7.13.4.1.1.5  DDR2 Keepout Region
            6. 7.13.4.1.1.6  Bulk Bypass Capacitors
            7. 7.13.4.1.1.7  High-Speed Bypass Capacitors
            8. 7.13.4.1.1.8  Net Classes
            9. 7.13.4.1.1.9  DDR2 Signal Termination
            10. 7.13.4.1.1.10 VREFSSTL_DDR Routing
          2. 7.13.4.1.2 DDR2 CK and ADDR_CTRL Routing
        2. 7.13.4.2 DDR3 Routing Specifications
          1. 7.13.4.2.1 DDR3 versus DDR2
          2. 7.13.4.2.2 DDR3 EMIFs
          3. 7.13.4.2.3 DDR3 Device Combinations
          4. 7.13.4.2.4 DDR3 Interface Schematic
            1. 7.13.4.2.4.1  Compatible JEDEC DDR3 Devices
            2. 7.13.4.2.4.2  PCB Stackup
            3. 7.13.4.2.4.3  Placement
            4. 7.13.4.2.4.4  DDR3 Keepout Region
            5. 7.13.4.2.4.5  Bulk Bypass Capacitors
            6. 7.13.4.2.4.6  High-Speed Bypass Capacitors
              1. 7.13.4.2.4.6.1 Return Current Bypass Capacitors and Vias
            7. 7.13.4.2.4.7  Net Classes
            8. 7.13.4.2.4.8  DDR3 Signal Termination
            9. 7.13.4.2.4.9  VREFSSTL_DDR Routing
            10. 7.13.4.2.4.10 VTT
            11. 7.13.4.2.4.11 CK and ADDR_CTRL Topologies and Routing Definition
              1. 7.13.4.2.4.11.1 Four DDR3 Devices
                1. 7.13.4.2.4.11.1.1 CK and ADDR_CTRL Topologies, Four DDR3 Devices
                2. 7.13.4.2.4.11.1.2 CK and ADDR_CTRL Routing, Four DDR3 Devices
              2. 7.13.4.2.4.11.2 Two DDR3 Devices
                1. 7.13.4.2.4.11.2.1 CK and ADDR_CTRL Topologies, Two DDR3 Devices
                2. 7.13.4.2.4.11.2.2 CK and ADDR_CTRL Routing, Two DDR3 Devices
              3. 7.13.4.2.4.11.3 One DDR3 Device
                1. 7.13.4.2.4.11.3.1 CK and ADDR_CTRL Topologies, One DDR3 Device
                2. 7.13.4.2.4.11.3.2 CK and ADDR/CTRL Routing, One DDR3 Device
            12. 7.13.4.2.4.12 Data Topologies and Routing Definition
              1. 7.13.4.2.4.12.1 DQS and DQ/DM Topologies, Any Number of Allowed DDR3 Devices
              2. 7.13.4.2.4.12.2 DQS and DQ/DM Routing, Any Number of Allowed DDR3 Devices
            13. 7.13.4.2.4.13 Routing Specification
              1. 7.13.4.2.4.13.1 CK and ADDR_CTRL Routing Specification
              2. 7.13.4.2.4.13.2 DQS and DQ Routing Specification
    14. 7.14 Multichannel Audio Serial Port (McASP)
      1. 7.14.1 McASP Device-Specific Information
      2. 7.14.2 McASP0, McASP1, McASP2, McASP3, McASP4, and McASP5 Peripheral Registers Descriptions
      3. 7.14.3 McASP (McASP[5:0]) Electrical Data/Timing
    15. 7.15 Multichannel Buffered Serial Port (McBSP)
      1. 7.15.1 McBSP Peripheral Register Descriptions
      2. 7.15.2 McBSP Electrical Data/Timing
    16. 7.16 MultiMedia Card/Secure Digital/Secure Digital Input Output (MMC/SD/SDIO)
      1. 7.16.1 MMC/SD/SDIO Peripheral Register Descriptions
      2. 7.16.2 MMC/SD/SDIO Electrical Data/Timing
    17. 7.17 Peripheral Component Interconnect Express (PCIe)
      1. 7.17.1 PCIe Peripheral Register Descriptions
      2. 7.17.2 PCIe Electrical Data/Timing
      3. 7.17.3 PCIe Design and Layout Guidelines
        1. 7.17.3.1 Clock Source
        2. 7.17.3.2 PCIe Connections and Interface Compliance
          1. 7.17.3.2.1 Coupling Capacitors
          2. 7.17.3.2.2 Polarity Inversion
        3. 7.17.3.3 Nonstandard PCIe Connections
          1. 7.17.3.3.1 PCB Stackup Specifications
          2. 7.17.3.3.2 Routing Specifications
    18. 7.18 Serial ATA Controller (SATA)
      1. 7.18.1 SATA Peripheral Register Descriptions
      2. 7.18.2 SATA Interface Design Guidelines
        1. 7.18.2.1 SATA Interface Schematic
        2. 7.18.2.2 Compatible SATA Components and Modes
        3. 7.18.2.3 PCB Stackup Specifications
        4. 7.18.2.4 Routing Specifications
        5. 7.18.2.5 Coupling Capacitors
    19. 7.19 Serial Peripheral Interface (SPI)
      1. 7.19.1 SPI Peripheral Register Descriptions
      2. 7.19.2 SPI Electrical Data/Timing
    20. 7.20 Timers
      1. 7.20.1 Timer Peripheral Register Descriptions
      2. 7.20.2 Timer Electrical/Data Timing
    21. 7.21 Universal Asynchronous Receiver/Transmitter (UART)
      1. 7.21.1 UART Peripheral Register Descriptions
      2. 7.21.2 UART Electrical/Data Timing
    22. 7.22 Universal Serial Bus (USB2.0)
      1. 7.22.1 USB2.0 Peripheral Register Descriptions
      2. 7.22.2 USB2.0 Electrical Data/Timing
  8. 8Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
      2. 8.1.2 Device and Development-Support Tool Nomenclature
    2. 8.2 Documentation Support
    3. 8.3 Related Links
    4. 8.4 Community Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Export Control Notice
    8. 8.8 Glossary
  9. 9Mechanical, Packaging, and Orderable Information
    1. 9.1 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • CYE|684
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Power, Reset, Clocking, and Interrupts

6.1 Power, Reset and Clock Management (PRCM) Module

The PRCM module is the centralized management module for the power, reset, and clock control signals of the device. The PRCM interfaces with all the components on the device for power, clock, and reset management through power-control signals. The PRCM module inTiming Requirements for AUD_CLKINxtegrates enhanced features to allow the device to adapt energy consumption dynamically, according to changing application and performance requirements. The innovative hardware architecture allows a substantial reduction in leakage current.

The PRCM module is composed of two main entities:

  • Power reset manager (PRM): Handles the power, reset, wake-up management, and system clock source control (oscillator)
  • Clock manager (CM): Handles the clock generation, distribution, and management.

For more details on the PRCM, see the Power, Reset, and Clock Management (PRCM) Module chapter of the AM387x Sitara™ ARM Processors Technical Reference Manual (SPRUGZ7).

6.2 Power

6.2.1 Voltage and Power Domains

Every Module within the device belongs to a Core Logic Voltage Domain, Memory Voltage Domain, and a Power Domain (see Table 6-1).

Table 6-1 Voltage and Power Domains

CORE LOGIC
VOLTAGE DOMAIN
MEMORY VOLTAGE
DOMAIN
POWER
DOMAIN
MODULES
ARM_L ARM_M ALWAYS ON ARM Cortex-A8 Subsystem


CORE_L


CORE_M
DCAN0/1, DMM, EDMA, ELM, DDR0/1, EMAC Switch, GPIO Banks 0/1/2/3,GPMC, I2C0/1/2/3, IPC, MCASP0/1/2/3/4/5, MCBSP, OCMC SRAM, PCIE, PRCM, RTC, SATA, SD/MMC0/1/2, SPI01/2/3, Timer1/2/3/4/5/6/7/8, UART0/1/2/3/4/5, USB0/1, WDT0, System Interconnect, JTAG, Media Controller, ISS
GFX SGX530
HDVPSS HDVPSS, HDMI, SD-DAC

6.2.1.1 Core Logic Voltage Domains

The device contains four Core Logic Voltage Domains. These domains define groups of Modules that share the same supply voltage for their core logic. Each Core Logic Voltage Domain is powered by a dedicated supply voltage rail. Table 6-2 shows the mapping between the Core Logic Voltage Domains and their associated supply pins.

Table 6-2 Core Logic Voltage Domains and Supply Pin Associations

CORE LOGIC
VOLTAGE DOMAIN
SUPPLY PIN NAME
ARM_L CVDD_ARM
CORE_L CVDD

Note: A regulated supply voltage must be supplied to each Core Logic Voltage Domain at all times, regardless of the Core Logic Power Domain states.

6.2.1.2 Memory Voltage Domains

The SRAM within each Device Module is assigned to one of four Memory Voltage Domains. The voltage of each Memory Voltage Domain is independently controlled by internal LDO regulators, which are supplied by the VDDA_1P8 pins.

The voltage level output by each of these LDO regulators is controlled through software by programming the RAMLDO_CTRLx registers in the Control Module. The Memory Voltage Domain voltage must be programmed based on the Core Logic Voltage Domain voltage for that domain (that is, the corresponding Core Logic Voltage Domain for the ARM_M Voltage Domain is ARM_C, and so on). Table 6-3 shows the Memory Voltage Domain voltage requirements.

Table 6-3 Memory Voltage Domain LDO Requirements

CORE LOGIC VOLTAGE
DOMAIN VOLTAGE (V)
MEMORY VOLTAGE DOMAIN
VOLTAGE (V)
0.83 – 1.20 1.20

6.2.1.3 Power Domains

The device contains six Power Domains which supply power to both the Core Logic and SRAM within their associated modules. Each Power Domain, except for the ALWAYS ON domain, has an internal power switch that can completely remove power from that domain. All power switches are turned "OFF" by default after reset, and software can individually turn them "ON/OFF" via Control Module registers.

Note: All Modules within a Power Domain are unavailable when the domain is powered "OFF". For instructions on powering "ON/OFF" the Power domains, see the Power, Reset, and Clock Management (PRCM) Module chapter of the AM387x Sitara™ ARM Processors Technical Reference Manual (SPRUGZ7).

6.2.2 SmartReflex [Not Supported]

The device contains SmartReflex modules that help to minimize power consumption on the Core Logic Voltage Domains by using external variable-voltage power supplies. Based on the device process, temperature, and desired performance, the SmartReflex modules advise the host processor to raise or lower the supply voltage to each domain for minimal power consumption.

The communication link between the host processor and the external regulators is a system-level decision and can be accomplished using GPIOs, I2C, SPI, or other methods. The following sections briefly describe the two major techniques employed by SmartReflex: Dynamic Voltage Frequency Scaling (DVFS) and Adaptive Voltage Scaling (AVS).

6.2.2.1 Dynamic Voltage Frequency Scaling (DVFS)

Each device Core Logic Voltage Domain can be run independently at one of several Operating Performance Points (OPPs). An OPP for a specific Core Logic Voltage Domain is defined by: (1) maximum frequencies of operation for Modules within the Domain and (2) an associated supply voltage range. Trading off power versus performance, OPPs with lower maximum frequencies also have lower voltage ranges for power savings.

The OPP for a domain can be changed in real-time without requiring a reset. This feature is called Dynamic Voltage Frequency Scaling (DVFS). Table 6-4 contains a list of voltage ranges and maximum module frequencies for the OPPs of each Core Logic Voltage Domain.

Table 6-4 Device Operating Points (OPPs)

CORE LOGIC VOLTAGE DOMAINS
ARM CORE
OPP Cortex A8
(MHz)
HDVPSS
(MHz)
SGX
(MHz)
ISS
(MHz)
Media Ctlr.
(MHz)
L3/L4,
Core
(MHz)
DDR
(MHz)(1)
100%(1.1 V) 600 200 200 400 200 200 400
120% (1.2 V) 720 200 250 400 200 220 400
166% (1.35 V) 800 220 280 480 240 220 533
1000 220 280 480 240 220 533
(1) All DDR access must be suspended prior to changing the DDR frequency of operation.

Although the OPP for each Core Logic Voltage Domain is independently selectable, not all combinations of OPPs are supported. Table 6-5 marks the supported ARM OPPs for a given CORE OPP.

Table 6-5 Supported OPP Combinations(1)(2)

ARM
CORE OPP166 OPP120 OPP100
OPP166 X
OPP120 X X
OPP100 X X
(1) "X" denotes supported combinations.
(2) The maximum voltage differences between CVDD and any other CVDD_x voltage domain must be < 150 mV.

6.2.2.2 Adaptive Voltage Scaling [Not Supported]

As mentioned in Section 6.2.2.1, Dynamic Voltage Frequency Scaling (DVFS) above, every OPP has an associated voltage range. Based on the silicon process, temperature, and chosen OPP, the SmartReflex modules guide software in adjusting the Core Logic Voltage Domain supply voltages within these ranges. This technique is called Adaptive Voltage Scaling (AVS). AVS occurs continuously and in real-time, helping to minimize power consumption in response to changing operating conditions.

6.2.3 Memory Power Management

To reduce SRAM leakage, many SRAM blocks can be switched from ACTIVE mode to SHUTDOWN mode. When SRAM is put in SHUTDOWN mode, the voltage supplied to it is automatically removed and all data in that SRAM is lost.

All SRAM located in a switchable power domain (all domains except ALWAYS_ON) automatically enters SHUTDOWN mode whenever its associated power domain goes into the "OFF" state. The SRAM returns to the ACTIVE state when the corresponding Power Domain returns to the "ON" state.

In addition, the following SRAM within the ALWAYS_ON Power Domain can also be independently put into SHUTDOWN by programming the x_MEM_PWRDN registers in the Control Module:

  • Media Controller SRAM
  • OCMC SRAM

For detailed instructions on powering up/down the various device SRAM, see the Control Module chapter of the AM387x Sitara™ ARM Processors Technical Reference Manual (SPRUGZ7).

6.2.4 SERDES_CLKP and SERDES_CLKN LDO

The SERDES_CLKP and SERDES_CLKN input buffers are powered by an internal LDO which is programmed through the REFCLK_LJCBLDO_CTRL register in the Control Module.

For more information on programming the SERDES_CLKP and SERDES_CLKN LDO, see PCI Express (PCIe) Module and Serial ATA (SATA) Controller chapters of the AM387x Sitara™ ARM Processors Technical Reference Manual (SPRUGZ7).

6.2.5 Dual Voltage I/Os

The device supports dual voltages on some of its I/Os. These I/Os are partitioned into the following groups, and each group has its own dedicated supply pins: DVDD, DVDD_GPMC, DVDD_C, and DVDD_SD. The supply voltage for each group can be independently powered with either 1.8 V or 3.3 V.

For the mapping between pins and power groups, see Section 2.11.

In addition, the I/O voltage on each DDR interface is independently selectable between either 1.5 V or 1.8 V to support various DDR device types. The I/O supplies for each DDR interface are separate and isolated to allow populating different memory types on each interface.

6.2.6 I/O Power-Down Modes

On the device, there are power-down modes available for the following PHYs:

  • Video DAC
  • DDR
  • USB
  • HDMI
  • PCIE
  • SATA

When a PHY controller is in a power domain that is to be turned "OFF", software must configure the corresponding PHY into power-down mode, prior to putting the power domain in the "OFF" state.

6.2.7 Standby Mode

The device supports Low-Power Standby Mode as described below.

Standby Mode is defined as a state in which:

  • All switchable power domains are in "OFF" state
  • The ARM Cortex-A8 is executing an IDLE loop at its lowest frequency of operation
  • All functional blocks not needed for a given application are clock gated

For detailed instructions on entering and exiting from Standby Mode see the Power, Reset, and Clock Management (PRCM) Module chapter of the AM387x Sitara™ ARM Processors Technical Reference Manual (SPRUGZ7).

6.2.8 Supply Sequencing

The device power supplies are organized into four Supply Sequencing Groups:

  1. All CVDD supplies (CVDD, CVDD_x)
  2. All 1.5-/1.8-V DVDD_DDR[x] Supplies (1.5 V for DDR3, 1.8 V for DDR2)
  3. All 1.8-V Supplies (DVDD_x, DVDD_M, VDDA_x_1P8, VDDA_1P8)
  4. All 3.3-V Supplies (DVDD, DVDD_x, DVDD_C, VDDA_x_3P3)

To ensure proper device operation, a specific power-up and power-down sequence must be followed. Some TI power-supply devices include features that facilitate these power sequencing requirements — for example, TI’s TPS659113 integrated PMIC. For more information on TI power supplies and their features, visit www.ti.com/processorpower.

For more detailed information on the actual power supply names and their descriptions, see Table 2-49, Supply Voltages Terminal Functions.

6.2.8.1 Power-Up Sequence

For proper device operation, the following power-up sequence in Table 6-6 and must be followed.

Table 6-6 Power-Up Sequence Ramping Values

NO. DESCRIPTION MIN MAX UNIT
1 1.8 V and DVDD_DDR[x] supplies stable to 3.3 V supplies ramp start 0 ms
2 1.8 V supplies to 1.5-/1.8- V DVDD_DDR[x] supplies 0(1) ms
3 1.8 V supplies stable to CVDD, CVDD_x variable supplies ramp start 0(1) ms
13 CVDD variable supply ramp start to CVDD_x variable supplies ramp start 0 ms
4 All supplies valid to power-on-reset (POR high) 4 096 Master
Clocks
(1) The 1.8 V supplies must be ≥ 1.5-/1.8-V DVDD_DDR[x] supplies.
AM3874 AM3871 power_up_sequence.gif Figure 6-1 Power-Up Sequence

6.2.8.2 Power-Down Sequence

For proper device operation, the following power-down sequence in Table 6-7 and Figure 6-2 must be followed. Ramping down all supplies at the same time is allowed, provided the requirements in Table 6-7 are met.

Table 6-7 Power-Down Sequence Ramping Values

NO. DESCRIPTION MIN MAX UNIT
8 CVDD, CVDD_x variable supply to 1.8 V supplies See (2) See (2) ms
9 1.5-/1.8-V DVDD_DDR[x] supplies to 1.8 V supplies See (2) See (2) ms
10 3.3 V supplies to 1.8 V supplies See (1) See (1) ms
14 CVDD_x variable supplies ramp-down start to CVDD variable supply ramp-down start 0 ms
(1) The 3.3 V supplies must never be more than 2 V above the 1.8 V supplies (see Figure 6-3).
(2) The 1.5-/1.8-V DVDD_DDR[x] and CVDD, CVDD_x variable supplies can be powered down prior to or simultaneously with the 1.8-V supplies.
AM3874 AM3871 power_down_sequence_DDR2_3.gif Figure 6-2 Power-Down Sequence
AM3874 AM3871 1.8VSupp_Falling_3.3V_Sup_Delta.gif Figure 6-3 1.8 V Supplies Falling Before 3.3 V Supplies Delta

6.2.9 Power-Supply Decoupling

6.2.9.1 Analog and PLL

PLL and Analog supplies benefit from filters or ferrite beads to keep the noise from causing problems. The minimum recommendation is a ferrite bead along with at least one capacitor on the device side of the bead. An additional recommendation is to add one capacitor just before the bead to form a Pi filter. The filter must be as close as possible to the device pin, with the device side capacitor being the most important component to be close to the device pin. PLL pins close together can be combined on the same supply, but analog pins should all have their own filters. PLL pins farther away from each other may need their own filtered supply.

6.2.9.2 Digital

Recommended capacitors for power supply decoupling are all 0.1uF in the smallest body size that can be used. Capacitors are more effective in the smallest physical size to limit lead inductance. For example, 0201 sized capacitors are better than 0402 sized capacitors, and so on. TI recommends using capacitors no larger than 0402. Place at least one capacitor for every two power pins. For those power pins that have only one pin, a capacitor is still required. Place one bulk (10 uF or larger) capacitor for every 10 or so power pins as closely as possible to the chip. These larger capacitors do not need to be under the chip footprint.

Pay special attention not to put so much capacitance on the supply that it slows the start-up voltage ramp enough to change the power sequencing order. Also be sure to verify that the main chip reset is low until after all supplies are at their correct voltage and stable.

DDR peripheral related supply capacitor numbers are provided in Section 7.13, DDR2/DDR3 Memory Controller.

6.3 Reset

6.3.1 System-Level Reset Sources

The device has several types of system-level resets. Table 6-8 lists these reset types, along with the reset initiator, and the effects of each reset on the device.

Table 6-8 System-Level Reset Types

TYPE INITIATOR RESETS ALL MODULES, EXCLUDING EMAC SWITCH, EMULATION, PLL AND CLOCK CONFIG RESETS EMAC SWITCH RESETS EMULATION PLL AND CLOCK CONFIG LATCHES
BOOT PINS
ASSERTS
RSTOUT_WD_OUT
PIN
Power-on Reset (POR) POR pin Yes Yes Yes Yes Yes Optional(2)(3)
External Warm Reset RESET pin Yes Optional(1) No No Yes Optional(2)(3)
Emulation Warm Reset On-Chip Emulation Logic Yes Optional(1) No No No Optional(2)
Watchdog Reset Watchdog Timer Yes Optional(1) No No No Yes
Software Global Cold Reset Software Yes Optional(1) Yes Yes No Optional(2)
Software Global Warm Reset Software Yes Optional(1) No No No Optional(2)
Test Reset TRST pin No No Yes No No No
(1) EMAC Switch is NOT reset when the ISO_CONTROL bit in the RESET_ISO Control Module register is set to "1".
(2) RSTOUT_WD_OUT pin asserted only if BTMODE[11] was latched as "0" when coming out of reset.
(3) While POR and/or RESET is asserted, the RSTOUT_WD_OUT pin is 3-stated and the internal pull resistor is disabled; therefore, an external pullup/pulldown can be used to set the state of this pin (high/low) while POR and/or RESET is asserted. For more detailed information on external PUs/PDs, see Section 3.5.1, Pullup/Pulldown Resistors.

6.3.2 Power-on Reset (POR pin)

Power-on Reset (POR) is initiated by the POR pin and is used to reset the entire chip, including the Test and Emulation logic, and the EMAC Switch. POR is also referred to as a cold reset because it is required to be asserted when the device goes through a power-up cycle. However, a device power-up cycle is not required to initiate a Power-on Reset.

The following sequence must be followed during a Power-on Reset:

  1. Wait for the power supplies to reach normal operating conditions while keeping the POR pin asserted.
  2. Wait for the input clock sources DEV_CLKIN, AUX_CLKIN, and SERDES_CLKN/P to be stable (if used by the system) while keeping the POR pin asserted (low).
  3. Once the power supplies and the input clock sources are stable, the POR pin must remain asserted (low) [see Section 6.3.18, Reset Electrical Data/Timing]. Within the low period of the POR pin, the following happens:
    1. All pins except Emulation pins enter a Hi-Z mode and the associated pulls, if applicable, will be enabled.
    2. The PRCM asserts reset to all modules within the device.
    3. The PRCM begins propagating these clocks to the chip with the PLLs in BYPASS mode.
  4. The POR pin may now be deasserted (driven high). When the POR pin is deasserted (high):
    1. The BTMODE[15:0] pins are latched.
    2. Reset to the ARM Cortex-A8 and Modules without a local processor is deasserted.
    3. RSTOUT_WD_OUT is briefly asserted if BTMODE[11] was latched as "0".
    4. The clock, reset, and power-down state of each peripheral is determined by the default settings of the PRCM.
    5. The ARM Cortex-A8 begins executing from the Boot ROM.

6.3.3 External Warm Reset (RESET pin)

An external warm reset is activated by driving the RESET pin active-low. This resets everything in the device, except for the Test and Emulation logic, and the EMAC Switch (optional). An emulator session stays alive during warm reset.

The following sequence must be followed during a warm reset:

  1. Power supplies and input clock sources should already be stable.
  2. The RESET pin must be asserted (low)[see Section 6.3.18, Reset Electrical Data/Timing]. Within the low period of the RESET pin, the following happens:
    1. All pins, except Test and Emulation pins, enter a Hi-Z mode and the associated pulls, if applicable, will be enabled.
    2. The PRCM asserts reset to all modules within the device, except for the Test and Emulation logic, EMAC Switch (optional), PLL, and Clock configuration.
  3. The RESET pin may now be deasserted (driven high). When the RESET pin is deasserted (high):
    1. The BTMODE[15:0] pins are latched.
    2. Reset to the ARM Cortex-A8 and modules without a local processor is deasserted, with the exception of Test and Emulation logic, EMAC Switch (optional), PLL, and Clock configuration.
    3. RSTOUT_WD_OUT is asserted [see Section 6.3.18, Reset Electrical Data/Timing], if BTMODE[11] was latched as "0".
    4. The clock, reset, and power-down state of each peripheral is determined by the default settings of the PRCM.
    5. The ARM Cortex-A8 begins executing from the Boot ROM.

6.3.4 Emulation Warm Reset

An Emulation Warm Reset is activated by the on-chip Emulation Module and has the same effect and requirements as an External Warm Reset (RESET), with the following exceptions:

  • BTMODE[15:0] pins are not relatched
  • RSTOUT_WD_OUT is not 3-stated and is actively driven based on the value previously latched on the BTMODE[11] pin.

The emulator initiates an Emulation Warm Reset via the ICEPICK module. To invoke the Emulation Warm Reset via the ICEPICK module, the user can perform the following from the Code Composer Studio™ IDE menu: Target -> Reset -> System Reset.

6.3.5 Watchdog Reset

A Watchdog Reset is initiated when the Watchdog Timer counter reaches zero and has the same effect and requirements as an External Warm Reset (RESET pin), with the following exceptions:

  • BTMODE[15:0] pins are not relatched
  • RSTOUT_WD_OUT is not 3-stated and is actively driven based on the value previously latched on the BTMODE[11] pin.

In addition, a Watchdog Reset always results in RSTOUT_WD_OUT being asserted, regardless of whether the BTMODE[11] pin was latched as "0" or "1".

6.3.6 Software Global Cold Reset

A Software Global Cold Reset is initiated under software control and has the same effect and requirements as a POR Reset, with the following exceptions:

  • BTMODE[15:0] pins are not relatched and EMAC Switch (optional) is not reset
  • RSTOUT_WD_OUT is not 3-stated and is actively driven based on the value previously latched on the BTMODE[11] pin.

Software initiates a Software Global Cold Reset by writing a "1" to the RST_GLOBAL_COLD_SW bit in the PRM_RSTCTRL register in the PRCM.

For more detailed information on the PRM_RSTCTRL register, see the PRCM Registers section of the Power, Reset, and Clock Management (PRCM) Module chapter of the AM387x Sitara™ ARM Processors Technical Reference Manual (SPRUGZ7).

6.3.7 Software Global Warm Reset

A Software Global Warm Reset is initiated under software control and has the same effect and requirements as a External Warm Reset (RESET pin), with the following exceptions:

  • BTMODE[15:0] pins are not relatched
  • RSTOUT_WD_OUT is not 3-stated and is actively driven based on the value previously latched on the BTMODE[11] pin.

Software initiates a Software Global Warm Reset by writing a "1" to the RST_GLOBAL_WARM_SW bit in the PRM_RSTCTRL register in the PRCM.

For more detailed information on the PRM_RSTCTRL register, see the PRCM Registers section of the Power, Reset, and Clock Management (PRCM) Module chapter of the AM387x Sitara™ ARM Processors Technical Reference Manual (SPRUGZ7).

6.3.8 Test Reset (TRST pin)

A Test Reset is activated by the emulator asserting the TRST pin. The only effect a Test Reset has is to reset the Test and Emulation Logic.

6.3.9 Local Reset

The Local Reset for various Modules within the device is controlled by programming the PRCM and/or the Peripheral Module’s internal registers. Only the associated Module is reset when a Local Reset is asserted, leaving the rest of the device unaffected.

For more details on Peripheral Local Resets, see the Reset Management section of the Power, Reset, and Clock Management (PRCM) Module chapter of the AM387x Sitara™ ARM Processors Technical Reference Manual (SPRUGZ7).

6.3.10 Reset Priority

If any of the above reset sources occur simultaneously, the device only processes the highest-priority reset request. The reset request priorities, from high-to-low, are as follows:

  1. Power-on Reset (POR)
  2. Test Reset (TRST)
  3. External Warm Reset (RESET pin)
  4. Emulation Warm Resets
  5. Watchdog Reset
  6. Software Global Cold/Warm Resets

6.3.11 Reset Status Register

The Reset Status Register (PRM_RSTST) contains information about the last reset that occurred in the system. For more information on this register, see the Power, Reset, and Clock Management (PRCM) Module chapter of the AM387x Sitara™ ARM Processors Technical Reference Manual (SPRUGZ7).

6.3.12 PCIE Reset Isolation

The device supports reset isolation for the PCI-Express (PCIE) module. This means that the PCI-Express Subsystem can be reset without resetting the rest of the device.

When the devcie is a PCI-Express Root Complex (RC), the PCIE Subsystem can be reset by software through the PRCM. Software should ensure that there are no ongoing PCIE transactions before asserting this reset by first taking the PCIE Subsystem into the IDLE state. After bringing the PCIE Subsystem out of reset, bus enumeration should be performed again and should treat all Endpoints (EP) as if they had just been connected.

When the device is a PCI-Express Endpoint (EP), the PCIE Subsystem will generate an interrupt when an in-band reset is received. Software should process this interrupt by putting the PCIE Subsystem in the IDLE state and then asserting the PCIE local reset through the PRCM.

All device level resets mentioned in the previous sections, except Test Reset, will also reset the PCIE Subsystem. Therefore, the PCIE peripheral should issue a Hot Reset to all downstream devices and re-enumerate the bus upon coming out of reset.

For more detailed information on reset isolation procedures, see the PCIe Reset Isolation section of the Power, Reset, and Clock Management (PRCM) Module chapter of the AM387x Sitara™ ARM Processors Technical Reference Manual (SPRUGZ7).

6.3.13 EMAC Switch Reset Isolation

The device supports reset isolation for the Ethernet Switch (EMAC Switch). This allows the device to undergo all resets listed in Section 6.3.1, System-Level Reset Sources, with the exception of POR Reset, without disrupting the Ethernet Switch or the traffic being routed through the switch during the reset condition. The following reset types can optionally provide an EMAC Switch reset isolation by setting the ISO_CONTROL bit in the RESET_ISO Control Module register to a "1":

  • External Warm Reset
  • Emulation Warm Reset
  • Watchdog Reset
  • Software Global Cold Reset
  • Software Global Warm Reset

When one of above resets occurs and the Ethernet Switch (EMAC Switch) is programmed to be isolated:

  • The switch function of the EMAC Switch and the PLL embedded in the SATA SERDES Module (which provides the reference clocks to the EMAC Switch) will not be reset.
  • Several Control Module registers are not reset. For more details, see the description of the RESET_ISO register in the Control Module chapter of the AM387x Sitara™ ARM Processors Technical Reference Manual (SPRUGZ7).
  • The pin multiplexing of some of the EMAC Switch pins is unaffected. For more details, see the description of the RESET_ISO register in the Control Module chapter of the AM387x Sitara™ ARM Processors Technical Reference Manual (SPRUGZ7).

The EMAC Switch is always reset when:

  • One of the above resets occurs and the Ethernet Switch is programmed to be “not isolated”
  • A POR Reset occurs

6.3.14 RSTOUT_WD_OUT Pin

The RSTOUT_WD_OUT pin reflects device reset status and is deasserted (high) when the device is out reset. This output will always be asserted when a Watchdog Timer reset (Watchdog Reset) occurs. In addition, this output is always 3-stated and the internal pull resistor is disabled on this pin while POR and/or RESET is asserted; therefore, an external pullup/pulldown can be used to set the state of this pin (high/low) while POR and/or RESET is asserted. For more detailed information on external PUs/PDs, see Section 3.5.1, Pullup/Pulldown Resistors.

If the BTMODE[11] pin is latched as a "0" at the rising edge of POR or RESET, then RSTOUT_WD_OUT is also asserted when any of the below resets occur:

  • Power-On Reset (asserted after the BTMODE[11] pin is latched)
  • External Warm Reset (asserted after the BTMODE[11] pin is latched)
  • Emulation Warm Reset
  • Software Global Cold/Warm Reset

The RSTOUT_WD_OUT pin remains asserted until the PRCM releases the host ARM Cortex-A8 processor for reset.

6.3.15 Effect of Reset on Emulation and Trace

The device Emulation and Trace Logic will only be reset by the following sources:

  • Power-On Reset
  • Software Global Cold Reset
  • Test Reset

Other than these three reset types, none of the other resets will affect the Emulation and Trace Logic. However, the multiplexing of the EMU[4:2] pins is reset by all system reset types except Test Reset.

6.3.16 Reset During Power Domain Switching

Each Power Domain has a dedicated Warm Reset and Cold Reset. Warm Reset for a Power Domain is asserted under either of the following two conditions:

  1. An External Warm Reset, Emulation Warm Reset, or Software Global Warm Reset occurs
  2. When that Power Domain switches from the "ON" state to the "OFF" state

Cold Reset for a Power Domain is asserted under either of the following two conditions:

  1. Power-On Reset or Software Global Cold Reset occurs
  2. When that Power Domain switches from the "OFF" state to the "ON" state

6.3.17 Pin Behaviors at Reset

When any reset, other than Test Reset, (all described in Section 6.3.1, System-Level Reset Sources) is asserted, all device I/O pins are reset into a Hi-Z state except for:

  • Emulation Pins. These pins are only put into a Hi-Z state when Test Reset (TRST) is asserted.
  • EMAC Switch Pins. These pins are always put into a Hi-Z state during Power-On Reset. However, some EMAC Switch pins will not be put into a Hi-Z state during the other reset modes when the ISO_CONTROL bit in the RESET_ISO register of the Control Module is programmed as a "1". For more details, see the description of the RESET_ISO register in the Control Module chapter of the AM387x Sitara™ ARM Processors Technical Reference Manual (SPRUGZ7).
  • RSTOUT_WD_OUT Pin during any reset types except for POR and RESET. For more detailed information on RSTOUT_WD_OUT pin behavior, see Section 6.3.14, RSTOUT_WD_OUT Pin.
  • DDR[0]/[1] Address/Control Pins (CLK, CLK, CKE, WE, CS[1]/[0], RAS, CAS, ODT[1]/[0], RST, BA[2:0], A[14:0]). These pins are 3-stated during reset. However, these pins are then driven to the same value as their internal pull resistor reset value when reset is released (For the direction of the internal pull during reset, see the DDR[0]/[1] Terminal Functions tables in the Section 2.11.4, DDR2/DDR3 Memory Controller of this document).

In addition, the PINCNTL registers, which control pin multiplexing, enabling the IPUs/IPDs, and enabling the receiver, are reset to their default state. Again, enabling the EMAC Switch reset isolation prevents some PINCNTL registers from being reset.

For details on EMAC Switch reset isolation, see the descriptions of the RESET_ISO register and the PINCNTL registers in the Control Module chapter of the AM387x Sitara™ ARM Processors Technical Reference Manual (SPRUGZ7).

Internal pull-up/down (IPU/IPD) resistors are enabled during and immediately after reset as described in Section 2.11, Terminal Functions of this document.

NOTE

Upon coming out of reset, the ARM Cortex-A8 starts executing code from the internal Boot ROM. The Boot ROM code modifies the PINCNTLx registers to configure the associated pins for the chosen primary and backup Bootmodes. For more details on the Boot ROM effects on pin multiplexing, see the ROM Code Memory and Peripheral Booting and Control Module chapters of the AM387x Sitara™ ARM Processors Technical Reference Manual (SPRUGZ7).

6.3.18 Reset Electrical Data/Timing

Table 6-9 Timing Requirements for Reset (see Figure 6-4 and Figure 6-5)

NO. OPP100 UNIT
MIN MAX
1 tw(RESET) Pulse duration, POR low or RESET low 12P(2) ns
2 tsu(BOOT) Setup time, BTMODE[15:0] pins valid before POR high or RESET high POR 2P(1) ns
RESET 2P(1) ns
3 th(BOOT) Hold time, BTMODE[15:0] pins valid after POR high or RESET high 0 ns
(1) P = 1/(DEV Clock) frequency in ns.
(2) The device clock source must be stable and at a valid frequency prior to meeting the tw(RESET) requirement.

Table 6-10 Switching Characteristics Over Recommended Operating Conditions During Reset
(see Figure 6-5)

NO. PARAMETER OPP100 UNIT
MIN MAX
4 td(RSTL-IORST) Delay time, RESET low or POR low to all I/Os entering their reset state 14 ns
5 td(RSTH-IOFUNC) Delay time, RESET high or POR high to all I/Os exiting their reset state 14 ns
6 td(RSTH-RSTOUTH) Delay time, RESET high to RSTOUT_WD_OUT high(1)(2) RESET assertion tw(RESET) ≥ 30P 0 2P ns
RESET assertion tw(RESET) < 30P 0 32P - tw(RESET) ns
7 td(PORH-RSTOUTH) Delay time, POR high to RSTOUT_WD_OUT high(1)(2) 0 12500P ns
8 td(RSTL-RSTOUTZ) Delay time, RESET low to RSTOUT_WD_OUT Hi-Z(1)(2) 0 2P ns
9 td(PORH-RSTOUTL) Delay time, POR high to RSTOUT_WD_OUT driven based on latched BTMODE[11] value(1)(2) 0 2P ns
10 td(RSTH-RSTOUTD) Delay time, RESET high to RSTOUT_WD_OUT driven based on latched BTMODE[11] value(1)(2) 0 2P ns
(1) For more detailed information on RSTOUT_WD_OUT pin behavior, see Section 6.3.14, RSTOUT_WD_OUT Pin.
(2) P = 1/(DEV Clock) frequency in ns.

Figure 6-4 shows the Power-Up Timing. Figure 6-5 shows the Warm Reset (RESET) Timing. Max Reset Timing is identical to Warm Reset Timing, except the BTMODE[15:0] pins are not relatched.

AM3874 AM3871 td_reset_pwrup_prs647.gif
A. Power supplies and DEV_CLKIN/AUX_CLKIN must be stable before the start of tw(RESET).
B. RSTOUT_WD_OUT only asserted if BTMODE[11] was latched as a "0" when coming out of reset.
C. For more detailed information on the RESET STATE of each pin, see Section 6.3.17, Pin Behaviors at Reset. Also see Section 2.11, Terminal Functions for the IPU/IPD settings during reset.
Figure 6-4 Power-Up Timing
AM3874 AM3871 td_reset_prs647.gif
A. RSTOUT_WD_OUT only asserted if BTMODE[11] was latched as a "0" when coming out of reset.
B. For more detailed information on the RESET STATE of each pin, see Section 6.3.17, Pin Behaviors at Reset. Also see Section 2.11, Terminal Functions for the IPU/IPD settings during reset.
Figure 6-5 Warm Reset (RESET) Timing

6.4 Clocking

The device clocks are generated from several reference clocks that are fed to on-chip PLLs and dividers (both inside and outside of the PRCM Module). Figure 6-6 shows a high-level overview of the device system clocking structure (Note: to reduce complexity, not all clocking connections are shown). For detailed information on the device clocks, see the Clock Generation and Management section of the Power, Reset, and Clock Management (PRCM) Module chapter of the AM387x Sitara™ ARM Processors Technical Reference Manual (SPRUGZ7).

AM3874 AM3871 dg_sysclking_blk_NOCSI_prs695.gif Figure 6-6 System Clocking Overview

6.4.1 Device (DEV) and Auxiliary (AUX) Clock Inputs

The device provides two clock inputs, Device (DEVOSC_MXI/DEV_CLKIN) and Auxiliary (AUXOSC_MXI/AUX_CLKIN). The Device (DEV) clock is used to generate the majority of the internal reference clocks, while the Auxiliary (AUX) clock can optionally be used as a source for the Audio and/or Video PLLs.

The DEV and AUX clocks can be sourced in two ways:

  1. Using an external crystal in conjunction with the internal oscillator or
  2. Using an external 1.8-V LVCMOS-compatible clock input

Note: The external crystals used with the internal oscillators must operate in fundamental parallel resonant mode only. There is no overtone support.

The DEV Clock should in most cases be 20 MHz. However, it can optionally range anywhere from 20 - 30 MHz if the following are true:

  • The DEV Clock is not used to source the SATA reference clock
  • A precise 32768-Hz clock is not needed for Real-Time Clock functionality
  • If the boot mode is FAST XIP

The AUX Clock is optional and can range from 20-30 MHz. AUX Clock can be used to source the Audio and/or Video PLLs when a very precise audio or video frequency is required.

6.4.1.1 Using the Internal Oscillators

When the internal oscillators are used to generate the DEV and AUX clocks, external crystals are required to be connected across the DEVOSC or AUXOSC oscillator MXI and MXO pins, along with two load capacitors (see Figure 6-7 and Figure 6-8). The external crystal load capacitors should also be connected to the associated oscillator ground pin (VSSA_DEVOSC or VSSA_AUXOSC). The capacitors should not be connected to board ground (VSS).

AM3874 AM3871 dg_oscsys27_prs647.gif Figure 6-7 Device Oscillator
AM3874 AM3871 dg_auxosc24_prs647.gif Figure 6-8 Auxiliary Oscillator

The load capacitors, C1 and C2 in the above pictures, should be chosen such that the below equation is satisfied. CL in the equation is the load specified by the crystal manufacturer. All discrete components used to implement the oscillator circuit should be placed as close as possible to the associated oscillator MXI, MXO, and VSS pins.

AM3874 AM3871 osc_eqsysusb_prs647.gif

Table 6-11 Input Requirements for Crystal Circuit on the Device Oscillator (DEVOSC)

PARAMETER MIN TYP MAX UNIT
Start-up time (from power up until oscillating at stable frequency) 4 ms
Crystal Oscillation frequency(1) 20 20 30 MHz
Parallel Load Capacitance (C1 and C2) 12 24 pF
Crystal ESR 50 Ω
Crystal Shunt Capacitance 5 pF
Crystal Oscillation Mode Fundamental Only n/a
Crystal Frequency Stability If Ethernet not used ±200 ppm
If MII is used and RGMII, RMII not used ±100
If RGMII, or RMII used ±50
(1) 20-MHz DEV clock is required for all bootmodes other than Fast XIP. For more detailed information on boot modes, see the ROM Code Memory and Peripheral Booting chapter of the AM387x Sitara™ ARM Processors Technical Reference Manual (SPRUGZ7).

Table 6-12 Input Requirements for Crystal Circuit on the Auxiliary Oscillator (AUXOSC)

PARAMETER MIN MAX UNIT
Start-up time (from power up until oscillating at stable frequency) 4 ms
Crystal Oscillation frequency 20 30 MHz
Parallel Load Capacitance (C1 and C2) 12 24 pF
Crystal ESR 50 Ω
Crystal Shunt Capacitance 5 pF
Crystal Oscillation Mode Fundamental Only n/a
Crystal Frequency stability(1) ±50 ppm
(1) Applies only when sourcing the HDMI or HDVPSS DAC clocks from the AUXOSC

6.4.1.2 Using a 1.8V LVCMOS-Compatible Clock Input

A 1.8-V LVCMOS-Compatible Clock Input can be used instead of the internal oscillators as the DEV and AUX clock inputs to the system. The external connections to support this are shown in Figure 6-9 and Figure 6-10. The DEV_CLKIN and AUX_CLKIN pins are connected to the 1.8-V LVCMOS-Compatible clock sources. The DEV_MXO and AUX_MXO pins are left unconnected. The VSSA_DEVOSC and VSSA_AUXOSC pins are connected to board ground (VSS).

AM3874 AM3871 dg_osclvcmosd_prs647.gif Figure 6-9 1.8-V LVCMOS-Compatible Clock Input (DEV_OSC)
AM3874 AM3871 dg_osclvcmosa_prs647.gif Figure 6-10 1.8-V LVCMOS-Compatible Clock Input (AUX_OSC)

The clock source must meet the DEVOSC_MXI/DEV_CLKIN timing requirements shown in Table 6-15, Timing Requirements for DEVOSC_MXI/DEV_CLKIN.

The clock source must meet the AUXOSC_MXI/AUX_CLKIN timing requirements shown in Table 6-16, Timing Requirements for AUXOSC_MXI/AUX_CLKIN.

6.4.2 SERDES_CLKN/P Input Clock

A high-quality, low-jitter differential clock source is required for the PCIE PHY and is an optional clock source for the SATA PHY. The clock is required to be AC coupled to the SERDES_CLKP and SERDES_CLKN device pins according to the specifications in Table 6-13. Both the clock source and the coupling capacitors should be placed physically as close to the processor as possible. In addition, make sure to follow any PCB routing and termination recommendations that the clock source manufacturer recommends.

Table 6-13 SERDES_CLKN/P AC Coupling Capacitors Recommendations

PARAMETER MIN TYP MAX UNIT
SERDES_CLKN/P AC coupling capacitor value 0.24 0.27 1.0 nF
SERDES_CLKN/P AC coupling capacitor package size(1)(2) 0402 0603 EIA
(1) L x W, 10 Mil units, that is, a 0402 is a 40 x 20 Mil surface mount capacitor.
(2) The physical size of the capacitor should be as small as practical. Use the same size on both lines in each pair placed side-by-side.

The differential clock source is required to meet the REFCLK AC Specifications outlined in the PCI-EXPRESS CARD ELECTROMECHANICAL SPECIFICATION, REV. 2.0, at the input to the AC coupling capacitors.

In addition, LVDS clock sources that are compliant to the above specification, but with the following exceptions, are also acceptable:

Table 6-14 Acceptable Exceptions to the REFCLK AC Specifications for LVDS Clock Sources

PARAMETER MIN MAX UNIT
VIH Differential High-Level Input Voltage 125 1000 mV
VIL Differential Low-Level Input Voltage -1000 -125 mV

6.4.3 AUD_CLKINx Input Clocks

External clock inputs can optionally be provided at the AUD_CLKIN0/1/2 pins to serve as a reference clocks for the following modules:

  • McASP3/4/5
  • McBSP
  • TIMER1/2/3/4/5/6/7/8

6.4.4 CLKIN32 Input Clock

An external 32768-Hz clock input can optionally be provided at the CLKIN32 pin to serve as a reference clock in place of the RTCDIVIDER clock for the following Modules:

  • RTC
  • GPIO0/1/2/3
  • TIMER1/2/3/4/5/6/7/8
  • ARM Cortex-A8
  • SYNCTIMER

The CLKIN32 source must meet the timing requirements shown in Table 6-18.

6.4.5 External Input Clocks

There are three pins referred to as AUD_CLKIN0,1,2 which are used as optional sources for HDMI I2S, McASP, McBSP and TIMER1-8. The maximum IO pin frequency for these three input clocks is 50MHz.

6.4.6 Output Clocks Select Logic

The device includes two selectable general-purpose clock outputs (CLKOUT0 and CLKOUT1). The source for these output clocks is controlled by the CLKOUT_MUX register in the Control Module (see Figure 6-11).

AM3874 AM3871 dg_clkout01_prs647.gif
A. Muxed output of DEVOSC clock, USBPLL clock output, VIDEO0 PLL Clock output, and RTC DIVIDER output.
Figure 6-11 CLKOUTx Source Selection Logic

For detailed information on the CLKOUTx switching characteristics, see Table 6-19.

6.4.7 Input/Output Clocks Electrical Data/Timing

Note: If an external clock oscillator is used, a single clean power supply should be used to power both the device and the external clock oscillator circuit.

Table 6-15 Timing Requirements for DEVOSC_MXI/DEV_CLKIN(1) (2) (3)(see Figure 6-12)

NO. OPP100 UNIT
MIN NOM MAX
1 tc(DMXI) Cycle time, DEVOSC_MXI/DEV_CLKIN 33.33 50 50 ns
2 tw(DMXIH) Pulse duration, DEVOSC_MXI/DEV_CLKIN high 0.45C 0.55C ns
3 tw(DMXIL) Pulse duration, DEVOSC_MXI/DEV_CLKIN low 0.45C 0.55C ns
4 tt(DMXI) Transition time, DEVOSC_MXI/DEV_CLKIN 7 ns
5 tJ(DMXI) Period jitter, DEVOSC_MXI/DEV_CLKIN 0.02C ns
Frequency Stability If Ethernet not used ±200 ppm
If MII is used and RGMII, RMII not used ±100
If RGMII, or RMII used ±50
(1) The DEVOSC_MXI/DEV_CLKIN frequency and PLL settings should be chosen such that the resulting SYSCLKs and Module Clocks are within the specific ranges shown in the Section 6.4.9, SYSCLKs and Section 6.4.10, Module Clocks.
(2) The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.
(3) C = DEV_CLKIN cycle time in ns. For example, when DEVOSC_MXI/DEV_CLKIN frequency is 20 MHz, use C = 50 ns.
AM3874 AM3871 td_clkindev_prs647.gif Figure 6-12 DEV_MXI/DEV_CLKIN Timing

Table 6-16 Timing Requirements for AUX_MXI/AUX_CLKIN (1) (2) (see Figure 6-13)

NO. OPP100 UNIT
MIN NOM MAX
1 tc(AMXI) Cycle time, AUXOSC_MXI/AUX_CLKIN 33.3 50 50 ns
2 tw(AMXIH) Pulse duration, AUXOSC_MXI/AUX_CLKIN high 0.45C 0.55C ns
3 tw(AMXIL) Pulse duration, AUXOSC_MXI/AUX_CLKIN low 0.45C 0.55C ns
4 tt(AMXI) Transition time, AUXOSC_MXI/AUX_CLKIN 7 ns
5 tJ(AMXI) Period jitter, AUXOSC_MXI/AUX_CLKIN 0.02C ns
6 Sf Frequency stability, AUXOSC_MXI/AUX_CLKIN(3) ± 50 ppm
(1) The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.
(2) C = AUX_CLKIN cycle time in ns. For example, when AUXOSC_MXI/AUX_CLKIN frequency is 20 MHz, use C = 50 ns.
(3) Applies only when sourcing the HDMI or HDVPSS DAC clocks from the AUXOSC.
AM3874 AM3871 td_clkinaux_prs647.gif Figure 6-13 AUX_MXI/AUX_CLKIN Timing

Table 6-17 Timing Requirements for AUD_CLKINx (1) (see Figure 6-14)

NO. OPP100/120/166 UNIT
MIN NOM MAX
1 tc(AUD_CLKINx) Cycle time, AUD_CLKINx 20 ns
2 tw(AUD_CLKINxH) Cycle time, AUD_CLKINx 0.45A 0.55A ns
3 tw(AUD_CLKINxL) Cycle time, AUD_CLKINx 0.45A 0.55A ns
(1) A = AUD_CLKINx cycle time in ns.
AM3874 AM3871 td_clkinx_prs647.gif Figure 6-14 AUD_CLKINx Timing

Table 6-18 Timing Requirements for CLKIN32 (1)(2) (see Figure 6-15)

NO. OPP100 UNIT
MIN NOM MAX
1 tc(CLKIN32) Cycle time, CLKIN32 1/32768 s
2 tw(CLKIN32H) Pulse duration, CLKIN32 high 0.45C 0.55C ns
3 tw(CKIN32L) Pulse duration, CLKIN32 low 0.45C 0.55C ns
4 tt(CLKIN32) Transition time, CLKIN32 7 ns
5 tJ(CLKIN32) Period jitter, CLKIN32 0.02C ns
(1) The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.
(2) C = CLKIN32 cycle time in ns. For example, when CLKIN32 frequency is 32768 Hz, use C = 1/32768 s.
AM3874 AM3871 td_clkin32_prs647.gif Figure 6-15 CLKIN32 Timing

Table 6-19 Switching Characteristics Over Recommended Operating Conditions for CLKOUTx (CLKOUT0 and CLKOUT1)(1) (2)
(see Figure 6-16)

NO. PARAMETER OPP100 UNIT
MIN MAX
1 tc(CLKOUTx) Cycle time, CLKOUTx 5 ns
2 tw(CLKOUTxH) Pulse duration, CLKOUTx high 0.45P 0.55P ns
3 tw(CLKOUTxL) Pulse duration, CLKOUTx low 0.45P 0.55P ns
4 tt(CLKOUTx) Transition time, CLKOUTx 0.05P ns
(1) The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN.
(2) P = 1/CLKOUTx clock frequency in nanoseconds (ns). For example, when CLKOUTx frequency is 200 MHz, use P = 5 ns.
AM3874 AM3871 td_clkoutx_prs647.gif Figure 6-16 CLKOUTx Timing

6.4.8 PLLs

The device contains 12 top-level PLLs, and 4 embedded PLLs (within the ARM Cortex-A8, PCIE, SATA, and CSI) that provide clocks to different parts of the system. Figure 6-17 and Figure 6-18 show simplified block diagrams of the Top-Level PLL and PLL_ARM. In addition, see the System Clocking Overview (Figure 6-6) for a high-level view of the device clock architecture including the PLL reference clock sources and connections.

AM3874 AM3871 dg_tlpll_sblkdiag_prs647.gif Figure 6-17 Top-Level PLL Simplified Block Diagram
AM3874 AM3871 dg_armpll_sblkdiag_prs647.gif Figure 6-18 PLL_ARM Simplified Block Diagram

The reference clock for most of the PLLs comes from the DEV input clock, with select PLLs also having the option to use the AUX input clock as a reference. Also, each PLL supports a Bypass mode in which the reference clock can be directly passed to the PLL CLKOUT through a divider. All device PLL’s will come-up in Bypass mode after reset.

For details on programming the device PLLs, see the Control Module chapter of the AM387x Sitara™ ARM Processors Technical Reference Manual (SPRUGZ7).

6.4.8.1 PLL Power Supply Filtering

The device PLLs are supplied externally via the VDDA_x_1P8 power-supply pins (where "x" represents ARMPLL, VID0PLL, VID1PLL, AUDIOPLL, DDRPLL, L3PLL, USB0, and HDMI). External filtering must be added on the PLL supply pins to ensure that the requirements in Table 6-20 are met.

Table 6-20 PLL Power Supply Requirements

PARAMETER MIN MAX UNIT
Dynamic noise at VDDA_x_1P8 50 mV p-p

6.4.8.2 PLL Multipliers and Dividers

The Top-Level and PLL_ARM PLLs support the internal multiplier and divider values shown in Table 6-21, Top-Level PLL Multiplier and Divider Limits and Table 6-22, PLL_ARM Multiplier and Divider Limits. The PLLs must be programmed to conform to the various REFCLK, CLKDCO, DCOCLK, and CLKOUT limits described in Section 6.4.8.3, PLL Frequency Limits.

Table 6-21 Top-Level PLL Multiplier and Divider Limits

PARAMETER MIN MAX
N Predivider 0 255
PLL Multiplier (M) 2 4095(1)
M2 Post Divider 1 127
N2 Bypass Divider 0 15
(1) The PLL Multiplier supports fractional values (up to 18-bits of fraction) except when the PLL Multiplier is > 4093.

Table 6-22 PLL_ARM Multiplier and Divider Limits

PARAMETER MIN MAX
N Predivider 0 127
PLL Multiplier (M)(2) 2 2047(1)
M2 Post Divider 1 31
N2 Bypass Divider 0 15
(1) The PLL Multiplier supports fractional values (up to 18-bits of fraction) except when the PLL Multiplier is < 20 OR > 2045.
(2) This parameter describes the limits on the programmable multiplier value M. The multiplication factor for the PLL_ARM is equal to 2 * M (also see Figure 6-18).

6.4.8.3 PLL Frequency Limits

Each PLL supports a minimum and maximum operating frequency for its REFCLK, CKLDCO, and CLKOUT values. The PLLs must be configured not to exceed any of the constraints placed on these values shown in Table 6-23 through Table 6-25. Care must be taken to stay within these limits when selecting external clock input frequencies, internal divider values, and PLL multiply ratios. In addition, limits shown in these tables may be further restricted by the clock frequency limitations of the device modules using these clocks. For more detailed information on the SYSCLK and Module Clock frequency limits, see Section 6.4.9, SYSCLKs and Section 6.4.10, Module Clocks.

Table 6-23 Top-Level PLL Frequency Ranges (ALL OPPs)

CLOCK MIN MAX UNIT
REFCLK 0.5 2.5 MHz
CLKDCO (HS1)(1) 1000 2000 MHz
CLKDCO (HS2)(2) 500 1000 MHz
CLKOUT see Table 6-25 see Table 6-25 MHz
(1) The PLL has two modes of operation: HS1 and HS2. The mode of operation should be set, according to the desired CLKDCO frequency, by programming the SELFREQDCO field of the ADPLLLJx_CLKCTRL registers in the Control Module.
(2) CLKDCO of the PLL_USB is used undivided by the USB modules; therefore, CLKDCO for the PLL_USB PLL must be programmed to 960 MHz for proper operation.

Table 6-24 ARM Cortex-A8 Embedded PLL (PLL_ARM) Frequency Ranges (ALL OPPs)

CLOCK MIN MAX UNIT
REFCLK 0.032 52 MHz
DCOCLK 20 2000 MHz
CLKOUT see Table 6-25 see Table 6-25 MHz

Table 6-25 PLL CLKOUT Frequency Ranges

PLL OPP100 UNIT
MIN MAX
PLL_ARM 10 600 MHz
PLL_SGX 10 200 MHz
PLL_L3 10 200 MHz
PLL_DDR 10 400 MHz
PLL_HDVPSS 10 200 MHz
PLL_AUDIO 10 200 MHz
PLL_MEDIACTL 10 400 MHz
PLL_USB 10(1) 960 MHz
PLL_VIDEO0 10 200 MHz
PLL_VIDEO1 10 200 MHz
PLL_VIDEO2 10 200 MHz
(1) When the USB is used, PLL_USB must be fixed at 960 MHz.

6.4.8.4 PLL Register Descriptions

The PLL Control Registers reside in the Control Module and are listed in Section 3.1.

6.4.9 SYSCLKs

In some cases, the system clock inputs and PLL outputs are sent to the PRCM Module for division and multiplexing before being routed to the various device Modules. These clock outputs from the PRCM Module are called SYSCLKs. Table Table 6-26 lists the device SYSCLKs along with their maximum supported clock frequencies. In addition, limits shown in these tables may be further restricted by the clock frequency limitations of the device modules using these clocks. For more details on Module Clock frequency limits, see Section 6.4.10 Module Clocks.

Table 6-26 Maximum SYSCLK Clock Frequencies(1)

SYSCLK MAX CLOCK FREQUENCY
OPP100 (MHz)
SYSCLK1 RSV
SYSCLK2 RSV
SYSCLK3 266
SYSCLK4 200
SYSCLK5 RSV
SYSCLK6 100
SYSCLK7 RSV
SYSCLK8 192
SYSCLK9 RSV
SYSCLK10 48
SYSCLK11 RSV
SYSCLK12 RSV
SYSCLK13 RSV
SYSCLK14 27
SYSCLK15 RSV
SYSCLK16 27
SYSCLK17 RSV
SYSCLK18 0.032768
SYSCLK19 192
SYSCLK20 192
SYSCLK21 192
SYSCLK22 RSV
SYSCLK23 200
(1) The maximum frequencies listed in this table are valid for OPP100. Some of these frequencies have higher maximum values when OPP120 or OPP166 is used, see Table 6-4

6.4.10 Module Clocks

Device Modules either receive their clock directly from an external clock input, directly from a PLL, or from a PRCM SYSCLK output. Table 6-27 lists the clock source options for each Module on this device, along with the maximum frequency that Module can accept. To ensure proper Module functionality, the device PLLs and dividers must be programmed not to exceed the maximum frequencies listed in this table.

Table 6-27 Maximum Module Clock Frequencies(1)

MODULE CLOCK SOURCES MAX FREQUENCY
OPP100 (MHz)
Cortex-A8 PLL_ARM
SYSCLK18
600
DCAN0/1 DEV Clock 30
DDR0/1 PLL_DDR 400
DMM PLL_DDR/2 200
EDMA SYSCLK4 200
EMAC Switch (GMII) SATA SERDES Fixed 125
EMAC Switch (RGMII) PLL_VIDEO0
PLL_VIDEO1
PLL_VIDEO02
PLL_L3
Fixed 250
EMAC Switch (RMII and MII) SATA SERDES
EMAC_RMREFCLK Pin
Fixed 50
GPIO SYSCLK6 100
GPIO Debounce SYSCLK18 Fixed 0.032768
GPMC SYSCLK6 100
HDMI PLL_VIDEO2 186
HDMI CEC SYSCLK10 Fixed 48
HDMI I2S SYSCLK20
SYSCLK21
AUD_CLK0/1/2
AUX Clock
50
HDVPSS PLL_HDVPSS 200
HDVPSS VOUT1 PLL_VIDEO2
HDMI PHY
186
HDVPSS VOUT0 PLL_VIDEO1
PLL_VIDEO2
165
HDVPSS SD VENC PLL_VIDEO0 Fixed 54
I2C0/1/2/3 SYSCLK10 48
ISS PLL_ MEDIACTL 400
L3 Fast SYSCLK4 200
L3 Medium SYSCLK4 200
L3 Slow SYSCLK6 100
L4 Fast SYSCLK4 200
L4 Slow SYSCLK6 100
Mailbox SYSCLK6 100
McASP SYSCLK6 100
McASP0/1/2 AUX_CLK SYSCLK20
SYSCLK21
192
McASP3/4/5 AUX_CLK PLL_AUDIO
PLL_VIDEO0/1/2
AUD_CLK0/1/2
AUX Clock
192
McBSP CLKS SYSCLK20
SYSCLK21
AUD_CLK0/1/2
AUX Clock
192
Media Controller PLL_MEDIACTL/2 200
MMCSD0/1/2 SYSCLK8 192
OCMC RAM SYSCLK4 200
PCIe SERDES SERDES_CLKx Pins 100
SATA SERDES DEV Clock
SERDES_CLKx Pins
20 or 100
SGX530 SYSCLK23 200
SPI0/1/2/3 SYSCLK10 48
Spinlock SYSCLK6 100
Sync Timer SYSCLK18 Fixed 0.032768
TIMER1/2/3/4/5/6/7/8 SYSCLK18
DEV Clock
AUX Clock
AUD_CLK0/1/2
TCLKIN
30
UART0/1/2 SYSCLK10 48
UART3/4/5 SYSCLK6
SYSCLK8
SYSCLK10
192
USB PLL_USB CLKDCO Fixed 960
WDT0 RTCDIVIDER
RCOSC32K
Fixed 0.032768
(1) The maximum frequencies listed in this table are valid for OPP100. Some of these frequencies have higher maximum values when OPP120 or OPP166 is used, see Table 6-4

6.5 Interrupts

The device has a large number of interrupts to service the needs of its many peripherals and subsystems. The ARM Cortex-A8 and Media Controller are capable of servicing these interrupts. The following sections list the device interrupt mapping and multiplexing schemes.

6.5.1 ARM Cortex-A8 Interrupts

The ARM Cortex-A8 Interrupt Controller (AINTC) is responsible for prioritizing all service requests from the System peripherals and generating either IRQs or FIQs to the Cortex-A8. The AINTC has the capability to handle up to 128 requests, and the priority of the interrupt inputs are programmable. Table 6-28 lists the interrupt sources for the AINTC.

Note: For General-Purpose devices, the AINTC does not support the generation of FIQs to the ARM processor.

For more details on ARM Cortex-A8 interrupt control, see the ARM Interrupt Controller (AINTC) chapter of the AM387x Sitara™ ARM Processors Technical Reference Manual (SPRUGZ7).

Table 6-28 ARM Cortex-A8 Interrupt Controller (AINTC) Interrupt Sources

Cortex-A8
INTERRUPT NUMBER
ACRONYM SOURCE
0 EMUINT Cortex-A8 Emulation
1 COMMTX Cortex-A8 Emulation
2 COMMRX Cortex-A8 Emulation
3 BENCH Cortex-A8 Emulation
4 ELM_IRQ ELM
5 Reserved
6 Reserved
7 NMI NMIn Pin
8 Reserved
9 L3DEBUG L3 Interconnect
10 L3APPINT L3 Interconnect
11 TINT8 TIMER8
12 EDMACOMPINT EDMA CC Completion
13 EDMAMPERR EDMA Memory Protection Error
14 EDMAERRINT EDMA CC Error
15 WDTINT0 Watchdog Timer 0
16 SATAINT SATA
17 USBSSINT USB Subsystem
18 USBINT0 USB0
19 USBINT1 USB1
20-27 Reserved
28 SDINT1 MMC/SD1
29 SDINT2 MMC/SD2
30 I2CINT2 I2C2
31 I2CINT3 I2C3
32 GPIOINT2A GPIO2 A
33 GPIOINT2B GPIO2 B
34 USBWAKEUP USB Subsystem Wakeup
35 PCIeWAKEUP PCIe Wakeup
36 DSSINT HDVPSS
37 GFXINT SGX530
38 HDMIINT HDMI
39 ISS_IRQ_5 ISS
40 3PGSWRXTHR0 EMAC Switch RX Threshold
41 3PGSWRXINT0 EMAC Switch Receive
42 3PGSWTXINT0 EMAC Switch Transmit
43 3PGSWMISC0 EMAC Switch Miscellaneous
44 UARTINT3 UART3
45 UARTINT4 UART4
46 UARTINT5 UART5
47 - Reserved
48 PCIINT0 PCIe
49 PCIINT1 PCIe
50 PCIINT2 PCIe
51 PCIINT3 PCIe
52 DCAN0_INT0 DCAN0
53 DCAN0_INT1 DCAN0
54 DCAN0_PARITY DCAN0 Parity
55 DCAN1_INT0 DCAN1
56 DCAN1_INT1 DCAN1
57 DCAN1_PARITY DCAN1 Parity
58-61 Reserved
62 GPIOINT3A GPIO3
63 GPIOINT3B GPIO3
64 SDINT0 MMC/SD0
65 SPIINT0 SPI0
66 - Reserved
67 TINT1 TIMER1
68 TINT2 TIMER2
69 TINT3 TIMER3
70 I2CINT0 I2C0
71 I2CINT1 I2C1
72 UARTINT0 UART0
73 UARTINT1 UART1
74 UARTINT2 UART2
75 RTCINT RTC
76 RTCALARMINT RTC Alarm
77 MBINT Mailbox
78 Reserved
79 PLLINT PLL Recalculation Interrupt
80 MCATXINT0 McASP0 Transmit
81 MCARXINT0 McASP0 Receive
82 MCATXINT1 McASP1 Transmit
83 MCARXINT1 McASP1 Receive
84 MCATXINT2 McASP2 Transmit
85 MCARXINT2 McASP2 Receive
86 MCBSPINT McBSP
87 Reserved
88 Reserved
89 Reserved
90 Reserved
91 Reserved
92 TINT4 TIMER4
93 TINT5 TIMER5
94 TINT6 TIMER6
95 TINT7 TIMER7
96 GPIOINT0A GPIO0
97 GPIOINT0B GPIO0
98 GPIOINT1A GPIO1
99 GPIOINT1B GPIO1
100 GPMCINT GPMC
101 DDRERR0 DDR0
102 DDRERR1 DDR1
103 Reserved
104 Reserved
105 MCATXINT3 McASP3 Transmit
106 MCARXINT3 McASP3 Receive
107 Reserved
108 MCATXINT4 McASP4 Transmit
109 MCARXINT4 McASP4 Receive
110 MCATXINT5 McASP5 Transmit
111 MCARXINT5 McASP5 Receive
112 TCERRINT0 EDMA TC 0 Error
113 TCERRINT1 EDMA TC 1 Error
114 TCERRINT2 EDMA TC 2 Error
115 TCERRINT3 EDMA TC 3 Error
116-119 Reserved
122 MMUINT System MMU
123 MCMMUINT Media Controller
124 DMMINT DMM
125 SPIINT1 SPI1
126 SPIINT2 SPI2
127 SPIINT3 SPI3