Refer to the PDF data sheet for device specific package drawings
Skew within the DQS[x] and DQ[x] net classes directly reduces setup and hold margin and, thus, this skew must be controlled. The only way to practically match lengths on a PCB is to lengthen the shorter traces up to the length of the longest net in the net class and its associated clock. DQLMn is defined as DQ Longest Manhattan distance n, where n is the byte number. For a 16-bit interface, there are two DQLMs, DQLM0 and DQLM1.
It is not required, nor is it recommended, to match the lengths across all bytes. Length matching is only required within each byte.
Given the DQS[x] and DQ[x] pin locations on the device and the DDR3 memories, the maximum possible Manhattan distance can be determined given the placement. Figure 5-77 shows this distance for a two-load case. It is from this distance that the specifications on the lengths of the transmission lines for the data bus are determined. For DQS[x] and DQ[x] routing, these specifications are contained in Table 5-59.
|1||DQ0 nominal length(3)(4)||DQLM0||mils|
|2||DQ1 nominal length(3)(5)||DQLM1||mils|
|3||DQ2 nominal length||DQLM2||mils|
|4||DQ3 nominal length||DQLM3||mils|
|8||Center-to-center DQ[x] to other DDR3 trace spacing(8)(9)||4||w|
|9||Center-to-center DQ[x] to other DQ[x] trace spacing(8)(10)||3||w|
|10||DQS[x] center-to-center spacing(11)|
|11||DQS[x] center-to-center spacing to other net(8)||4||w|