Place a differential RC filter (R1, R2, C5) in front of the device to improve signal-to-noise performance of the signal path. Input noise with a frequency close to the ΔΣ modulator sampling frequency (typically 20MHz) is folded back into the low-frequency range by the modulator. The purpose of the RC filter at the input is to attenuate high-frequency noise below the desired noise level of the measurement. Design the input filter such that:

• The filter capacitance (C5) is a minimum of 10nF
• The cutoff frequency of the filter is at least one order of magnitude lower than the sampling frequency (f_CLKIN) of the ΔΣ modulator
• The dynamic input bias current does not generate a significant voltage drop across the DC impedances (R1, R2) relative to the common-mode input voltage range
• The impedances measured from the analog inputs are equal (R1 equals R2)

Place capacitors C6 and C7 to improve common-mode rejection at high frequencies (>1MHz) and to improve offset voltage performance. For best performance, verify C6 matches the value of C7 and that both capacitors are 10 to 20 times lower in value than C5. NP0-type capacitors offer low temperature drift and low voltage coefficients, and are preferred for common-mode filtering.

For most applications, the structure shown in Figure 8-2 achieves excellent performance.

Figure 8-2 Input Filter