SBASAJ9B June   2022  – December 2024 AMC22C12-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information 
    5. 5.5  Power Ratings
    6. 5.6  Insulation Specifications (Basic Isolation)
    7. 5.7  Safety-Related Certifications 
    8. 5.8  Safety Limiting Values 
    9. 5.9  Electrical Characteristics
    10. 5.10 Switching Characteristics 
    11. 5.11 Timing Diagrams
    12. 5.12 Insulation Characteristics Curves
    13. 5.13 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Analog Input
      2. 6.3.2 Reference Input
      3. 6.3.3 Isolation Channel Signal Transmission
      4. 6.3.4 Open-Drain Digital Output
        1. 6.3.4.1 Transparent Output Mode
        2. 6.3.4.2 Latch Output Mode
      5. 6.3.5 Power-Up and Power-Down Behavior
      6. 6.3.6 VDD1 Brownout and Power-Loss Behavior
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Overcurrent Detection
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
      2. 7.2.2 Overvoltage Detection
        1. 7.2.2.1 Design Requirements
        2. 7.2.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curves
    3. 7.3 Best Design Practices
    4. 7.4 Power Supply Recommendations
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
      2. 7.5.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Mechanical Data

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.9 Electrical Characteristics

minimum and maximum specifications apply from TA = –40°C to 125°C, VDD1 = 3.0 V to 25 V, VDD2 = 2.7 V to 5.5 V, VREF = 20 mV to 2.7 V(1), and VIN = –400 mV to 4 V(3); typical specifications are at TA = 25°C, VDD1 = 5 V, VDD2 = 3.3 V, and VREF = 250 mV (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUT
RIN Input resistance IN pin, 0 ≤ VIN ≤ 4 V 1 GΩ
IBIAS Input bias current IN pin, 0 ≤ VIN ≤ 4 V(4) 0.1 25 nA
IN pin, –400 mV ≤ VIN ≤ 0 V(5) –310 –0.5
CIN Input capacitance IN pin 4 pF
REFERENCE PIN
IREF Reference current REF to GND1, 20 mV < VREF ≤ 2.7 V 99 100 101 μA
VMSEL Mode selection threshold(2) VREF rising 500 550 600 mV
VREF falling 450 500 550
Mode selection threshold hysteresis 50 mV
COMPARATORS
VIT+ Positive-going trip threshold Cmp0 VREF + VHYS mV
EIT+ Positive-going trip threshold error Cmp0, (VIT+ – VREF – VHYS),
VREF = 20 mV, VHYS = 4 mV		 –2 2 mV
Cmp0, (VIT+ – VREF – VHYS),
VREF = 250 mV, VHYS = 4 mV		 –2 2
Cmp0, (VIT+ – VREF – VHYS),
VREF = 2 V, VHYS = 25 mV		 –5 5
VIT– Negative-going trip threshold Cmp0 VREF mV
EIT– Negative-going trip threshold error Cmp0, (VIT– – VREF), VREF = 20 mV –2.5 2.5
mV
Cmp0, (VIT– – VREF), VREF = 250 mV –2.5 2.5
Cmp0, (VIT– – VREF), VREF = 2 V –5 5
VIT– Negative-going trip threshold Cmp1 –VREF – VHYS mV
EIT– Negative-going trip threshold error Cmp1, (VIT– + VREF + VHYS),
VREF = 20 mV, VHYS = 4 mV		 –3 3
mV
Cmp1, (VIT– + VREF + VHYS),
VREF = 250 mV, VHYS = 4 mV		 –3 3
VIT+ Positive-going trip threshold Cmp1 –VREF mV
EIT+ Positive-going trip threshold error Cmp1, (VIT+ + VREF), VREF = 20 mV –3.5 3.5 mV
Cmp1, (VIT+ + VREF), VREF = 250 mV –3.5 3.5
VHYS Trip threshold hysteresis Cmp0 and Cmp1, (VIT+ – VIT–), VREF ≤ 450 mV 4 mV
Cmp0 only, (VIT+ – VIT–), VREF ≥ 600 mV 25
DIGITAL I/O
VIH High-level input voltage LATCH pin 0.7 x VDD2 VDD2 + 0.3 V
VIL Low-level input voltage LATCH pin –0.3 0.3 x VDD2 V
CIN Input capacitance LATCH pin 4 pF
VOL Low-level output voltage ISINK = 4 mA 80 250 mV
ILKG Open-drain output leakage current VDD2 = 5 V, VOUT = 5 V 5 100 nA
CMTI Common-mode transient immunity |VIN – VREF| ≥ 4 mV, RPULLUP = 10 kΩ 55 110 V/ns
POWER SUPPLY
VDD1UV VDD1 undervoltage detection threshold VDD1 rising 3 V
VDD1 falling 2.9
VDD1POR VDD1 power-on reset threshold VDD1 falling 2.3 V
VDD2UV VDD2 undervoltage detection threshold VDD2 rising 2.7 V
VDD2 falling 2.1
IDD1 High-side supply current 3.0V ≤ VDD1 ≤ 3.4V 4.0 mA
IDD1 High-side supply current 3.4V < VDD1 ≤ 25V 3.2 4.3 mA
IDD2 Low-side supply current 1.8 2.2 mA
(1) Reference voltages >1.6 V require VDD1 > VDD1MIN. See the Recommended Opertion Conditions table for details.
(2) The voltage level VREF determines if the device operates as window-comparator with positive and negative thresholds or as simple comparator with positive thresholds only. See the Reference Input section for more details.
(3) But not exceeding the maximum input voltage specified in the Recommended Opertion Conditions table.
(4) The typical value is measured at VIN = 0.4 V.
(5) The typical value is measured at VIN = –400 mV.