SWRS203B May 2017 – April 2020 AWR1642
Refer to the PDF data sheet for device specific package drawings
Table 5-1 describes the four rails from an external power supply block of the AWR1642 device.
|SUPPLY||DEVICE BLOCKS POWERED FROM THE SUPPLY||RELEVANT IOS IN THE DEVICE|
|1.8 V||Synthesizer and APLL VCOs, crystal oscillator, IF Amplifier stages, ADC, LVDS||Input: VIN_18VCO, VIN18CLK, VIN_18BB, VIOIN_18DIFF, VIOIN_18IO
LDO Output: VOUT_14SYNTH, VOUT_14APLL
|1.3 V (or 1 V in internal LDO bypass mode)||Power Amplifier, Low Noise Amplifier, Mixers and LO Distribution||Input: VIN_13RF2, VIN_13RF1
LDO Output: VOUT_PA
|3.3 V (or 1.8 V for 1.8 V I/O mode)||Digital I/Os||Input VIOIN|
|1.2 V||Core Digital and SRAMs||Input: VDDIN, VIN_SRAM|
The 1.3-V (1.0 V) and 1.8-V power supply ripple specifications mentioned in Table 5-2 are defined to meet a target spur level of –105 dBc (RF Pin = –15 dBm) at the RX. The spur and ripple levels have a dB-to-dB relationship, for example, a 1-dB increase in supply ripple leads to a ~1 dB increase in spur level. Values quoted are rms levels for a sinusoidal input applied at the specified frequency.