SWRS222B December 2018 – April 2020 AWR1843
Refer to the PDF data sheet for device specific package drawings
The AWR1843 requires external clock source (that is, a 40-MHz crystal) for initial boot and as a reference for an internal APLL hosted in the device. An external crystal is connected to the device pins. Figure 5-2 shows the crystal implementation.
The load capacitors, Cf1 and Cf2 in Figure 5-2, should be chosen such that Equation 1 is satisfied. CL in the equation is the load specified by the crystal manufacturer. All discrete components used to implement the oscillator circuit should be placed as close as possible to the associated oscillator CLKP and CLKM pins.
Table 5-5 lists the electrical characteristics of the clock crystal.
|fP||Parallel resonance crystal frequency||40||MHz|
|CL||Crystal load capacitance||5||8||12||pF|
|Temperature range||Expected temperature range of operation||–40||150||ºC|
|Frequency tolerance||Crystal frequency tolerance(1)(2)||–200||200||ppm|
External AC-coupled sine wave or DC-coupled square wave
Phase Noise referred to 40 MHz
|Phase Noise at 1 kHz||–132||dBc/Hz|
|Phase Noise at 10 kHz||–143||dBc/Hz|
|Phase Noise at 100 kHz||–152||dBc/Hz|
|Phase Noise at 1 MHz||–153||dBc/Hz|