SLUSA76B December   2010  – January 2015

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Typical Application Schematic
  5. 5 Revision History
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Voltage-Based Dynamic Power Management (VBUS-DPM)
      2. 8.3.2 CHG Pin Indication
      3. 8.3.3 CHG and PG LED Pull-Up Source
      4. 8.3.4 Power Good Indication (PG)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Down or Undervoltage Lockout (UVLO)
      2. 8.4.2 Operation Mode Detection and Transition
      3. 8.4.3 Sleep Mode
      4. 8.4.4 Load Mode
      5. 8.4.5 Charge Mode
        1. 8.4.5.1  Overvoltage Protection (OVP) - Continuously Monitored
        2. 8.4.5.2  Power Up
        3. 8.4.5.3  Battery Detect Routine
        4. 8.4.5.4  New Charge Cycle
        5. 8.4.5.5  BAT Output
        6. 8.4.5.6  Fast Charge Current (IOUT)
        7. 8.4.5.7  Termination
        8. 8.4.5.8  Timers
        9. 8.4.5.9  Battery Temperature Monitoring
        10. 8.4.5.10 Limited Power Charge Mode - TS Pin High
      6. 8.4.6 Suspend Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

11 Layout

11.1 Layout Guidelines

The minimum VBUS and BAT capacitors, CVBUS and CBAT, of 1 uF are required to be placed as close as possible between the respective pins and the IC ground pin. Higher bulk capacitance values and additional high frequency (< 0.1 uF) bypass capacitors are allowed. Next, the resistor on ISET, RISET, and on VDPM, RVDPM, should be placed as close as possible to the respective pins and the IC ground pin. The TS pullup resistor, RVTSB or RT1, can then be placed between the VTSB and TS pins. Optional capacitors up to 1.0 uF on TS, CTS, and VTSB, CVTSB, can be placed to minimize noise coupling.

11.2 Layout Example

bq24210-layout.pngFigure 16. Recommended Layout