SLUSBA1H October   2012  – August 2015

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Device Options
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Charge Profile
      2. 9.3.2  EN1 and EN2 Pins
      3. 9.3.3  External Settings: ISET, ILIM and VIN_DPM
      4. 9.3.4  BC1.2 D+/D- Detection
      5. 9.3.5  Transient Response
      6. 9.3.6  AnyBoot Battery Detection
      7. 9.3.7  Input Voltage Based DPM
      8. 9.3.8  Sleep Mode
      9. 9.3.9  Input Over-Voltage Protection
      10. 9.3.10 NTC Monitor
      11. 9.3.11 Production Test Mode
      12. 9.3.12 Safety Timer
      13. 9.3.13 Watchdog Timer
      14. 9.3.14 Fault Modes
      15. 9.3.15 Dynamic Power Path Management
    4. 9.4 Device Functional Modes
      1. 9.4.1 I2C Operation (Host Mode / Default Mode)
    5. 9.5 Programming
      1. 9.5.1 Serial Interface Description
        1. 9.5.1.1 F/S Mode Protocol
    6. 9.6 Register Maps
      1. 9.6.1 Register #1
      2. 9.6.2 Register #2
      3. 9.6.3 Register #3
      4. 9.6.4 Register #4
      5. 9.6.5 Register #5
      6. 9.6.6 Register #6
      7. 9.6.7 Register #7
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Inductor Selection
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
    3. 12.3 Thermal Considerations
  13. 13Device and Documentation Support
    1. 13.1 Related Links
    2. 13.2 Trademarks
    3. 13.3 Electrostatic Discharge Caution
    4. 13.4 Glossary
  14. 14Mechanical, Packaging, and Orderable Information
    1. 14.1 Package Summary

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Specifications

8.1 Absolute Maximum Ratings(1)

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
Pin Voltage Range (with respect to GND) IN –0.3 22 V
SW –0.7 12 V
BOOT –0.3 20 V
LDO,STAT, INT, /CHG, /PG, EN1, EN2, EN3, /CE, D+, D-, ILIM, ISET, VDPM, TS, SCL, SDA –0.3 7 V
SYS, BAT –0.3 5 V
BOOT relative to SW –0.3 7 V
Output Current (Continuous) IN 2 A
SYS, BAT 4
Output Sink Current STAT, /CHG, /PG 5 mA
Operating free-air temperature range –40 85 °C
Junction temperature, TJ –40 125 °C
Input Power IN 15 W
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

8.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±2000 V
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

8.3 Recommended Operating Conditions

All voltages are with respect to PGND if not specified. Currents are positive into, negative out of the specified terminal. Consult Packaging Section of the data book for thermal limitations and considerations of packages
MIN MAX UNIT
VIN IN voltage range 4.35 18(1) V
IN operating voltage range 4.35 10.5
IIN Input current 2 A
ICHG Current in charge mode, BAT 2 A
IDISCHG Current in discharge mode, BAT 4 A
RISET Charge current programming resistor range 75 Ω
RILIM Input current limit programming resistor range 105 Ω
PIN Input Power 12 W
TJ Operating junction temperature range 0 125 °C
(1) The inherent switching noise voltage spikes should not exceed the absolute maximum rating on either the BOOT or SW pins. Small routing loops for the power nets in layout minimize switching noise.

8.4 Thermal Information

THERMAL METRIC(1) YFF
(30 PINS)		 RGE
(24 PINS)		 UNIT
RθJA Junction-to-ambient thermal resistance 76.5 32.9 °C/W
RθJCtop Junction-to-case (top) thermal resistance 0.2 32.8 °C/W
RθJB Junction-to-board thermal resistance 44 10.6 °C/W
ψJT Junction-to-top characterization parameter 1.6 0.3 °C/W
ψJB Junction-to-board characterization parameter 43.4 10.7 °C/W
RθJCbot Junction-to-case (bottom) thermal resistance N/A 2.3 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

8.5 Electrical Characteristics

VUVLO < VIN < VOVP and VIN > VBAT+VSLP, TJ = 0ºC-125°C and TJ = 25°C for typical values (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT CURRENTS
IIN Supply current from IN VDPM < VIN < VOVP AND VIN > VBAT+VSLP PWM switching, CE Enable 13 mA
VDPM < VIN < VOVP AND VIN > VBAT+VSLP PWM switching, CE Disable 5
VIN= 5.5V, 0°C< TJ < 85°C, High-Z Mode 170 225 μA
IBAT Battery discharge current in high impedance mode, (BAT, SW, SYS) 0°C< TJ < 85°C, VBAT = 4.2 V,
VIN = 0V or 5V, High-Z Mode		 16 22 μA
Battery discharge current in SYSOFF mode 0°C< TJ < 85°C, VBAT = 4.2 V,
VIN < UVLO, SYSOFF Mode		 1
POWER-PATH MANAGEMENT
VSYSREG System Regulation Voltage MINSYS stage (no DPM or DPPM) –1% 3.52 1% V
MINSYS stage (DPM or DPPM active) –1.50% VMINSYS
–200mV		 1.50%
BATREG stage VBAT
+ ICHG Ron
SYSREG stage VBATREG
+2.1%		 VBATREG
+3.1%		 VBATREG
+4.1%
VSPLM Enter supplement mode voltage threshold VBAT = 3.6V VBAT –
40mV		 V
ISPLM Exit supplement mode current threshold VBAT = 3.6V 20 mA
tDGL(SC1) Deglitch Time, OUT Short Circuit during Discharge or Supplement Mode Measured from (VBAT – VSYS) = 300 mV 740 μs
tREC(SC1) Recovery Time, OUT Short Circuit during Discharge or Supplement Mode 64 ms
BATTERY CHARGER
RON(BAT-SYS) Internal battery charger MOSFET on-resistance Measured from BAT to SYS, VBAT = 4.2V (WCSP) 20 30 mΩ
Measured from BAT to SYS, VBAT = 4.2V (QFN) 30 40
VBATREG I2C host mode Operating in voltage regulation, Programmable Range 3.5 4.44 V
SA mode or I2C default mode 4.2
Voltage Regulation Accuracy TJ = 25°C –0.5% 0.5%
TJ = 0°C to 125°C –0.75% 0.75%
ICHG Fast Charge Current Range VLOWV ≤ VBAT < VBAT(REG) 500 2000 mA
Fast Charge Current Accuracy I2C mode –7% 7%
ICHG-LOW Low Charge Current Setting Set via I2C 297 330 363 mA
KISET Programmable Fast Charge Current Factor bq24250 bq24251 bq24253 Inline1_ICHG_lusba1.gif 232.5 250 267.5 AΩ
VISET Maximum ISET pin voltage (in regulation) 0.42 V
RISET-SHORT Short circuit resistance threshold 45 55 75 Ω
VLOWV Pre-charge to fast charge threshold Rising 2.9 3 3.1 V
Hysteresis for VLOWV Battery voltage falling 100 mV
IPRECHG Pr-charge current (VBATUVLO < VBAT < VLOWV) Ipre-chg is a precentile of the external fast charge settings. 8 10 12 %
tDGL(LOWV) Deglitch time for pre-charge to fast charge transition 32 ms
VBAT_UVLO Battery Under voltage lockout threshold VBAT rising 2.37 2.5 2.63 V
Battery UVLO hysteresis 200 mV
VBATSHRT Trickle charge to pre-charge threshold 1.9 2 2.1 V
Hysteresis for VBATSHRT Battery voltage falling 100 mV
IBATSHRT Trickle charge mode charge current (VBAT < VBATSHRT) 25 35 50 mA
tDGL(BATSHRT) Deglitch time for trickle charge to pre-charge transition 256 us
ITERM Termination Current Threshold Termination current on SA only 10 %ICHG
Termination Current Threshold Tolerance –10% 10%
tDGL(TERM) Deglitch time for charge termination Both rising and falling, 2-mV over-drive, tRISE, tFALL = 100 ns 64 ms
VRCH Recharge threshold voltage Below VBATREG 70 115 160 mV
tDGL(RCH) Deglitch time VBAT falling below VRCH, tFALL = 100 ns 32 ms
BATTERY DETECTION
VBATREG_HI Battery Detection High Regulation Voltage Same as VBATREG VBATREG V
VBATREG_LO Battery Detection Low Regulation Voltage 360 mV offset from VBATREG VBATREG
–480mV		 V
VBATDET Hi Battery detection comparator VBATREG = VBATREG_HI VBATREG
–120mV		 V
VBATDET LO Battery detection comparator VBATREG = VBATREG_LO VBATREG
+120mV		 V
IDETECT Battery Detection Current Sink Always on during battery detection 7.5 mA
tDETECT Battery detection time For both VBATREG_HI and VBATREG_LO 32 ms
Tsafe Safety Timer Accuracy –10% +10%
INPUT PROTECTION
IIN Input current limiting IIN_LIMIT = 100 mA 90 95 100 mA
IIN_LIMIT = 150 mA 135 142.5 150
IIN_LIMIT = 500 mA 450 475 500
IIN_LIMIT = 900 mA 810 860 910
IIN_LIMIT = 1500 mA 1400 1475 1550
IIN_LIMIT = 2000 mA 1850 1950 2050
IIN_LIMIT = External bq24250 bq24251 bq24253 inline2_ILIM_lusba1.gif
ILIM Maximum input current limit programmable range for IN input 500 2000 mA
KILIM Maximum input current factor for IN input ILIM = 500 mA to 2.0 A 240 270 300 AΩ
VILIM Maximum ILIM pin voltage (in regulation) 0.42 V
IIN /IILIM Ratio between input current and the ILIM pin current in external control or stand alone mode External ILIM control or stand alone 540 A/A
RILIM-SHORT Short circuit resistance threshold 55 75 Ω
VIN_DPM VIN_DPM threshold range SA mode 4.2 10 V
I2C mode 4.2 4.76
VIN_DPM threshold for USB Input in SA mode USB100, USB150, USB500, USB900, current limit selected. Also I2C register default. 4.27 4.36 4.45
VIN_DPM threshold with adaptor current limit and VDPM shorted to GND Must set to external resistor settings via the EN1/EN2 pins or the I2C register interface. VIN_DPM
.
–2%		 VIN_DPM VIN_DPM
.
+2%
VIN_DPM threshold Accuracy Both I2C and SA mode –2% 2%
VREF_DPM DPM regulation voltage External resistor setting only 1.15 1.2 1.25 V
VDPM_SHRT VIN_DPM short threshold If VDPM is shorted to ground, VIN_DPM threshold will use internal default value 0.3 V
VUVLO IC active threshold voltage VIN rising 3.15 3.35 3.5 V
IC active hysteresis VIN falling from above VUVLO 175 mV
VSLP Sleep-mode entry threshold, VIN-VBAT 2.0 V ≤ VBAT ≤ VBATREG, VIN falling 0 50 100 mV
Sleep-mode exit hysteresis, VIN-VBAT 2.0 V ≤ VBAT ≤ VBATREG 40 100 160 mV
tDGL(SLP) Deglitch time for IN rising above VIN+VSLP_EXIT Rising voltage, 2-mV over drive, tRISE = 100 ns 32 ms
VOVP Input supply OVP threshold voltage IN rising Input OVP
–200mV		 Input OVP Input OVP
+200mV		 V
VOVP hysteresis IN falling from VOVP 100 mV
tDGL(OVP) Deglitch time for IN Rising above VOVP IN rising voltage, tRISE = 100 ns 32 ms
VBOVP Battery OVP threshold voltage VBAT threshold over VBATREG to turn off charger during charge 102.5 105 107.5 % VBATREG
VBOVP hysteresis Lower limit for VBAT falling from above VBOVP 1 % VBATREG
tDGL(BOVP) BOVP Deglitch Battery entering/exiting BOVP 1 ms
PWM CONVERTER
RON(BLK) Internal blocking MOSFET on-resistance Measured from IN to PMID (WCSP & QFN) 60 100 mΩ
RON(HS) Internal high-side MOSFET on-resistance Measured from PMID to SW (WCSP & QFN) 100 150 mΩ
RON(LS) Internal low-side MOSFET on-resistance Measured from SW to PGND (WCSP & QFN) 110 165 mΩ
ICbC Cycle-by-cycle current limit VSYS shorted 2.6 3.2 3.8 A
fOSC Oscillator frequency 2.7 3 3.3 MHz
DMAX Maximum duty cycle 95%
DMIN Minimum duty cycle 0%
TSHTDWN Thermal trip 150 °C
Thermal hysteresis 10
TREG Thermal regulation threshold Charge current begins to cut off 125
LDO (LINEAR DROPOUT)
VLDO LDO Output Voltage bq24250 VIN = 5.5 V, ILDO = 0 to 50 mA 4.65 4.85 5.04 V
bq24251 and bq24253 4.65 4.95 5.25
ILDO Maximum LDO Output Current 50 mA
VDO LDO Dropout Voltage (VIN – VLDO) VIN = 5.0 V, ILDO = 50 mA 200 300 mV
BATTERY-PACK NTC MONITOR (1)
VHOT High temperature threshold VTS falling 29.6 30 30.4 % VLDO
VHYS(HOT) Hysteresis on high threshold VTS rising 1
VWARM Warm temperature threshold VTS falling 37.9 38.3 38.7
VHYS(WARM) Hysteresis on warm temperature threshold VTS rising 1
VCOOL Cool temperature threshold VTS rising 56.1 56.5 56.9
VHSY(COOL) Hysteresis on cool temperature threshold VTS falling 1
VCOLD Low temperature threshold VTS rising 59.6 60 60.4
VHYS(COLD) Hysteresis on low threshold VTS falling 1
VFRZ Freeze temperature threshold VTS rising 62 62.5 63
VHYS(FRZ) Hysteresis on freeze threshold VTS falling 1
VTS_DIS TS disable threshold 70 73
tDGL(TS) Deglitch time on TS change 32 ms
INPUTS (EN1, EN2, EN2, CE, CE1, CE2, BATREG, SCL, SDA, DBP)
VIH Input high threshold 1 V
VIL Input low threshold 0.4 V
STATUS OUTPUTS (CHG, PG, STAT, INT, BATRDY)
VOL Low-level output saturation voltage IO = 5 mA, sink current 0.4 V
IIH High-level leakage current Hi-Z and 5V applies 1 µA
TIMERS
tSAFETY 45 min safety timer 2700 s
6 hr safety timer 21600
9 hr safety timer 32400
tWATCH-DOG Watch dog timer 50 s
D+/D– DETECTION
IDP_SRC D+ current source for DCD DCD 7 13 µA
RDM_DWN D– pull-down resistance for DCD DCD 14.25 24.8 kΩ
VDP_LOW D+ low comparator threshold for DCD DCD 0.85 0.9 0.95 V
VDP_SRC D+ source voltage for Primary Detection Primary Detection 0.5 0.6 0.7 V
IDP_SRC_PD D+ source voltage output current for Primary Detection Primary Detection 200 µA
IDM_SINK D– sink current for Primary Detection Primary Detection 50 100 150 µA
VDAT_REF Primary Detection threshold Primary Detection 250 325 400 mV
VLGC Primary Detection threshold Primary Detection 0.85 0.9 0.95 V
VDM_SRC D- source voltage for Secondary Detection Secondary Detection 0.5 0.6 0.7 V
IDM_SRC_PD D- source voltage output current for Secondary Detection Secondary Detection 200 µA
IDP_SINK D+ sink current for Secondary Detection Secondary Detection 50 100 150 µA
VDAT_REF Secondary Detection threshold Secondary Detection 250 325 400 mV
VATT_LO Apple/TomTom detection low threshold Apple/TomTom Detection 1.8 1.85 1.975 V
VATT_HI Apple/TomTom detection high threshold Apple/TomTom Detection 3.2 3.5 3.8 V
CI Input Capacitance D– , switch open 4.5 pF
D+, switch open 4.5
ID_LKG Leakage Current into D+/D– D–, switch open –1 1 µA
D+, switch open –1 1

8.6 Typical Characteristics

bq24250 bq24251 bq24253 bq2425x_batt_det_lusba1a.gif
VBAT = 3.8 V VIN = 5 V VREG = 4.2 V
ICHG = 0.5 A ILIM = 1 A
Figure 1. Battery Detection
bq24250 bq24251 bq24253 C001_SLUSBA1.gif
ICHG = 2 A VIN = 5 V VREG = 4.2 V
Figure 3. Efficiency vs Battery Voltage
bq24250 bq24251 bq24253 C002_SLUSBA1.gif
VREG = 4.2 V
Figure 5. Efficiency vs Output Current
bq24250 bq24251 bq24253 C007_SLUSBA1.gif
VIN = 0 V SYSOFF = 0 Charge Enabled
BAT & SYS are Shorted
Figure 7. BAT IQ, SYSOFF = 0
bq24250 bq24251 bq24253 C008_SLUSBA1.gif
Charge EN and DIS No Battery and System
Figure 9. Input IQ With Charge DIS and EN
bq24250 bq24251 bq24253 C011_SLUSBA1.gif
VBAT = 3.3 V VIN = 5 V VREG = 4.2 V
ILIM = 2 A
Figure 11. ICHG Accuracy with Internal Settings, VBAT = 3.3 V
bq24250 bq24251 bq24253 C013_SLUSBA1.png
Figure 13. Ratio Between VILIM and IIN With External ILIM Control
bq24250 bq24251 bq24253 bq2425x_batt_removal_lusba1a.gif
VBAT = 3.8 V VIN = 6 V VREG = 4.2 V
ICHG = 1 A ILIM = 1 A
Figure 2. Battery Removal
bq24250 bq24251 bq24253 C004_SLUSBA1.gif
VIN = 5 V No Battery ILIM = 2 A
VREG = 4.2 V Charge Disable
Figure 4. System Voltage Regulation vs Load Current
bq24250 bq24251 bq24253 C003_SLUSBA1.gif
VREG = 3.6 V
Figure 6. Efficiency vs Output Current
bq24250 bq24251 bq24253 C010_SLUSBA1.gif
VIN = 0 V SYSOFF = 1 Charge Enabled
BAT & SYS are Shorted
Figure 8. BAT IQ, SYSOFF = 1
bq24250 bq24251 bq24253 C009_SLUSBA1.gif
Charge EN Hi-Z EN
Figure 10. Input IQ with Charge Enable and Hi-Z
bq24250 bq24251 bq24253 C012_SLUSBA1.gif
VBAT = 3.8 V VIN = 5 V VREG = 4.2 V
ILIM = 2 A
Figure 12. ICHG Accuracy with Internal Settings, VBAT = 3.8 V
bq24250 bq24251 bq24253 Input_OVP_Event2_SLUSBA1.gif
VBAT = 3.9 V VOVP = 10.5 V
ICHG = 1 A ILIM = 1 A
Figure 14. Input OVP Event with INT