SLUSA49C April   2010  – June 2015

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Battery Voltage Regulation
      2. 8.3.2  Battery Current Regulation
      3. 8.3.3  Input Adapter Current Regulation
      4. 8.3.4  Precharge
      5. 8.3.5  Charge Termination, Recharge, and Safety Timer
      6. 8.3.6  Power Up
      7. 8.3.7  Enable and Disable Charging
      8. 8.3.8  System Power Selector
      9. 8.3.9  Automatic Internal Soft-Start Charger Current
      10. 8.3.10 Converter Operation
      11. 8.3.11 Synchronous and Nonsynchronous Operation
      12. 8.3.12 Cycle-by-Cycle Charge Undercurrent Protection
      13. 8.3.13 Input Overvoltage Protection (ACOV)
      14. 8.3.14 Input Undervoltage Lockout (UVLO)
      15. 8.3.15 Battery Overvoltage Protection
      16. 8.3.16 Cycle-by-Cycle Charge Overcurrent Protection
      17. 8.3.17 Thermal Shutdown Protection
      18. 8.3.18 Temperature Qualification and JEITA Guideline
      19. 8.3.19 Timer Fault Recovery
      20. 8.3.20 PG Output
      21. 8.3.21 CE (Charge Enable)
      22. 8.3.22 Charge Status Outputs
      23. 8.3.23 Battery Detection
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Inductor Selection
        2. 9.2.2.2 Input Capacitor
        3. 9.2.2.3 Output Capacitor
        4. 9.2.2.4 Power MOSFET Selection
        5. 9.2.2.5 Input Filter Design
        6. 9.2.2.6 Inductor, Capacitor, and Sense Resistor Selection Guidelines
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Examples
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Pin Configuration and Functions

RGE Package
24-Pin VQFN
Top View
bq24616 po_lusa49.gif

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
ACDRV 3 O AC adapter-to-system MOSFET driver output. Connect through a 1-kΩ resistor to the gate of the ACFET P-channel power MOSFET and the reverse-conduction-blocking P-channel power MOSFET. The internal gate drive is asymmetrical, allowing a quick turnoff and slow turnon, in addition to the internal break-before-make logic with respect to BATDRV. If needed, an optional capacitor from gate to source of the ACFET is used to slow down the ON and OFF times.
ACN 1 I Adapter current-sense resistor, negative input. A 0.1-μF ceramic capacitor is placed from ACN to ACP to provide differential-mode filtering. An optional 0.1-μF ceramic capacitor is placed from the ACN pin to GND for common-mode filtering.
ACP 2 I Adapter current-sense resistor, positive input. A 0.1-μF ceramic capacitor is placed from ACN to ACP to provide differential-mode filtering. A 0.1-μF ceramic capacitor is placed from the ACP pin to GND for common-mode filtering.
ACSET 16 I Adapter current-set input. The voltage on the ACSET pin programs the input current-regulation set-point during dynamic power management (DPM)
BATDRV 23 O Battery-to-system MOSFET driver output. Gate drive for the battery-to-system load BAT PMOS power FET to isolate the system from the battery to prevent current flow from the system to the battery, while allowing a low-impedance path from battery to system. Connect this pin through a 1-kΩ resistor to the gate of the input BAT P-channel MOSFET. Connect the source of the FET to the system load-voltage node. Connect the drain of the FET to the battery pack positive terminal. The internal gate drive is asymmetrical to allow a quick turnoff and slow turnon, in addition to the internal break-before-make logic with respect to ACDRV. If needed, an optional capacitor from gate to source of the BATFET is used to slow down the ON and OFF times.
BTST 22 I PWM high-side driver positive supply. Connect the 0.1-μF bootstrap capacitor from PH to BTST, and a bootstrap Schottky diode from REGN to BTST.
CE 4 I Charge-enable active-HIGH logic input. HI enables charge. LO disables charge. It has an internal 1-MΩ pulldown resistor.
GND 17 Low-current sensitive analog/digital ground. On PCB layout, connect with thermal underneath the IC.
HIDRV 21 O PWM high-side driver output. Connect to the gate of the high-side power MOSFET with a short trace.
ISET1 11 I Fast-charge current-set input. The voltage on the ISET1 pin programs the fast-charge current regulation set-point. To avoid early termination during the VT1 and VT2 range, fast-charge current must be higher than 2 times the termination current.
ISET2 15 I Precharge and termination current-set input. The voltage of ISET2 pin programs the precharge current regulation set-point and termination current trigger point.
LODRV 19 O PWM low-side driver output. Connect to the gate of the low-side power MOSFET with a short trace.
PG 8 O Open-drain power good status output. Active-LOW when IC has a valid VCC (not in UVLO or ACOV or SLEEP mode). Active-HIGH when IC has an invalid VCC. PG can be used to drive an LED or communicate with a host processor.
PH 20 I PWM high-side driver negative supply. Connect to the phase-switching node (junction of the low-side power MOSFET drain, high-side power MOSFET source, and output inductor).
REGN 18 O PWM low-side driver positive 6-V supply output. Connect a 1-μF ceramic capacitor from REGN to the GND pin, close to the IC. Use for low-side driver and high-side driver bootstrap voltage by connecting a small-signal Schottky diode from REGN to BTST.
SRN 13 I/O Charge current-sense resistor, negative input. A 0.1-μF ceramic capacitor is placed from SRN to SRP to provide differential-mode filtering. An optional 0.1-μF ceramic capacitor is placed from the SRN pin to GND for common-mode filtering.
SRP 14 I/O Charge current-sense resistor, positive input. A 0.1-μF ceramic capacitor is placed from SRN to SRP to provide differential-mode filtering. A 0.1-μF ceramic capacitor is placed from the SRP pin to GND for common-mode filtering.
STAT1 5 O Open-drain charge-status pin to indicate various charger operations (see Table 2).
STAT2 9 O Open-drain charge-status pin to indicate various charger operations (see Table 2).
TS 6 I Temperature qualification voltage input for battery pack negative-temperature-coefficient thermistor. Program the hot and cold temperature window with a resistor-divider from VREF to TS to GND. (see Figure 14).
TTC 7 I Fast-charge safety timer and termination control. Connect a capacitor from this node to GND to set the timer. When this input is LOW, the fast-charge timer and termination are disabled. When this input is HIGH, the fast-charge timer is disabled, but termination is allowed.
VCC 24 I IC power positive supply. Connect through a 10-Ω resistor to the common-source (diode-OR) point: source of high-side P-channel MOSFET and source of reverse-blocking power P-channel MOSFET. Place a 1-μF ceramic capacitor from VCC to GND pin close to the IC.
VFB 12 I Output voltage analog feedback adjustment. Connect the output of a resistive voltage divider from the battery terminals to this node to adjust the output battery regulation voltage.
VREF 10 O 3.3-V regulated voltage output. Place a 1-μF ceramic capacitor from VREF to GND pin close to the IC. This voltage could be used for programming of voltage and current regulation and for programming the TS threshold.
Thermal Pad — — Exposed pad beneath the IC. Always solder the thermal pad to the board, and have vias on the thermal pad plane star-connecting to GND and to the ground plane for a high-current power converter. It also serves as a thermal pad to dissipate the heat.