SLUSA44A March   2010  – July 2015


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Output Voltage Regulation
      2. 7.3.2  Output Current Regulation
      3. 7.3.3  Power Up
      4. 7.3.4  Enable and Disable Charging
      5. 7.3.5  Automatic Internal Soft-Start Charger Current
      6. 7.3.6  Converter Operation
      7. 7.3.7  Synchronous and Nonsynchronous Operation
      8. 7.3.8  Input Overvoltage Protection (ACOV)
      9. 7.3.9  Output Overvoltage Protection
      10. 7.3.10 Cycle-by-Cycle Charge Overcurrent Protection
      11. 7.3.11 Thermal Shutdown Protection
      12. 7.3.12 Temperature Qualification
      13. 7.3.13 CE (Charge Enable)
      14. 7.3.14 PG Output
      15. 7.3.15 Charge Status Outputs
    4. 7.4 Device Functional Modes
      1. 7.4.1 Constant Current Mode
      2. 7.4.2 Constant Voltage Mode
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. Inductor Selection
        2. Input Capacitor
        3. Output Capacitor
        4. Power MOSFETs Selection
        5. Input Filter Design
        6. Inductor, Capacitor, and Sense Resistor Selection Guidelines
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10 Layout

10.1 Layout Guidelines

The switching node rise and fall times should be minimized for minimum switching loss. Proper layout of the components to minimize high frequency current path loop (see Figure 15) is important to prevent electrical and magnetic field radiation and high frequency resonant problems. Here is a PCB layout priority list for proper layout. Layout PCB according to this specific order is essential.

  1. Place the input capacitor as close as possible to switching MOSFET supply and ground connections and use the shortest copper trace connection. These parts must be placed on the same layer of PCB instead of on different layers and using vias to make this connection.
  2. The IC must be placed close to the switching MOSFET gate terminals and keep the gate drive signal traces short for a clean MOSFET drive. The IC can be placed on the other side of the PCB of switching MOSFETs.
  3. Place the inductor input terminal to switching MOSFET output terminal as close as possible. Minimize the copper area of this trace to lower electrical and magnetic field radiation but make the trace wide enough to carry the charging current. Do not use multiple layers in parallel for this connection. Minimize parasitic capacitance from this area to any other trace or plane.
  4. The charging current sensing resistor must be placed right next to the inductor output. Route the sense leads connected across the sensing resistor back to the IC in same layer, close to each other (minimize loop area) and do not route the sense leads through a high-current path (see Figure 15 for Kelvin connection for best current accuracy). Place decoupling capacitor on these traces next to the IC.
  5. Place the output capacitor next to the sensing resistor output and ground.
  6. Output capacitor ground connections must be tied to the same copper that connects to the input capacitor ground before connecting to system ground.
  7. Route analog ground separately from power ground and use single ground connection to tie charger power ground to charger analog ground. Just beneath the IC, use analog ground copper pour, but avoid power pins to reduce inductive and capacitive noise coupling. Connect analog ground to GND pin using thermal pad as the single ground connection point to connect analog ground and power ground together, or use a 0-Ω resistor to tie analog ground to power ground (thermal pad must tie to analog ground in this case). A star-connection under thermal pad is highly recommended.
  8. It is critical to solder the exposed thermal pad on the backside of the IC package to the PCB ground. Ensure that there are sufficient thermal vias directly under the IC, connecting to the ground plane on the other layers.
  9. Decoupling capacitors must be placed next to the IC pins and make trace connection as short as possible.
  10. All via size and number should be enough for a given current path.

Refer to the EVM design (SLUU410) for the recommended component placement with trace and via locations.

For the QFN information, refer to Quad Flatpack No-Lead Logic Packages (SCBA017) and QFN/SON PCB Attachment Application Report (SLUA271).

10.2 Layout Examples

bq24640 hiz_cur_path_lusa44.gifFigure 15. High-Frequency Current Path
bq24640 PCB_layout_lusa44.gifFigure 16. Sensing Resistor PCB Layout