SLUSCP1A August   2016  – August 2016

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Demodulator
      2. 7.3.2 PWM Control
        1. 7.3.2.1 PWM_CTRL Input
        2. 7.3.2.2 PWM1, PWM2
        3. 7.3.2.3 Self-Switching
        4. 7.3.2.4 Duty Cycle Adjustment
      3. 7.3.3 Current Sense Amplifier
      4. 7.3.4 Voltage Regulator
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power Transfer
        1. 7.4.1.1 Dynamic Power Limiting™
      2. 7.4.2 Communication
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Capacitor Selection
        2. 8.2.2.2 Current Monitoring Requirements
        3. 8.2.2.3 Input Regulation
        4. 8.2.2.4 System Input Power Requirements
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Layout Notes
    2. 10.2 Layout Examples
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

RHB Package
32-Pin QFN
Top View

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
BOOT1 25 I/O Positive supply rail for the high-side gate driver. Connect a 0.1-µF ceramic capacitor between the BOOT1 and SW1 pins.
BOOT2 16 I/O Positive supply rail for the high-side gate driver. Connect a 0.1-µF ceramic capacitor between the BOOT2 and SW2 pins.
BP3 4 O LDO output. Tie with 2.2-µF capacitor to GND. For use by bq500511A only.
CLK_OUT 9 O Internal oscillator clock out signal.
CSN 29 I Current sense amplifier negative input.
CSO 31 O Current sense amplifier output. For use by bq500511A only.
CSP 30 I Current sense amplifier positive input. Connect current sense resistor as close as possible to this pin. This also serves as the quiet node for power supply input.
DMIN1 11 I Modulated signal from coil for DEMOD CHAN1.
DMIN2 12 I Modulated signal from coil for DEMOD CHAN2.
DMOUT1 8 O Demodulated 2-kHz signal from CHAN1. For use by bq500511A only.
DMOUT2 7 O Demodulated 2-kHz signal from CHAN2. For use by bq500511A only.
EN 3 I Enable pin with a weak internal pull-down. Float or pull below 1.5 V to disable gate driver, demodulation and current sense. Pull above 2.2 V to enable gate driver. Used by bq500511A to enter and leave standby mode for the transmitter.
GND 5 – Signal ground for the ground-referenced logic. All signal level circuits should be referenced to this pin unless otherwise noted.
GND 6 – Signal ground for the ground-referenced logic. All signal level circuits should be referenced to this pin unless otherwise noted.
GND 13 – Signal ground for the ground-referenced logic. All signal level circuits should be referenced to this pin unless otherwise noted.
MODE 10 I MODE pin with a weak internal pull-down. Float, or pull below 1.5 V to enable frequency control of the internally generated PWM signal. Pull above 2.2 V to enable pulse width control of the internally generated PWM signal. Used by bq500511A to select the control method for power control
PGND 20 – Power ground for the ground-referenced power stage. Connect to GND.
PGND 21 – Power ground for the ground-referenced power stage. Connect to GND.
PGND 22 – Power ground for the ground-referenced power stage. Connect to GND.
PVIN1 27 I DC input voltage for half-bridge MOSFET. Bypass with 22-µF ceramic capacitor to GND.
PVIN1 28 I DC input voltage for half-bridge MOSFET. Bypass with 22-µF ceramic capacitor to GND.
PVIN2 14 I DC input voltage for half-bridge MOSFET. Bypass with 22-µF ceramic capacitor to GND.
PVIN2 15 I DC input voltage for half-bridge MOSFET. Bypass with 22-µF ceramic capacitor to GND.
PWM_CTRL 2 I PWM_CTRL pin with a weak internal pull-down. Controlled by bq500511A (SLUSCN3) for system power delivery control.
PWM1/CLK_IN 1 I PWM1/CLK_IN pin with a weak internal pull-down. Controlled by bq500511A (SLUSCN3) for system power delivery control.
PWM2/UP_DN 32 I PWM2/UP_DN pin with a weak internal pull-down. Controlled by bq500511A (SLUSCN3) for system power delivery control.
SW1 23 O Switch node of the half-bridge MOSFETs. Connect to TX coil.
SW1 24 O Switch node of the half-bridge MOSFETs. Connect to TX coil.
SW1 26 O Switch node of the half-bridge MOSFETs. Connect to TX coil.
SW2 17 O Switch node of the half-bridge MOSFETs. Connect to resonant capacitor.
SW2 18 O Switch node of the half-bridge MOSFETs. Connect to resonant capacitor.
SW2 19 O Switch node of the half-bridge MOSFETs. Connect to resonant capacitor.