The BQ769142 device supports a random connection
sequence of cells to the device during pack manufacturing. For example, cell-10 in a
14-cell
stack might be first connected at the input terminals leading to pins VC10 and VC9,
then cell-4 may next be connected at the input terminals leading to pins VC4 and
VC3, and so on. It is not necessary to connect the negative terminal of cell-1 first
at VC0. As another example, consider a cell stack that is already assembled and
cells already interconnected to each other, then the stack is connected to the PCB
through a connector, which is plugged or soldered to the PCB. In this case, the
sequence order in which the connections are made to the PCB can be random in time,
they do not need to be controlled in a certain sequence.
There are, however, some restrictions to how the cells are connected during
manufacturing:
- To avoid misunderstanding, note that the cells in
a stack cannot be randomly connected to any VC
pin on the device, such as the lowest cell (cell-1) connected to
VC13A,
while the top cell
(cell-14)
is connected to VC4, and so on. It is important that the cells in the stack
be connected in ascending pin order, with the lowest cell (cell-1) connected
between VC1 and VC0, the next higher voltage cell (cell-2) connected between
VC2 and VC1, and so on.
- The random cell connection support is possible
due to high voltage tolerance on pins
VC1–VC14.
Note: VC0 has a lower voltage
tolerance. This is because VC0 should be connected through the
series-cell input resistor to the VSS pin on the PCB, before any cells
are attached to the PCB. Thus, the VC0 pin voltage is expected to remain
close to the VSS pin voltage during cell attach. If VC0 is not connected
through the series resistor to VSS on the PCB, then cells cannot be
connected in random
sequence.
- Each of the
VC1–VC14
pins includes a diode between the pin and the adjacent lower cell input pin
(that is, between
VC14
and
VC13A,
between VC9 and VC8, and so on), which is reverse biased in normal
operation. This means an upper cell input pin should not be driven to a low
voltage while a lower cell input pin is driven to a higher voltage, since
this would forward bias these diodes. During cell attach, the cell input
terminals should generally be floating before they are connected to the
appropriate cell. It is expected that transient current will flow briefly
when each cell is attached, but the cell voltages will quickly stabilize to
a state without DC current flowing through the diodes. However, if a large
capacitance is included between a cell input pin and another terminal (such
as VSS or another cell input pin), the transient current may become
excessive and lead to device heating. Therefore, it is recommended to limit
capacitances applied at each cell input pin to the values recommended in the
specifications.