SCHS463 May   2025 CD3268A , CD3269A

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
  7. 6 Parameter Measurement Information
    1. 6.1 eN-MIC Microphone Integrated Noise Measurement
    2. 6.2 Current Measurements
    3. 6.3 MICPWR Output Voltage Measurement
    4. 6.4 Tone Mode Threshold Measurements
    5. 6.5 Impedance Measurements
    6. 6.6 Tone Mode Output Measurements
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Tone Mode Start-up Timing
      2. 7.3.2 Authentication
      3. 7.3.3 Shunt Regulator
      4. 7.3.4 Power-on-reset
    4. 7.4 Device Functional Modes
      1. 7.4.1 Button Mode
      2. 7.4.2 Tone Mode
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Third-Party Products Disclaimer
      2. 9.1.2 Development Support
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.4 Power-on-reset

The CD326x has an internal power-on-reset (POR) circuit that holds all internal logic in a predetermined reset state until the supply voltage reaches a valid operating level and all internal nodes have stabilized. Figure 7-3 illustrates POR operation.

While the MIC pin is below VLVALID (200mV typical), POR is in an indeterminate state. When the supply voltage on the MIC pin is greater than VLVALID, the POR circuit asserts low until the supply rises to VPOR-RISE (1.2V typical). When the supply reaches VPOR-RISE, the POR function enters a valid operating supply state, and the POR signal remains asserted low for a predetermined delay tDPOR (1ms typical).

The POR function remains in the valid operating supply state until the supply voltage on the MIC pin falls below VPOR-FALL (0.8V typical). Upon falling below this threshold, the POR circuit immediately asserts the POR signal and enters the original low-supply state until a valid operating supply voltage is supplied. When the POR circuit recognizes a low-supply voltage during tDPOR, the circuit immediately resets the delay timer, maintains the asserted POR signal, and enters the low-supply state. After a valid operating supply voltage is reached again, the POR circuit repeats the operation.

CD3268A CD3269A Power-on-reset (POR) Logic SignalFigure 7-3 Power-on-reset (POR) Logic Signal