SCHS469 March 2025 CD4053B-Q1
PRODUCTION DATA
- 1
- 1 Features
- 2 Applications
- 3 Description
- 4 Pin Configuration and Functions
- 5 Specifications
- 6 Parameter Measurement Information
- 7 Detailed Description
- 8 Application and Implementation
- 9 Device and Documentation Support
- 10Revision History
- 11Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
- D|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information
6 Parameter Measurement Information
Figure 6-1 Typical
Bias VoltagesNote:
The ADDRESS (digital-control inputs) and INHIBIT logic levels are: 0 = VSS and 1 = VDD. The analog signal (through the TG) may swing from VEE to VDD.
Figure 6-2 Waveforms, Channel Being
Turned ON (RL = 1kΩ)
Figure 6-3 Waveforms, Channel Being
Turned OFF (RL = 1kΩ)
Figure 6-4 OFF
Channel Leakage Current – Any Channel OFF
Figure 6-5 On Channel Leakage Current –
Any Channel On
Figure 6-6 OFF
Channel Leakage Current – All Channels OFF
Figure 6-7 Propagation Delay – Address Input to Signal Output
Figure 6-8 Propagation Delay – Inhibit Input to Signal Output
Figure 6-9 Input
Voltage Test Circuits (Noise Immunity)
Figure 6-10 Quiescent Device Current
Figure 6-11 Channel ON Resistance Measurement Circuit
Figure 6-12 Input
Current
Figure 6-13 Feed-Through (All Types)
Figure 6-14 Crosstalk Between Any Two Channels (All Types)
Figure 6-15 Crosstalk Between Duals
or Triplets 
Figure 6-16 24-to-1MUX
Addressing