SCHS228E November   1998  – June 2026 CD74AC14

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Description
  4. 3 Pin Configuration and Functions
  5. 4 Specifications
    1. 4.1 Absolute Maximum Ratings
    2. 4.2 Recommended Operating Conditions
    3. 4.3 Thermal Information
    4. 4.4 Electrical Characteristics (PDIP Package)
    5. 4.5 Electrical Characteristics (SOIC package)
    6. 4.6 Switching Characteristics (PDIP Package)
    7. 4.7 Switching Characteristics (SOIC package)
  6. 5 Parameter Measurement Information
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Power Supply Recommendations
    2. 7.2 Layout
      1. 7.2.1 Layout Guidelines
      2. 7.2.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • 1.5V to 5.5V operation and balanced noise immunity at 30% of the supply voltage
  • Speed of bipolar F, AS, and S, with significantly reduced power consumption
  • Greater noise immunity than standard inverters
  • Operates with much slower than standard input rise and fall slew rates
  • Balanced propagation delays
  • ±24mA output drive current − fanout to 15F devices
  • SCR latchup-resistant CMOS process and circuit design