SCHS353A January   2004  – February 2022 CD74HC595

PRODUCTION DATA  

  1. 1 Features
  2. 2 Description
  3. 3 Revision History
  4. 4 Pin Configuration and Functions
    1.     5
  5. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Recommended Operating Conditions (1)
    3. 5.3 Thermal Information
    4. 5.4 Electrical Characteristics
    5. 5.5 Timing Requirements
    6.     12
    7. 5.6 Switching Characteristics
    8. 5.7 Operating Characteristics
  6. 6 Parameter Measurement Information
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Device Functional Modes
  8. 8 Power Supply Recommendations
  9. 9 Layout
    1. 9.1 Layout Guidelines
  10. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DB|16
  • NS|16
  • DW|16
  • N|16
  • D|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.5 Timing Requirements

PARAMETER VCC (V) 25°C -40°C to 85°C -55°C to 125°C UNIT
MIN MAX MIN MAX MIN MAX
HC TYPES
fclock Clock frequency 2 6 5 4.2 MHz
4.5 31 25 21
6 36 29 25
tW Pulse duration SRCLK or RCLK high or low 2 80 100 120 ns
4.5 16 20 24
6 14 17 20
SRCLR low 2 80 100 120
4.5 16 20 24
6 14 17 20
tSU Setup time SER before SRCLK↑ 2 100 125 150 ns
4.5 20 25 30
6 17 21 25
SRCLK↑ before RCLK↑(1) 2 75 94 113
4.5 15 19 23
6 13 16 19
SRCLR low before RCLK↑ 2 50 65 75
4.5 10 13 15
6 9 11 13
SRCLR high (inactive) before SRCLK↑ 2 50 60 75
4.5 10 12 15
6 9 11 13
th Hold time, SER after SRCLK↑ 2 0 0 0 ns
4.5 0 0 0
6 0 0 0
(1) This setup time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which case the shift register is one clock pulse ahead of the storage register.