SCAS878C May   2009  – January 2016 CDCLVP2108

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: LVCMOS Input, at VCC = 2.375 V to 3.6 V
    6. 6.6  Electrical Characteristics: Differential Input, at VCC = 2.375 V to 3.6 V
    7. 6.7  Electrical Characteristics: LVPECL Output, at VCC = 2.375 V to 2.625 V
    8. 6.8  Electrical Characteristics: LVPECL Output, at VCC = 3 V to 3.6 V
    9. 6.9  Timing Requirements, at VCC = 2.375 V to 2.625 V
    10. 6.10 Timing Requirements, at VCC = 3 V to 3.6 V
    11. 6.11 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Test Configurations
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
      1. 8.4.1 LVPECL Output Termination
      2. 8.4.2 Input Termination
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power-Supply Filtering
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Parameter Measurement Information

7.1 Test Configurations

This section describes the function of each block for the CDCLVP2108. Figure 5 through Figure 11 show how the device should be set up for a variety of test configurations.

CDCLVP2108 ai_test_lvcmos_dc_in_cas878.gif Figure 5. DC-Coupled LVCMOS Input During Device Test
CDCLVP2108 ai_vth_var_lvcmos_in_cas878.gif Figure 6. Vth Variation over LVCMOS Levels
CDCLVP2108 ai_test_lvpecl_dc_in_cas878.gif Figure 7. DC-Coupled LVPECL Input During Device Test
CDCLVP2108 ai_test_lvds_dc_in_cas878.gif Figure 8. DC-Coupled LVDS Input During Device Test
CDCLVP2108 ai_test_diff_ac_in_cas878.gif Figure 9. AC-Coupled Differential Input to Device
CDCLVP2108 ai_test_lvpecl_dc_out_cas878.gif Figure 10. LVPECL Output DC Configuration During Device Test
CDCLVP2108 ai_test_lvpecl_ac_out_cas878.gif Figure 11. LVPECL Output AC Configuration During Device Test