SLPS386B September   2012  – January 2016 CSD17551Q3A

PRODUCTION DATA.  

  1. 1Features
  2. 2Applications
  3. 3Description
  4. 4Revision History
  5. 5Specifications
    1. 5.1 Electrical Characteristics
    2. 5.2 Thermal Information
    3. 5.3 Typical MOSFET Characteristics
  6. 6Device and Documentation Support
    1. 6.1 Community Resources
    2. 6.2 Trademarks
    3. 6.3 Electrostatic Discharge Caution
    4. 6.4 Glossary
  7. 7Mechanical, Packaging, and Orderable Information
    1. 7.1 Q3A Package Dimensions
    2. 7.2 Q3A Recommended PCB Pattern
    3. 7.3 Q3A Recommended Stencil Pattern
    4. 7.4 Q3A Tape and Reel Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DNH|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Specifications

5.1 Electrical Characteristics

(TA = 25°C unless otherwise stated)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
STATIC CHARACTERISTICS
BVDSS Drain-to-source voltage VGS = 0 V, ID = 250 μA 30 V
IDSS Drain-to-source leakage current VGS = 0 V, VDS = 24 V 1 μA
IGSS Gate-to-source leakage current VDS = 0V, VGS = 20 V 100 nA
VGS(th) Gate-to-source threshold voltage VDS = VGS, ID = 250 μA 1.1 1.6 2.1 V
RDS(on) Drain-to-source on-resistance VGS = 4.5 V, ID = 11 A 9.6 11.8 mΩ
VGS = 10 V, ID = 11 A 7.8 9 mΩ
gfs Transconductance VDS = 15 V, ID = 11 A 101 S
DYNAMIC CHARACTERISTICS
Ciss Input capacitance VGS = 0 V, VDS = 15 V, ƒ = 1 MHz 1050 1370 pF
Coss Output capacitance 244 317 pF
Crss Reverse transfer capacitance 24 31 pF
RG Series gate resistance 1.5 3 Ω
Qg Gate charge total (4.5 V) VDS = 15 V, ID = 11 A 6 7.8 nC
Qgd Gate charge gate to drain 1.5 nC
Qgs Gate charge gate to source 2.3 nC
Qg(th) Gate charge at Vth 1.4 nC
Qoss Output charge VDS = 15 V, VGS = 0 V 7.4 nC
td(on) Turn on delay time VDS = 15 V, VGS = 4.5 V,
IDS = 11 A, RG = 2 Ω		 8 ns
tr Rise time 24 ns
td(off) Turn off delay time 12 ns
tf Fall time 3.4 ns
DIODE CHARACTERISTICS
VSD Diode forward voltage ISD = 11 A, VGS = 0 V 0.8 1 V
Qrr Reverse recovery charge VDS= 13.5 V, IF = 11 A,
di/dt = 300 A/μs		 13 nC
trr Reverse recovery time 14 ns

5.2 Thermal Information

(TA = 25°C unless otherwise stated)
THERMAL METRIC MIN TYP MAX UNIT
RθJC Junction-to-case thermal resistance(1) 3.9 °C/W
RθJA Junction-to-ambient thermal resistance (1)(2) 60 °C/W
(1) RθJC is determined with the device mounted on a 1 inch2 (6.45 cm2), 2 oz. (0.071 mm thick) Cu pad on a 1.5 inches × 1.5 inches
(3.81 cm × 3.81 cm), 0.06 inch (1.52 mm) thick FR4 PCB. RθJC is specified by design, whereas RθJA is determined by the user’s board design.
(2) Device mounted on FR4 material with 1 inch2 (6.45 cm2), 2 oz. (0.071 mm thick) Cu.
CSD17551Q3A m0161-01_lps202.gif
Max RθJA = 60°C/W when mounted on 1 inch2 (6.45 cm2) of
2 oz. (0.071 mm thick) Cu.
CSD17551Q3A m0161-02_lps202.gif
Max RθJA = 144°C/W when mounted on a minimum pad area of 2 oz. (0.071 mm thick) Cu.

5.3 Typical MOSFET Characteristics

(TA = 25°C unless otherwise stated)
CSD17551Q3A graph01_SLPS386.png
Figure 1. Transient Thermal Impedance
CSD17551Q3A graph02_SLPS386.png
Figure 2. Saturation Characteristics
CSD17551Q3A graph04p2_SLPS386.png
Figure 4. Gate Charge
CSD17551Q3A graph06_SLPS386.png
Figure 6. Threshold Voltage vs Temperature
CSD17551Q3A graph08_SLPS386.png
Figure 8. Normalized On-State Resistance vs Temperature
CSD17551Q3A graph10p3_SLPS386.png
Figure 10. Maximum Safe Operating Area
CSD17551Q3A graph12_SLPS386.png
Figure 12. Maximum Drain Current vs Temperature
CSD17551Q3A graph03_SLPS386.png
Figure 3. Transfer Characteristics
CSD17551Q3A graph05_SLPS386.png
Figure 5. Capacitance
CSD17551Q3A graph07p2_SLPS386.png
Figure 7. On-State Resistance vs Gate-to-Source Voltage
CSD17551Q3A graph09_SLPS386.png
Figure 9. Typical Diode Forward Voltage
CSD17551Q3A graph11_SLPS386.png
Figure 11. Single Pulse Unclamped Inductive Switching