SLPS525A September   2014  – January 2016 CSD17578Q3A

PRODUCTION DATA.  

  1. 1Features
  2. 2Applications
  3. 3Description
  4. 4Revision History
  5. 5Specifications
    1. 5.1 Electrical Characteristics
    2. 5.2 Thermal Information
    3. 5.3 Typical MOSFET Characteristics
  6. 6Device and Documentation Support
    1. 6.1 Community Resources
    2. 6.2 Trademarks
    3. 6.3 Electrostatic Discharge Caution
    4. 6.4 Glossary
  7. 7Mechanical, Packaging, and Orderable Information
    1. 7.1 Q3A Package Dimensions
    2. 7.2 Q3A Recommended PCB Pattern
    3. 7.3 Q3A Recommended Stencil Pattern
    4. 7.4 Q3A Tape and Reel Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DNH|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Specifications

5.1 Electrical Characteristics

(TA = 25°C unless otherwise stated)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
STATIC CHARACTERISTICS
BVDSS Drain-to-Source Voltage VGS = 0 V, ID = 250 μA 30 V
IDSS Drain-to-Source Leakage Current VGS = 0 V, VDS = 24 V 1 μA
IGSS Gate-to-Source Leakage Current VDS = 0 V, VGS = 20 V 100 nA
VGS(th) Gate-to-Source Threshold Voltage VDS = VGS, ID = 250 μA 1.1 1.5 1.9 V
RDS(on) Drain-to-Source
On-Resistance		 VGS = 4.5 V, ID = 10 A 8.2 9.4 mΩ
VGS = 10 V, ID = 10 A 6.3 7.3 mΩ
gfs Transconductance VDS = 3 V, ID = 10 A 48 S
DYNAMIC CHARACTERISTICS
Ciss Input Capacitance VGS = 0 V, VDS = 15 V, ƒ = 1 MHz 1150 1590 pF
Coss Output Capacitance 134 174 pF
Crss Reverse Transfer Capacitance 56 73 pF
RG Series Gate Resistance 1.8 3.6 Ω
Qg Gate Charge Total (4.5 V) VDS = 15 V, ID = 10 A 7.9 10.3 nC
Qg Gate Charge Total (10 V) 17.1 22.2
Qgd Gate Charge Gate-to-Drain 1.7 nC
Qgs Gate Charge Gate-to-Source 3.3 nC
Qg(th) Gate Charge at Vth 1.6 nC
Qoss Output Charge VDS = 15 V, VGS = 0 V 4.2 nC
td(on) Turn On Delay Time VDS = 15 V, VGS = 10 V,
IDS = 10 A, RG = 0 Ω		 2 ns
tr Rise Time 6 ns
td(off) Turn Off Delay Time 13 ns
tf Fall Time 1 ns
DIODE CHARACTERISTICS
VSD Diode Forward Voltage ISD = 10 A, VGS = 0 V 0.8 1.0 V
Qrr Reverse Recovery Charge VDS= 15 V, IF = 10 A,
di/dt = 300 A/μs		 4.4 nC
trr Reverse Recovery Time 6 ns

5.2 Thermal Information

(TA = 25°C unless otherwise stated)
THERMAL METRIC MIN TYP MAX UNIT
RθJC Junction-to-Case Thermal Resistance (1) 4.2 °C/W
RθJA Junction-to-Ambient Thermal Resistance(1)(2) 60
(1) RθJC is determined with the device mounted on a 1 inch2 (6.45 cm2), 2 oz. (0.071 mm thick) Cu pad on a 1.5 inches × 1.5 inches
(3.81 cm × 3.81 cm), 0.06 inch (1.52 mm) thick FR4 PCB. RθJC is specified by design, whereas RθJA is determined by the user’s board design.
(2) Device mounted on FR4 material with 1 inch2 (6.45 cm2), 2 oz. (0.071 mm thick) Cu.
CSD17578Q3A m0161-01_lps202.gif
Max RθJA = 60°C/W when mounted on 1 inch2 (6.45 cm2) of
2-oz. (0.071-mm thick) Cu.
CSD17578Q3A m0161-02_lps202.gif
Max RθJA = 145°C/W when mounted on a minimum pad area of 2-oz. (0.071-mm thick) Cu.

5.3 Typical MOSFET Characteristics

(TA = 25°C unless otherwise stated)
CSD17578Q3A D001_SLPS525_mod3.png
Figure 1. Transient Thermal Impedance
CSD17578Q3A D002_SLPS525.gif
Figure 2. Saturation Characteristics
CSD17578Q3A D004_SLPS525.gif
ID = 10 A VDS = 15 V
Figure 4. Gate Charge
CSD17578Q3A D006_SLPS525.gif
ID = 250 µA
Figure 6. Threshold Voltage vs Temperature
CSD17578Q3A D008_SLPS525.gif
ID = 10 A
Figure 8. Normalized On-State Resistance vs Temperature
CSD17578Q3A D010_SLPS525.gif
Single Pulse,
Max RθJC = 4.2°C/W
Figure 10. Maximum Safe Operating Area (SOA)
CSD17578Q3A D012_SLPS525.gif
Figure 12. Maximum Drain Current vs Temperature
CSD17578Q3A D003_SLPS525.gif
VDS = 5 V
Figure 3. Transfer Characteristics
CSD17578Q3A D005_SLPS525.gif
Figure 5. Capacitance
CSD17578Q3A D007_SLPS525.gif
Figure 7. On-State Resistance vs Gate-to-Source Voltage
CSD17578Q3A D009_SLPS525.gif
Figure 9. Typical Diode Forward Voltage
CSD17578Q3A D011_SLPS525.gif
Figure 11. Single Pulse Unclamped Inductive Switching