SLPS690B August   2017  – February 2022 CSD22205L

PRODUCTION DATA  

  1. 1Features
  2. 2Applications
  3. 3Description
  4. 4Revision History
  5. 5Specifications
    1. 5.1 Electrical Characteristics
    2. 5.2 Thermal Information
    3. 5.3 Typical MOSFET Characteristics
  6. 6Device and Documentation Support
    1. 6.1 Receiving Notification of Documentation Updates
    2. 6.2 Trademarks
  7. 7Mechanical, Packaging, and Orderable Information
    1. 7.1 CSD22205L Package Dimensions
    2. 7.2 Land Pattern Recommendation
    3. 7.3 Stencil Recommendation

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • YMG|4
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Description

This –8-V, 8.2-mΩ, 1.2-mm × 1.2-mm Land Grid Array (LGA) NexFET™ device has been designed to deliver the lowest on-resistance and gate charge in the smallest outline possible with excellent thermal characteristics in an ultra-low profile. The Land Grid Array (LGA) package is a silicon chip scale package with metal pads instead of solder balls.

GUID-20220215-SS0I-J8SQ-MVVT-X3NNF9TZ4LQ1-low.gif RDS(on) vs VGS
GUID-20220215-SS0I-M6BF-BCTD-JNT26WDKJHDJ-low.gif RDS(on) vs VGS
Product Summary
TA = 25°CVALUEUNIT
VDSDrain-to-Source Voltage–8V
QgGate Charge Total (–4.5 V)6.5nC
QgdGate Charge Gate-to-Drain1.0nC
RDS(on)Drain-to-Source On-ResistanceVGS = –1.5 V30mΩ
VGS = –1.8 V20
VGS = –2.5 V11.5
VGS = –4.5 V8.2
VGS(th)Threshold Voltage–0.7V
Device Information(1)
DEVICEQTYMEDIAPACKAGESHIP
CSD22205L30007-Inch Reel1.20-mm × 1.20-mm
Land Grid Array
Package
Tape and Reel
CSD22205LT250
For all available packages, see the orderable addendum at the end of the data sheet.
Absolute Maximum Ratings
TA = 25°CVALUEUNIT
VDSDrain-to-Source Voltage–8V
VGSGate-to-Source Voltage–6V
IDContinuous Drain Current(1)–7.4A
IDMPulsed Drain Current(2)–71A
PDPower Dissipation(1)0.6W
TJ,
Tstg
Operating Junction Temperature,
Storage Temperature
–55 to 150°C
Min Cu RθJA = 225°C/W.
Pulse width ≤ 100 μs, duty cycle ≤ 1%.
GUID-20220215-SS0I-DKK9-H9FJ-MRZCHRVJ1SPS-low.gif Figure 3-1 Top View and Circuit Configuration