SLPS570 November   2015 CSD25404Q3

PRODUCTION DATA.  

  1. 1Features
  2. 2Applications
  3. 3Description
  4. 4Revision History
  5. 5Specifications
    1. 5.1 Electrical Characteristics
    2. 5.2 Thermal Information
    3. 5.3 Typical MOSFET Characteristics
  6. 6Device and Documentation Support
    1. 6.1 Community Resources
    2. 6.2 Trademarks
    3. 6.3 Electrostatic Discharge Caution
    4. 6.4 Glossary
  7. 7Mechanical, Packaging, and Orderable Information
    1. 7.1 CSD25404Q3 Package Dimensions
    2. 7.2 Recommended PCB Pattern
    3. 7.3 Recommended Stencil Opening
    4. 7.4 Q3 Tape and Reel Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DQG|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Specifications

5.1 Electrical Characteristics

(TA = 25°C unless otherwise stated)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
STATIC CHARACTERISTICS
BVDSS Drain-to-source voltage VGS = 0 V, ID = –250 μA –20 V
IDSS Drain-to-source leakage current VGS = 0 V, VDS = –16 V –1 μA
IGSS Gate-to-source leakage current VDS = 0 V, VGS = ±12 V –100 nA
VGS(th) Gate-to-source threshold voltage VDS = VGS, ID = –250 μA –0.65 –0.90 –1.15 V
RDS(on) Drain-to-source on resistance VGS = –1.8 V, ID = –1 A 40 150 mΩ
VGS = –2.5 V, ID = –10 A 10.1 12.1 mΩ
VGS = –4.5 V, ID = –10 A 5.5 6.5 mΩ
gfs Transconductance VDS = –10 V, ID = –10 A 47 S
DYNAMIC CHARACTERISTICS
CISS Input capacitance VGS = 0 V, VDS = –10 V,
ƒ = 1 MHz		 1630 2120 pF
COSS Output capacitance 902 1170 pF
CRSS Reverse transfer capacitance 52 68 pF
RG Series gate resistance 0.8 2.4 Ω
Qg Gate charge total (–4.5 V) VDS = –10 V, ID = –10 A 10.8 14.1 nC
Qgd Gate charge gate to drain 2.2 nC
Qgs Gate charge gate to source 2.8 nC
Qg(th) Gate charge at Vth 1.5 nC
QOSS Output charge VDS = –10 V, VGS = 0 V 9.0 nC
td(on) Turn on delay time VDS = –10 V, VGS = –4.5 V,
ID = –10 A , RG = 5 Ω		 13 ns
tr Rise time 8 ns
td(off) Turn off delay time 35 ns
tf Fall time 13 ns
DIODE CHARACTERISTICS
VSD Diode forward voltage IS = –10 A, VGS = 0 V –0.8 –1 V
Qrr Reverse recovery charge VDS = –10 V, IF = –10 A,
di/dt = 200 A/μs		 20.5 nC
trr Reverse recovery time 26 ns

5.2 Thermal Information

(TA = 25°C unless otherwise stated)
THERMAL METRIC MIN TYP MAX UNIT
RθJC Junction-to-case thermal resistance(1) 1.3 °C/W
RθJA Junction-to-ambient thermal resistance(1)(2) 55 °C/W
(1) RθJC is determined with the device mounted on a 1 inch2 (6.45 cm2), 2 oz. (0.071 mm thick) Cu pad on a 1.5 inch × 1.5 inch (3.81 cm × 3.81 cm), 0.06 inch (1.52 mm) thick FR4 PCB. RθJC is specified by design, whereas RθJA is determined by the user’s board design.
(2) Device mounted on FR4 material with 1 inch2 (6.45 cm2), 2 oz. (0.071 mm thick) Cu.
CSD25404Q3 m0137-01_lps211.gif
Max RθJA = 55°C/W when mounted on
1 inch2 of 2 oz. Cu.
CSD25404Q3 m0137-02_lps211.gif
Max RθJA = 160°C/W when mounted on minimum pad area of
2 oz. Cu.

5.3 Typical MOSFET Characteristics

(TA = 25°C unless otherwise stated)
CSD25404Q3 D001_SLPS570.png
Figure 1. Transient Thermal Impedance
CSD25404Q3 D002_SLPS570.gif
Figure 2. Saturation Characteristics
CSD25404Q3 D004_SLPS570.gif
ID = –10 A VDS = –10 V
Figure 4. Gate Charge
CSD25404Q3 D006_SLPS570.gif
ID = –250 µA
Figure 6. Threshold Voltage vs Temperature
CSD25404Q3 D008_SLPS570.gif
ID = –10 A
Figure 8. Normalized On-State Resistance vs Temperature
CSD25404Q3 D010_SLPS570_r2.gif
Single Pulse, Max RθJC = 1.3 °C/W
Figure 10. Maximum Safe Operating Area
CSD25404Q3 D003_SLPS570.gif
VDS = –5 V
Figure 3. Transfer Characteristics
CSD25404Q3 D005_SLPS570.gif
Figure 5. Capacitance
CSD25404Q3 D007_SLPS570.gif
Figure 7. On-State Resistance vs Gate-to-Source Voltage
CSD25404Q3 D009_SLPS570.gif
Figure 9. Typical Diode Forward Voltage
CSD25404Q3 D011_SLPS570_r2.gif
Figure 11. Maximum Drain Current vs Temperature